SAMSUNG S3P70F4

S3C70F2/C70F4/P70F4
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The S3P70F4 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the
same to S3C70F2/C70F4. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and
its versatile 8-bit timer/counter, the S3C70F2/C70F4 offers an excellent design solution for a wide variety of
general-purpose applications.
Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response
to internal and external events. In addition, the S3C70F2/C70F4's advanced CMOS technology provides for very
low power consumption and a wide operating voltage range — all at a very low cost.
1-1
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
FEATURES SUMMARY
Memory
•
512 × 4-bit data memory (RAM)
•
2048 × 8-bit program memory (ROM):S3C70F2
4096 × 8-bit program memory (ROM):S3C70F4
Bit Sequential Carrier
•
Supports 16-bit serial data transfer in arbitrary
format
Interrupts
24 I/O Pins
•
Two external interrupt vectors
•
I/O: 18 pins, including 8 high current pins
•
Three internal interrupt vectors
•
Input only: 6 pins
•
Two quasi-interrupts
Comparator
Memory-Mapped I/O Structure
•
4-channel mode:
Internal reference (4-bit resolution)
16-step variable reference voltage
•
3-channel mode:
External reference
150 mV resolution (worst case)
•
Idle mode: Only CPU clock stops
•
Stop mode: System clock stops
•
8-bit Basic Timer
•
Programmable interval timer
•
Watch-dog timer
8-bit Timer/Counter 0
•
Programmable interval timer
•
External event counter function
Timer/counter clock output to TCLO0 pin
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms at 4.19
MHz
•
4 frequency outputs to BUZ pin
8-bit Serial I/O Interface
Data memory bank 15
Two Power-Down Modes
OSCILLATION SOURCES
•
Crystal, Ceramic for system clock
•
Crystal/ceramic: 0.4 - 6.0 MHz
•
CPU clock divider circuit (by 4. 8, or 64)
Instruction Execution Times
•
0.95, 1.91, 15.3 µs at 4.19 MHz
•
0.67, 1.33, 10.7 µs at 6.0 MHz
Operating Temperature
•
– 40 °C to 85 °C
Operating Voltage Range
•
1.8 V to 5.5 V
•
8-bit transmit/receive mode
•
8-bit receive-only mode
Package Type
•
LSB-first or MSB-first transmission selectable
•
•
Internal or external clock source
1-2
30 SDIP, 32 SOP
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU
All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical,
and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two
cycles.
CPU REGISTERS
Program Counter
A 11-bit program counter (PC) stores addresses for instruction fetch during program execution. Usually, the PC is
incremented by the number of bytes of the instruction being fetched. An exception is the 1-byte instruction REF
which is used to reference instructions stored in a look-up table in the ROM. Whenever a reset operation or an
interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC13–12 is reserved to support future
expansion of the device's ROM size.
Stack Pointer
An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in the generalpurpose data memory bank 0. The SP is read or written by 8-bit instructions and SP bit 0 must always be set to
logic zero.
During an interrupt or a subroutine call, the PC value and the program status word (PSW) are saved to the stack
area in RAM. When the service routine has completed, the values referenced by the stack pointer are restored.
Then, the next instruction is executed.
The stack pointer can access the stack regardless of data memory access enable flag status. Since the reset
value of the stack pointer is not defined in firmware, it is recommended that the stack pointer be initialized to 00H
by program code. This sets the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 4096 × 8-bit ROM is divided into three functional areas:
— 16-byte area for vector addresses
— 96-byte instruction reference area
— 1920-byte general purpose area (S3C70F2)
— 3968-byte general purpose area (S3C70F4)
The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be used
as general-purpose ROM.
The REF instruction references 2 × 1-byte and 2-byte instructions stored in locations 0020H–007FH. The REF
instruction can also reference 3-byte instructions such as JP or CALL. In order for REF to be able to reference
these instructions, however, JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written
to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in
the instruction reference area can be allocated to general-purpose use.
1-3
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
DATA MEMORY
Overview
Data memory is organized into three areas:
— 32 × 4-bit working registers
— 224 × 4-bit general-purpose area in bank 0
— 256 × 4-bit general-purpose area in bank 1
— 128 × 4-bit area in bank 15 for memory-mapped I/O addresses
Data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions.
Data memory is organized into two memory banks — bank 0, bank 1 and bank 15. The select memory bank instruction (SMB) selects the bank to be used as working data memory. After power-on reset operation,
initialization values for data memory must be redefined by code.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15.
When the EMB flag is logic zero, restricted area can be accessed. When the EMB flag is set to logic one, all two
data memory banks can be accessed according to the current SMB value. The EMB = "0" addressing mode is
used for normal program execution, whereas the EMB = "1" mode is commonly used for interrupts, subroutines,
mapped I/O, and repetitive access of specific RAM addresses.
Working Registers
The RAM's working register area in data memory bank 0 is further divided into four register banks. Each register
bank has eight 4-bit registers that are addressable either by 1-bit or 4-bit instructions. Paired 4-bit registers can
be addressed as double registers by 8-bit instructions.
Register A is the 4-bit accumulator and double register EA is the 8-bit extended accumulator. Double registers
WX, WL, and HL are used as data pointers for indirect addressing. Unused working registers can be used as
general-purpose memory.
To limit the possibility of data corruption due to incorrect register bank addressing, register bank 0 is usually used
for the main program and banks 1, 2, and 3 for interrupt service routines.
1-4
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory enable flags.
Before an interrupt or subroutine is processed, the PSW values are pushed onto the stack in data memory bank
0. When the service routine is completed, the PSW values are restored.
IS1
IS0
EMB
ERB
C
SC2
SC1
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. You can address the skip condition flags
(SC0–SC2) using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit registers store address values used to access specific memory and register banks: the select memory
bank register, SMB, and the select register bank register, SRB.
'SMB n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory
address in the SMB register. To select register bank 0, 1, 2, or 3, and store the address data in the SRB, you can
use the instruction 'SRB n'.
The instructions "PUSH SB" and "POP SB" move SRB and SMB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware.
The system clock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. To
drive S3C70F2/C70F4 using an external clock source, the external clock signal should be input to Xin, and its
inverted signal to Xout.
4-bit power control register controls the oscillation on/off, and select the CPU clock. The internal system clock
signal (fx) can be divided internally to produce three CPU clock frequencies — fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, and INTS) or externally by
peripheral devices (INT0 and INT1). There are two quasi-interrupts: INTK and INTW. INTK (KS0–KS2) detects
falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds. The
following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1-5
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
POWER-DOWN
To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode; the STOP instruction initiates stop mode.
In idle mode, the CPU clock stops while peripherals continue to operate normally. In stop mode, system clock
oscillation stops completely, halts all operations except for a few basic peripheral functions. A power-down is
terminated either by a RESET or by an interrupt (with exception of the external interrupt INT0).
RESET
When RESET is input during normal operation or during power-down mode, a reset operation is initiated and the
CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
I/O PORTS
The S3C70F2/C70F4 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FF6H
in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins for a
total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding
address using bit manipulation instructions.
TIMERS and TIMER/COUNTER
The timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer.
The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock
frequency.
The programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and
dividing external clock signals. The 8-bit timer/counter generates a clock signal (SCK) for the serial I/O interface.
The watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit.
Its functions include real-time, watch-time measurement, and clock generation for frequency output for buzzer
sound.
SERIAL I/O INTERFACE
The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:
— 8-bit mode register
— Clock selector circuit
— 8-bit buffer register
— 3-bit serial clock counter
The serial I/O circuit can be set to transmit-and-receive, or to receive-only mode. MSB-first or LSB-first
transmission is also selectable.
The serial interface can operate with an internal or an external clock source, or using the clock signal generated
by the 8-bit timer/counter. Transmission frequency can be modified by setting the appropriate bits in the SIO
mode register.
1-6
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
BIT SEQUENTIAL CARRIER
The bit sequential carrier (BSC) is a 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions.
Using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. In this way, programs
can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value
of the L register. BSC data can also be manipulated using direct addressing.
COMPARATOR
The S3C70F2/C70F4 contains a 4-channel comparator which can be multiplexed to normal input port.
— Conversion time: 15.2 µs, 121.6 µs at 4.19 MHz
— Two operation modes:
Three channels for analog input and one channel for external reference voltage input
Four channels for analog input and internal reference voltage level
— 16-level internal reference voltage generator
— 150 mV accuracy for input voltage level difference detection (maximum)
— Comparator enable and disable
The comparison results are read from the 4-bit CMPREG register after the specified conversion time.
1-7
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
BLOCK DIAGRAM
Basic Timer
RESET
XIN
Watch Timer
XOUT
8-Bit
Timer/Counter
I/O Port 0
Interrupt
Control
Block
P3.0/TCL0
P3.1/TCLO0
P3.2/CLO
Clock
Serial I/O Port
I/O Port 3
Internal
Interrupts
P4.0 - P4.3
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
Program
Counter
Input Port 1
P0.0/SCK
P0.1/SO
P0.2/SI
Input Port 2
P2.0/KS0/CIN0
P2.1/KS1/CIN1
P2.2/KS2/CIN2
P2.3/KS3/CIN3
I/O Port 4
Instruction Decoder
P5.0 - P5.3
Stack
Pointer
I/O Port 5
Arithmetic
and
Logic Unit
Program
Status Word
Flags
I/O Port 6
512 x 4-Bit
Data
Memory
Comparator
Program Memory
KS57C01502: 2 KByte
KS57C01504: 4 KByte
Figure 1-1. S3C70F2/C70F4 Simplified Block Diagram
1-8
P0.0/CLO
P0.1/TIO
P0.2/INT1
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
PIN ASSIGNMENTS
VSS
Xout
Xin
TEST
P1.0/INT0
P1.1/INT1
RESET
P0.0/SCK
P0.1./SO
P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VSS
Xout
Xin
TEST
P1.0/INT0
P1.1/INT1
RESET
NC
P0.0/SCK
P0.1./SO
P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S3C70F2
S3C70F4
(Top View)
30-SDIP
S3C70F2
S3C70F4
(Top View)
30-SDIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
VDD
P6.3/BUZ
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.2/CLO
P3.1/TCLO0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P6.3/BUZ
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
NC
P3.2/CLO
P3.1/TCLO0
Figure 1-2. S3C70F2/C70F4 Pin Assignment Diagram
1-9
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
PIN DESCRIPTIONS
Table 1-1. S3C70F2/C70F4 Pin Descriptions
Pin Name
Pin
Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
I/O
3-bit I/O port. 1-bit or 3-bit read/write and test are
possible. Pull-up resistors are assignable to input pins by
software and are automatically disabled for output pins.
Pins are individually configurable as input or output.
8(9)
9(10)
10(11)
SCK
SO
SI
P1.0
P1.1
I
2-bit input port. 1-bit or 2-bit read and test are possible.
Pull-up resistors are assignable by software.
5(5)
6(6)
INT0
INT1
P2.0–P2.3
I
4-bit input port. 1-bit or 4-bit read and test are possible.
11-14
(12-15)
CIN0–CIN3
P3.0
P3.1
P3.2
I/O
Same as port 0
15(16)
16(17)
17(18)
TCL0
TCLO0
CLO
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O ports. 1-, 4-, or 8-bit read/write and test are
possible. Pins are individually configurable as input or
output. 4-bit pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. The N-channel open-drain or push-pull output can
be selected by software (1-bit unit)
18-21(20-23)
22-25(24-27)
–
P6.0
P6.1
P6.2
P6.3
I/O
4-bit I/O port.
1-bit or 4-bit read/write and test are possible.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins. Pins are
individually configurable as input or output.
26(28)
27(29)
28(30)
29(31)
KS0
KS1
KS2
BUZ
INT0
I
External interrupts with detection of rising and falling
edges
5(5)
P1.0
INT1
I
External interrupts with detection of rising or falling
edges
6(6)
P1.1
CIN0–CIN3
I
4-channel comparator input.
CIN0–CIN2: comparator input only.
CIN3: comparator input or external reference input
11-14(12-15)
P2.0–P2.3
SCK
I/O
Serial interface clock signal
8(9)
P0.0
SO
I/O
Serial data output
9(10)
P0.1
SI
I/O
Serial data input
10(11)
P0.2
TCL0
I/O
External clock input for timer/counter
15(16)
P3.0
TCLO0
I/O
Timer/counter clock output
16(17)
P3.1
CLO
I/O
CPU clock output
17(18)
P3.2
BUZ
I/O
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19
MHz for buzzer sound
29(31)
P6.3
NOTE: Pn numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
1-10
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
Table 1-1. S3C70F2/C70F4 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Quasi-interrupt input with falling edge detection
Number
Share Pin
26-28(28-30)
P6.0–P6.2
30(32)
—
VDD
—
Main power supply
VSS
—
Ground
1(1)
—
RESET
I
Reset signal
7(7)
—
TEST
I
Test signal input (must be connected to VSS)
4(4)
—
Xin, Xout
—
3,2(3,2)
—
Crystal or ceramic oscillator signal for system clock
NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
Table 1-2. Overview of S3C70F2/C70F4 Pin Data
SDIP Pin
Numbers
Pin
Names
Share
Pins
I/O
Type
Reset
Value
Circuit
Type
1
VSS




2,3
Xout, Xin




4
TEST

I


5,6
P1.0, P1.1
INT0, INT1
I
Input
A-3
7
RESET

I

B
8-10
P0.0 - P0.2
SCK, SO, SI
I/O
Input
D-1
11-14
P2.0 - P2.3
CIN0 - CIN3
I
Input
F-1, F-2 (note)
15-17
P3.0 - P3.2
TCL0, TCLO0,
CLO
I/O
Input
D-1
18-21
P4.0 - P4.3

I/O
Input
E
22-25
P5.0 - P5.3

I/O
Input
E
26-29
P6.0 - P6.3
KS0, KS1, KS2,
BUZ
I/O
Input
D-1
30
VDD




NOTE: I/O circuit type F-2 is implemented for P2.3 only.
1-11
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
PIN CIRCUIT DIAGRAMS
VDD
VDD
PULL-UP
RESISTOR
P-CHANNEL
IN
IN
N-CHANNEL
SCHMITT TRIGGER
Figure 1-5. Pin Circuit Type B
Figure 1-3. Pin Circuit Type A
VDD
VDD
PULL-UP
RESISTOR
P-CHANNEL
DATA
P-CHANNEL
RESISTOR
ENABLE
OUT
N-CHANNEL
OUTPUT
DISABLE
IN
SCHMITT TRIGGER
Figure 1-4. Pin Circuit Type A-3
1-12
Figure 1-6. Pin Circuit Type C
KS57C01502/C01504/P01504
PRODUCT OVERVIEW
VDD
PULL-UP
RESISTOR
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
P-CHANNEL
CIRCUIT
TYPE 4
DIGITAL INPUT
I/O
ANALOG INPUT
SCHMITT TRIGER
Figure 1-7. Pin Circuit Type D-1
Figure 1-9. Pin Circuit Type F-1
VDD
PNE
VDD
DATA
PULL-UP
RESISTOR
DIGITAL INPUT
PULL-UP
RESISTOR
ENABLE
P - CHANNEL
ANALOG INPUT
I/O
OUTPUT
DISABLE
N- CHANNEL
EXTERNAL VREF
Figure 1-8. Pin Circuit Type E
Figure 1-10. Pin Circuit Type F-2
1-13
PRODUCT OVERVIEW
KS57C01502/C01504/P01504
NOTES
1-14
S3C70F2/C70F4/P70F4
14
ELECTRICAL DATA
ELECTRICAL DATA
Table 14-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
VDD
–
Input Voltage
VI
Output Voltage
VO
Output Current High
I OH
Output Current Low
I OL
Rating
All I/O ports
–
Units
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
One I/O port active
–5
mA
All I/O ports active
– 15
Ports 0, 3, and 6
5
Ports 4 and 5
30
All ports, total
+ 100
mA
Operating Temperature
TA
–
– 40 to + 85
°C
Storage Temperature
Tstg
–
– 65 to + 150
°C
Table 14-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input High
Voltage
Input Low
Voltage
Output High
Voltage
Symbol
Conditions
Min
Typ
Max
Units
V
VIH1
Ports 4 and 5
0.7VDD
–
VDD
VIH2
Ports 0, 1, 2, 3, 6, and RESET
0.8VDD
–
VDD
VIH3
XIN and XOUT
VDD – 0.1
–
VDD
VIL1
Ports 4 and 5
–
–
0.3VDD
VIL2
Ports 0, 1, 2, 3, 6, and RESET
VIL3
XIN and XOUT
VOH
VDD = 4.5 V to 5.5 V
V
0.2VDD
0.1
VDD - 1.0
–
–
V
IOH = – 1 mA
Ports 0, 3, 4, 5, 6
14-1
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Output Low
Voltage
Symbol
VOL
Conditions
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Min
Typ
Max
Units
–
–
2
V
–
2
–
3
Ports 4, 5
VDD = 4.5V to 5.5 V
IOL = 4.0mA
All output pins except Ports 4, 5
Input High
Leakage
Current
Input Low
Leakage
Current
ILIH1
VIN = VDD
All input pins except XIN and XOUT
ILIH2
VIN = VDD
XIN and XOUT
ILIL1
VIN = 0 V
All input pins except XIN, XOUT
–
µA
20
–
–
–3
µA
and RESET
ILIL2
VIN = 0 V
XIN and XOUT
Output High
Leakage
Current
ILOH
VO = VDD
All output pins
–
–
3
µA
Output Low
Leakage
Current
ILOL
VO = 0 V
–
–
–3
µA
Pull-Up
Resistor
RL1
VI = 0 V; VDD = 5 V
Port 0, 1, 3, 4, 5, 6
25
50
100
kΩ
VDD = 3 V
50
100
200
VDD = 5 V; VI = 0 V; RESET
100
250
400
VDD = 3 V
200
500
800
RL2
14-2
– 20
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Symbol
IDD1
Current (1)
IDD2
IDD3
Conditions
Min
Typ
Max
–
3.0
8.0
Run mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
2.0
5.5
VDD = 3 V ± 10%
6.0MHz
1.3
4.0
4.19MHz
1.0
3.0
0.8
2.5
Idle mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
0.6
1.8
VDD = 3 V ± 10%
6.0MHz
0.6
1.5
4.19MHz
0.4
1.0
0.5
3.0
0.3
2.0
–
Stop mode; VDD = 5.0 V ± 10%
–
Stop mode; VDD = 3.0 V ± 10%
Units
mA
mA
µA
NOTES:
1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resistor,
2.
output port drive currents and comparator.
The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 )
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
4.2 MHz
15.625 kHz
400 kHz
1
2
2.7
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
14-3
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-3. Oscillators Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
Xin
Xout
C1
Crystal
Oscillator
Xin
External
Clock
Xin
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 1.8 V to 5.5 V
0.4
–
4.2
–
–
4
ms
MHz
C2
Xout
C1
Parameter
Stabilization time (2)
VDD = 3.0 V
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 1.8 V to 5.5 V
0.4
–
4.2
–
–
10
ms
MHz
C2
Xout
Stabilization time (2)
VDD = 3.0 V
XIN input frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 1.8 V to 5.5 V
0.4
–
4.2
–
83.3
–
1250
XIN input high and low
level width (tXH, tXL)
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-4
ns
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-4. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
15
pF
CIO
15
pF
I/O Capacitance
Table 14-5. Comparator Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5V, VSS = 0 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
–
–
0
–
VDD
V
Reference Voltage
Range
VREF
–
0
–
VDD
V
Input Voltage Accuracy
VCIN
–
–
–
±150
mV
Input Leakage Current
ICIN, IREF
–
–3
–
3
µA
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
0.95
VDD = 2.7 V to 5.5 V
0
–
1.5
MHz
1
MHz
–
–
µs
–
–
ns
Input Voltage Range
Table 14-6. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction Cycle
Symbol
tCY
Time
TCL0 Input
f TI
VDD = 1.8 V to 5.5 V
Frequency
TCL0 Input High,
tTIH, tTIL
Low Width
SCK Cycle Time
Conditions
tKCY
VDD = 2.7 V to 5.5 V
0.48
VDD = 1.8 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
800
External SCK source
Internal SCK source
670
VDD = 1.8 V to 5.5 V
3200
External SCK source
Internal SCK source
3800
14-5
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-6. A.C. Electrical Characteristics ( Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
SCK High, Low
Width
Symbol
tKH, tKL
Conditions
VDD = 2.7 V to 5.5 V
Min
Typ
Max
Units
335
–
–
ns
–
–
ns
–
–
ns
–
300
ns
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
tKCY/2 – 50
1600
External SCK source
Internal SCK source
SI Setup Time to
SCK High
tSIK
VDD = 2.7 V to 5.5 V
tKCY/2 – 150
100
External SCK source
Internal SCK source
150
VDD = 1.8 V to 5.5 V
150
External SCK source
SI Hold Time to
SCK High
tKSI
Internal SCK source
500
VDD = 2.7 V to 5.5 V
400
External SCK source
Internal SCK source
400
VDD = 1.8 V to 5.5 V
600
External SCK source
Internal SCK source
Output Delay for
SCK to SO
tKSO (1)
VDD = 2.7 V to 5.5 V
500
–
External SCK source
Internal SCK source
250
VDD = 1.8 V to 5.5 V
1000
External SCK source
Internal SCK source
Interrupt Input
High, Low Width
RESET Input
Low Width
tINTH,
tINTL
tRSL
1000
INT0
(2)
INT1, KS0–KS2
10
Input
10
–
–
µs
–
–
µs
NOTES:
1. R (1 Kohm) and C (100 pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
14-6
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.8
–
5.5
V
Data retention supply current
IDDDR
–
0.1
10
µA
Release signal set time
tSREL
–
–
µs
–
ms
–
ms
Oscillator stabilization wait
time (1)
tWAIT
VDDDR = 1.8 V
–
0
Released by RESET
–
Released by interrupt
–
17
2
/ fx
(2)
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator startup.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
EXECUTION OF
STOP INSTRUCTION
VDDDR
RESET
tWAIT
t SREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
14-7
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
0.8 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN)
1 / fx
tXL
tXH
VDD - 0.2 V
Xin
0.2 V
Figure 14-5. Clock Timing Measurement at XIN
14-8
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
1 / fTI
tTIL
tTIH
TCL
0.8 VDD
0.2 VDD
Figure 14-6. TCL Timing
tRSL
RESET
0.2 VDD
Figure 14-7. Input Timing for RESET Signal
tINTL
INT0, 1
KS0 to KS2
tINTH
0.8 VDD
0.2 VDD
Figure 14-8. Input Timing for External Interrupts
14-9
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
t CKY
t KL
tKH
SCK
0.8 VDD
0.2 VDD
t SIK
t KSI
0.8 VDD
INPUT DATA
SI
0.2 VDD
t KSO
SO
OUTPUT DATA
Figure 14-9. Serial Data Transfer Timing
14-10
S3C70F2/C70F4/P70F4
15
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The S3C70F2/C70F4/P70F4microcontroller is available in a 30-pin SDIP package (Samsung part number 30SDIP-400) and a 32-SOP package (Samsung part number 30-SOP-450A).
#16
0-15
0.2
5
30-SDIP-400
+0
- 0 .10
.05
10.16
8.94 ± 0.20
#30
0.56 ± 0.10
(1.30)
NOTE:
1.12 ± 0.10
1.778
5.21 MAX
27.48 ± 0.20
3.30 ± 0.30
27.88 MAX
3.81 ± 0.20
#15
0.51 MIN
#1
Dimensions are in millimeters.
Figure 15-1. 30-SDIP-400 Package Dimensions
15-1
MECHANICAL DATA
S3C70F2/C70F4/P70F4
0-8
#17
0.25
20.30 MAX
19.90 ± 0.20
+ 0.10
- 0.05
0.90 ± 0.20
#16
2.00 ± 0.10
#1
2.20 MAX
32-SOP-450A
11.43
8.34 ± 0.20
12.00 ± 0.30
#32
0.40 ± 0.10
(0.43)
NOTE:
1.27
0.05 MIN
0.10 MAX
Dimensions are in millimeters.
Figure 15-2. 30-SOP-450A Package Dimensions
15-2
S3C70F2/C70F4/P70F4
16
S3P70F4 OTP
S3P70F4 OTP
OVERVIEW
The S3P70F4 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C70F2/C70F4 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P70F4 is fully compatible with the S3C70F2/C70F4, both in function and in pin configuration. Because of
its simple programming requirements, the S3P70F4 is ideal for use as an evaluation chip for the
S3C70F2/C70F4.
VSS/VSS
Xout
Xin
VPP/TEST
P1.0/INT0
P1.1/INT1
RESET /RESET
P0.0/SCK
P0.1./SO
P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
NOTE:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S3C70F4
(30-SDIP)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
VDD/VDD
P6.3/BUZ/SCLK
P6.2/KS2/SDAT
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.2/CLO
P3.1/TCLO0
The bolds indicate an OTP pin name.
Figure 16-1. S3P70F4 Pin Assignments (30-SDIP Package)
16-1
S3P70F4 OTP
S3C70F2/C70F4/P70F4
VSS/VSS
Xout
Xin
VPP/TEST
P1.0/INT0
P1.1/INT1
RESET /RESET
NC
P0.0/SCK
P0.1./SO
P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
NOTE:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S3P70F4
(32-SOP)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD/VDD
P6.3/BUZ/SCLK
P6.2/KS2/SDAT
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
NC
P3.2/CLO
P3.1/TCLO0
The bolds indicate an OTP pin name.
Figure 16-2. S3P70F4 Pin Assignments (32-SOP Package)
16-2
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P6.2
SDAT
28 (30)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P6.3
SCLK
29 (31)
I/O
Serial clock pin. Input only pin.
TEST
VPP(TEST)
4 (4)
I
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
RESET
RESET
7 (7)
I
Chip initialization
VDD / VSS
VDD / VSS
30/1 (32/1)
I
Logic power supply pin. VDD should be tied to +5 V
during programming.
NOTE: ( ) means the 32-SOP OTP pin number.
Table 16-2. Comparison of S3P70F4 and S3C70F2/C70F4 Features
Characteristic
S3P70F4
S3C70F2/C70F4
Program Memory
4 K-byte EPROM
2 K-byte mask ROM: S3C70F2
4 K-byte mask ROM: S3C70F4
Operating Voltage (VDD)
2.0 V to 5.5 V
1.8 V to 5.5V
OTP Programming Mode
VDD = 5 V, VPP(TEST)=12.5V
Pin Configuration
30 SDIP, 32 SOP
30 SDIP, 32 SOP
EPROM Programmability
User Program one time
Programmed at the factory
–
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P70F4, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16–3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
Vpp(TEST)
REG/MEM
ADDRESS(A15-A0)
R/W
MODE
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
S3P70F4 OTP
S3C70F2/C70F4/P70F4
OTP ELECTRICAL DATA
Table 16-4. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
Rating
Units
VDD
–
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
mA
Input Voltage
VI
Output Voltage
VO
–
Output Current High
I OH
One I/O port active
–5
All I/O ports active
– 15
Output Current Low
I OL
All I/O ports
Ports 0, 3, and 6
5
mA
Ports 4 and 5
30
All ports, total
+ 100
Operating Temperature
TA
–
– 40 to + 85
°C
Storage Temperature
Tstg
–
– 65 to + 150
°C
Table 16-5. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Input High
Voltage
Input Low
Voltage
Output High
Voltage
16-4
Symbol
Conditions
Min
Typ
Max
Units
V
VIH1
Ports 4 and 5
0.7VDD
–
VDD
VIH2
Ports 0, 1, 2, 3, 6, and RESET
0.8VDD
–
VDD
VIH3
XIN and XOUT
VDD – 0.1
–
VDD
VIL1
Ports 4 and 5
–
–
0.3VDD
VIL2
Ports 0, 1, 2, 3, 6, and RESET
VIL3
XIN and XOUT
VOH
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 0, 3, 4, 5, 6
V
0.2VDD
0.1
VDD - 1.0
–
–
V
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-5. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Output Low
Voltage
Symbol
VOL
Conditions
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Min
Typ
Max
Units
–
–
2
V
–
2
–
3
Ports 4, 5
VDD = 4.5 V to 5.5 V
IOL = 4.0mA
All output pins except Ports 4, 5
Input High
Leakage
Current
Input Low
Leakage
Current
ILIH1
VIN = VDD
All input pins except XIN and XOUT
ILIH2
VIN = VDD
XIN and XOUT
ILIL1
VIN = 0 V
All input pins except XIN, XOUT
–
µA
20
–
–
–3
µA
and RESET
ILIL2
VIN = 0 V
XIN and XOUT
Output High
Leakage
Current
ILOH
VO = VDD
All output pins
–
–
3
µA
Output Low
Leakage
Current
ILOL
VO = 0 V
–
–
–3
µA
Pull-Up
Resistor
RL1
VI = 0 V; VDD = 5 V
Port 0, 1, 3, 4, 5, 6
VDD = 3 V
25
50
100
kΩ
50
100
200
VDD = 5 V; VI = 0 V; RESET
100
250
400
VDD = 3 V
200
500
800
RL2
– 20
16–5
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-5. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
IDD1
Supply
Current
Symbol
(1)
IDD2
IDD3
Conditions
Min
Typ
Max
–
3.0
8.0
Run mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
2.0
5.5
VDD = 3 V ± 10%
6.0MHz
1.3
4.0
4.19MHz
1.0
3.0
0.8
2.5
Idle mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
0.6
1.8
VDD = 3 V ± 10%
6.0MHz
0.6
1.5
4.19MHz
0.4
1.0
0.5
3.0
0.3
2.0
–
Stop mode; VDD = 5.0 V ± 10%
–
Stop mode; VDD = 3.0 V ± 10%
Units
mA
mA
µA
NOTES:
1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers,
2.
output port drive currents and comparator.
The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 )
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
4.2 MHz
15.625 kHz
400 kHz
1
2
2.7
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-3. Standard Operating Voltage Range
16–6
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-6. Oscillators Characteristics
(TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
Xin
Xout
C1
Crystal
Oscillator
Xin
External
Clock
Xin
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 2.0 V to 5.5 V
0.4
–
4.2
–
–
4
ms
MHz
C2
Xout
C1
Parameter
Stabilization time (2)
VDD = 3.0 V
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 2.0 V to 5.5 V
0.4
–
4.2
–
–
10
ms
MHz
C2
Xout
Stabilization time (2)
VDD = 3.0 V
Xin input frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 2.0 V to 5.5 V
0.4
–
4.2
–
83.3
–
1250
XIN input high and low
level width (tXH, tXL)
ns
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
16–7
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-7. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
15
pF
CIO
15
pF
I/O Capacitance
Table 16-8. Comparator Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5V, VSS = 0 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
–
–
0
–
VDD
V
Reference Voltage
Range
VREF
–
0
–
VDD
V
Input Voltage Accuracy
VCIN
–
–
–
±150
mV
Input Leakage Current
ICIN, IREF
–
–3
–
3
µA
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 2.0 V to 5.5 V
0.95
VDD = 2.7 V to 5.5 V
0
–
1.5
MHz
1
MHz
–
–
µs
–
–
ns
Input Voltage Range
Table 16-9. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Instruction Cycle
Time
TCL0 Input
Frequency
Symbol
tCY
f TI
Conditions
VDD = 2.0 V to 5.5 V
TCL0 Input High,
Low Width
SCK Cycle Time
tTIH, tTIL
tKCY
VDD = 2.7 V to 5.5 V
0.48
VDD = 2.0 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
800
External SCK source
Internal SCK source
670
VDD = 2.0 V to 5.5 V
3200
External SCK source
Internal SCK source
16–8
3800
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-9. A.C. Electrical Characteristics ( Concluded)
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
SCK High, Low
Width
Symbol
tKH, tKL
Conditions
VDD = 2.7 V to 5.5 V
Min
Typ
Max
Units
335
–
–
ns
–
–
ns
–
–
ns
–
300
ns
External SCK source
Internal SCK source
tKCY/2 - 50
VDD = 2.0 V to 5.5 V
1600
External SCK source
Internal SCK source
SI Setup Time to
SCK High
tSIK
VDD = 2.7 V to 5.5 V
tKCY/2 - 150
100
External SCK source
Internal SCK source
150
VDD = 2.0 V to 5.5 V
150
External SCK source
SI Hold Time to
SCK High
tKSI
Internal SCK source
500
VDD = 2.7 V to 5.5 V
400
External SCK source
Internal SCK source
400
VDD = 2.0 V to 5.5 V
600
External SCK source
Internal SCK source
Output Delay for
SCK to SO
tKSO (1)
VDD = 2.7 V to 5.5 V
500
–
External SCK source
Internal SCK source
250
VDD = 2.0 V to 5.5 V
1000
External SCK source
Internal SCK source
Interrupt Input
High, Low Width
RESET Input
Low Width
tINTH,
tINTL
tRSL
1000
INT0
(2)
INT1, KS0–KS2
10
Input
10
–
–
µs
–
–
µs
NOTES:
1. R(1Kohm) and C (100pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
16–9
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
2.0
–
5.5
V
Data retention supply current
IDDDR
VDDDR = 2.0 V
–
0.1
10
µA
Release signal set time
tSREL
–
0
–
–
µs
Oscillator stabilization wait
time (1)
tWAIT
Released by RESET
–
217 / fx
–
ms
Released by interrupt
–
(2)
–
ms
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
16–10
S3C70F2/C70F4/P70F4
S3P70F4 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-4. OTP Programming Algorithm
16–11
S3P70F4 OTP
S3C70F2/C70F4/P70F4
NOTES
16–12