Ordering number : EN8791 Monolithic Digital IC LB11889M For VCR Capstan Three-Phase Brushless Motor Driver Overview The LB11889M is three-phase brushless motor driver for VCR capstan motors. Features • 3-phase full-wave current linear drive. • Torque ripple correction circuit (fixed correction ratio). • Current limiter circuit with control characteristics gain switching. • Output stage upper/lower oversaturation prevention circuit (No external capacitor required). • FG amplifier built in. • Thermal shutdown circuit built in. Absolute Maximum Ratings at Ta = 25°C Parameter Maximum power supply voltage Symbol Conditions Ratings VCC max Unit 7 V VS max 24 V Maximum output current IO max 1.3 A Allowable power dissipation voltage Pd max 950 mW Independent IC Operating temperature Topr -20 to +75 °C Storage temperature Tstg -55 to +150 °C Allowable Operating Range at Ta = 25°C Parameter Power supply voltage Symbol Conditions VS GSENSE input range VHALL VGSENSE Unit 5 to 22 VCC Hall input amplitude Ratings Between hall inputs Relative to the control system GND V 4.5 to 5.5 V ±30 to ±80 mVo-p -0.20 to +0.20 V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. D2706 TI IM B8-4207 No.8791-1/11 LB11889M Electrical Characteristics at Ta = 25°C, VCC = 5V, VS = 15V Ratings Parameter VCC power supply current Symbol Conditions min typ max ICC RL = ∞, VCTL = 0V, VLIM = 0V (at static mode) 12 18 VOsat1 IO = 500mA, Rf = 0.5Ω, sink+source VCTL = VLIM = 5V (With saturation prevention) 2.1 2.6 VOsat2 IO = 1.0A, Rf = 0.5Ω, sink+source 2.6 3.5 Unit mA Output Output saturation voltage V VCTL = VLIM = 5V (With saturation prevention) Output leak current IOleak 1.0 mA FR FR pin input threshold voltage VFSR 2.25 FR pin input input bias current Ib (FSR) -5.0 VCREF 2.37 VCREF IN 1.70 2.50 2.75 V µA Control CTLREF pin voltage CTLREF pin input range CTL pin input bias current CTL pin control start voltage Ib (CTL) VCTL (ST) VCTL = 5V, CTLREF : OPEN V 3.50 V 8.0 µA 2.20 2.35 2.50 V 3.00 3.15 3.30 V 0.52 0.65 0.78 A/V 1.20 1.50 1.80 A/V Rf = 0.5Ω, VCTL = 5V, IO≥10mA With hall input logic fixed (U, V, W = H, H, L) 140 200 260 mV VCTL = 5V, CTLREF : OPEN, VLIM = 0V -2.5 VCTL (ST2) Rf = 0.5Ω, VLIM = 5V CTL pin control Gm1 Gm1 (CTL) Rf = 0.5Ω, ∆IO = 200mA With hall input logic fixed (U, V, W = H, H, L) Gm2 (CTL) 2.63 Rf = 0.5Ω, VLIM = 5V, IO≥10mA With hall input logic fixed (U, V, W = H, H, L) CTL pin control switching voltage CTL pin control Gm2 2.50 Rf = 0.5Ω, ∆VCTL = 200mV With hall input logic fixed (U, V, W = H, H, L) Current limiter LIM current limiter offset voltage LIM pin input bias current LIM pin current limiter level Voff (LIM) Ib (LIM) Ilim Rf = 0.5Ω, VCTL = 5V, VLIM = 2.06V With hall input logic fixed (U, V, W = H, H, L) 830 µA 900 970 mA +6 mV 1.0 3.0 µA 3.3 V Hall amplifier Hall amplifier input offset voltage Hall amplifier input bias current Hall amplifier common-mode Voff (HALL) -6 Ib (HALL) VCM (HALL) 1.3 TRC Torque ripple correction factor TRC At bottom and peak of Rf waveform at IO = 200mA 9 (RF = 0.5Ω, ADJ-OPEN) Note 2 ADJ pin voltage VADJ 2.37 2.50 % 2.63 V FG amplifier FG amplifier input offset voltage Voff (FG) FG amplifier input bias current Ib (FG) FG amplifier output saturation VOsat (FG) -8 +8 -100 nA At internal pull-up resistor on the sink side voltage FG amplifier common-mode input VCM (FG) 0.5 voltage mV 0.5 V 4.0 V 0.325 V Saturation Saturation prevention circuit lower VOsat (DET) Voltage between each OUT and Rf at IO = 10mA, TSD operating temperature T-TSD (Design target) Note.1 180 °C TSD temperature hysteresis width ∆TSD (Design target) Note.1 20 °C set voltage Rf = 0.5Ω, VCTL = VLIM = 5V 0.175 0.25 TSD Note 1. No measurements are made on the parameters with Note (Design target). No.8791-2/11 LB11889M Note 2. The torque ripple correction factor is obtained based on the voltage waveform across Rf as shown below. Vp III II I V IV Vb VI Each hall logic setting GND lebel 2× (Vp-Vb) Correnction factor = ×100 (%) Vp+Vb Package Dimensions unit : mm (typ) 3280A 1 18 0.35 0.25 2.45MAX (2.25) (0.8) Allowable power dissipation, Pd max - W 0.65 7.9 19 10.5 36 0.8 Pd max - Ta 1.0 15.2 0.95W Independent IC 0.8 0.6 0.57W 0.4 0.2 0 -20 0 20 40 60 80 100 ILB01488 0.1 Ambient temperature, Ta - °C SANYO : MFP36SLF(375mil) No.8791-3/11 LB11889M Truth Table and Control Function Hall input Source → Sink V→W 1 W→V U→W 2 U→V W→V W→U H L L V→U H L H H L U→V FR L L L U→W 6 H L V→W 5 W H V→U 4 V H W→U 3 U H H L H L H L H L H L H L H L Note) “H” for FR represents a voltage of 2.75V or greater ; “L” represents a voltage of 2.25V or lower (at VCC = 5V). Note) Input “H” for all input represents that (+) is higher than each phase input (-) by 0.01V or greater ; input “L” represents that (+) is lower than each phase input (-) by 0.01V or greatre. Note) Since this drive scheme is the 180° energizing scheme, phases other than Sink, Source phases are not turned OFF. Control Function & Current Limiter Function Control characteristics VLIM = 5V CTLREF : OPEN Current limiter characteristics VCTL = 5V CTLREF : OPEN IOUT IOUT Slope = 0.50A/Vtyp Gm2 = 1.50A/Vtyp Gm1 = 0.65A/Vtyp VLIM VCTL 0 1 2 2.35Vtyp 3 3.15Vtyp 10 5 0 10 2 3 4 200mVtyp No.8791-4/11 LB11889M Pin Functions Pin name Pin no. FGIN (-) 3 Functions FGIN (+) 4 Noninverting input pin for the FG amplifier to be used as differential input. No bias is applied internally. FG-OUT 5 FG amplifier output pin with resistive load internally. CTL 6 Speed control pin. Control is performed by means of constant current drive which is applied by current feedback from Rf. CTLREF 7 Control reference voltage pin. The voltage is set at approximately VCC/2 internally, but can be varied by applying a voltage through a low impedance. (The input impedance is approximately 2.5kΩ.) LIM 8 Current limiter function control pin. This pin voltage is capable of varying the output current linealy. FC 9 UIN+, UINVIN+, VIN- 10, 11 U phase hall element input pin. “H” for logic represents IN+>IN-. 12, 13 V phase hall element input pin. “H” for logic represents IN+>IN-. WIN+, WIN- 14, 15 W phase hall element input pin. “H” for logic represents IN+>IN-. VCC 16 Input pin for the FG amplifier to be used with inverted input. A feedback resistor is connected between this pin and FG OUT. Gm = 0.65A/V & 1.50A/V TYP at Rf = 0.5Ω Slope = 0.5A/V TYP at Rf = 0.5Ω Speed control loop’s frequency characteristics correction pin. Power supply pin used to supply to each circuit other than the output blocks inside the IC. This voltage must be stabilized to reject noise and ripple. VS 21 ADJ 22 Power supply pin for output blocks. Pin to be used to adjust the torque ripple correction factor externally. When adjusting the correction factor, apply voltage externally to the ADJ pin through a low impedance. Increasing the applied voltage decreases the correction factor ; lowering the applied voltage increases the correction factor. The rate of change, when left open, ranges approximately from 0 to 2 times. Rf (PWR) 23 (Approximately VCC/2 is set internally and the input impedance is approximately 5kΩ.) Output current detection pins. Current feedback is provided to the control blocks by connecting Rf between the pins and Rf (SNS) 31 GND. The operation of the lower over-saturation prevention circuit and torque ripple correction circuit depends on the pin voltage. In particular, since the oversaturation prevention level is set by the pin voltage, decreasing the Rf value extremely may cause the lower over-saturation prevention to work less efficiently in the large current region. The PWR pin and SENSE pin must be connected. UOUT VOUT 26 U phase output pin 27 V phase output pin WOUT 28 W phase output pin GSENSE 32 GND sensing pin. (With spark killer diode built in) By connecting this pin to GND in the vicinity of the Rf resistor side of the Rf included motor GND wiring, the influence that the GND common impedance exerts on Rf can be excluded. (Must not be left open.) FR 33 GND 34 Forward/reverse select pin. This pin voltage determines forward/reverse. (Vth = 2.5V typ. At VCC = 5V) GND for other than output transistors. The lowest potential of output transistors is on the Rf pin. No.8791-5/11 LB11889M Each Input/Output Equivalent Circuit Pin name Input/Output equivalent circuit UIN (+) UIN (-) VIN (+) VIN (-) Each (+) input WIN (+) Each (-) input WIN (-) 200Ω 100µA 200Ω UOUT VOUT VS VCC 150µA WOUT VS Rf (POWER) Each OUT Rf (SENSE) Lower oversaturation prevention circuit input block VCC 30kΩ 10µA 200Ω 200Ω Rf (SENSE) Rf (POWER) CTL LIM VCC VCC VCC CTL 200µA max 5kΩ CTLREF CTLREF 200Ω LIM 5kΩ 100µA 200Ω 200Ω FR VCC VCC 1/2 VCC 6kΩ 10kΩ 500Ω 6kΩ 10kΩ 200Ω 10kΩ ADJ 10kΩ 200µA FR VCC 20µA VCC ADJ Continued on next page. No.8791-6/11 LB11889M Continued from preceding page. Pin name Input/output equivalent circuit FGIN (-) FGIN (+) 5µA VCC FGIN (+) FGIN (-) 300Ω FGOUT VCC VCC 300Ω FGOUT 10kΩ VCC 2kΩ FC FC No.8791-7/11 LB11889M Block Diagram 9 Output stage FC 21 VS VIN+ 12 - U + V VIN- 13 - W IN+ 14 + W IN- 15 - Synthesized output logarithmic compression block UIN- 11 + Hall input synthesizing block (Linear matrix) UIN+ 10 Anti-logarithm & differential distribution Upper saturation prevention control W gm U 26 U-OUT V 27 V-OUT W 28 W-OUT 23 Rf (PWR) + - 31 Rf (SENSE) gm + - Differential distribution & torque ripple correction block Control amplifier 1 + CTL 6 CTLREF 7 + + - + - LIMREF Drive distribution circuit & lower saturation prevention control 22 ADJ Feedback amplifier + gm - Control amplifier 2 32 GSENSE LIM 8 FR 33 Forward /reverse select FG amplifier TSD 3 FGIN- + 4 FGIN+ 5 GND 34 VCC 16 - FGOUT Reference voltage Bandgap 1.2V No.8791-8/11 LB11889M Pin Assignment FRAME 1 36 FRAME FRAME 2 35 FRAME FGIN(-) 3 34 GND FGIN(+) 4 33 FR FG-OUT 5 32 GSENSE CTL 6 31 Rf(SENSE) CTLREF 7 30 LIM 8 29 FC 9 28 W-OUT UIN(+) 10 27 V-OUT UIN(-) 11 26 U-OUT VIN(+) 12 25 VIN(-) 13 24 WIN(+) 14 23 WIN(-) 15 22 ADJ VCC 16 21 VS FRAME 17 20 FRAME FRAME 18 19 FRAME LB11889M Rf(POWER) Top view Note: Although the FRAME pins and the GND pin are not connected internally in the IC, the FRAME pins must be connected to the GND pin externally for ground potential stabilization. No.8791-9/11 R L Hall output 104µF 12kΩ The hall bias resistor R must be selected according to the sensor output. L L Hall output R 1 36 1MΩ FG output pin Hall input 104µF 104µF 104µF 0.5Ω 18 19 VS Torque instruction voltage supply pin CTLREF voltage supply pin Current limiter setting voltage supply pin VCC ADJ voltage supply pin Power GND Note) The component values shown in this application circuit example one merely provided as examples, and circuit operating characteristics are not guaranteed. MR Hall output GaAs is recommended for a hall element. 104µF Forward/reverse instruction voltage supply pin LB11889M Sample Application Circuit No.8791-10/11 LB11889M Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 2006. Specifications and information herein are subject to change without notice. PS No.8791-11/11