Ordering number : EN8931 Bi-CMOS IC LV5106FN For cell phone system Power supply Overview The LV5106FN is a power supply for a cell phone system that integrates four series regulators, two de-writers, and an LED driver (with 5V output) on a single chip. Functions • REG×4 (CMOS output) • DET circuit (one for REG1, one for VBAT (with reset output) • Thermal shutdown circuit (150°C) • Three-color LED driver (charge pump 5V output incorporated) • FRONT LED driver • Mic bias output Features • Low power consumption • Built-in charge pump circuit • Built-in 3-color LED drive circuit 4μA when REG4 and VBATDET operate 30μA when REG1, REG2, REG3, and REG4 + DET1 and VBATDET operate VBAT : 3.2V to 4.5V, 5V constant output with a load of 80mA Three independent colors, 128-step PWM intensity control Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Symbol Conditions VCC max Pd max Ratings Unit 7 Ta ≤ 75°C *Mounted on a board. 440 V mW Operating temperature Topr -30 to +75 °C Storage temperature Tstg -40 to +125 °C ∗ Mounted on a 50.0mm×50.0mm×0.8mm, glass epoxy board. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 61307 TI PC B8-6923 No.8931-1/6 LV5106FN Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage 1 VBAT Supply voltage 2 VBATCP Conditions Ratings Unit 29, 33pin 3.2 to 4.5 V 3pin 3.2 to 5.9 V Electrical Characteristics Ta = 25°C, VBAT = 3.6V, VCHARGE = 0V, unless otherwise specified. Parameter Symbol Ratings Conditions min typ Unit max Analog : Current dissipation Current dissipation 1 ICC1 REG4, VBATDET : ON 4 10 μA 25 35 μA 20 28 μA 30 42 μA 15 21 μA 5 8 mA REG1, 2, 3, charge punp, DET1 : OFF no-load VBAT = 3.2V to 4.2V Current dissipation 2 ICC2 REG1, 2, 4, DET1, VBATDET : ON REG3, charge pump : OFF no load Current dissipation 3 ICC3 REG3, 4, VBATDET : ON REG1, 2, DET1, charge pump : OFF no load Current dissipation 4 ICC4 REG1, 2, 3, 4, DET1, VBATDET : ON charge pump : OFF no load Current dissipation 5 ICC5 REG1, 2, 3, 4, DET1, VBATDET : ON charge pump : OFF no load ECO : L Current dissipation 6 ICC6 REG1, 2, 3, 4, charge pump, DET1, VBATDET : ON no load REG1 Output voltage 1 VO1 IO = 30mA, ECO = H 2.74 2.8 2.86 V Output voltage 2 VO1E IO = 30mA, ECO = L 2.71 2.8 2.89 V Output voltage 3 ΔVO1 (IO = 30mA, REG1 output voltage at ECO = H) (IO = 10mA, REG1 output voltage at IO = 10 mA 0 15 35 mV Output voltage 4 ΔVO2 35 mV and ECO = L) IO = 30mA -35 (charge-pump on-time REG1 output voltage) – (charge-pump off-time REG1 output voltage) Drop out voltage VDR1 VBAT = 2.7V, IO = 30mA 0.04 0.06 Load regulation ΔVOLO1 IO = 1 to 150mA 10 50 mV Line regulation ΔVOLN1 VBAT = 3.3 to 4.5V, IO = 1mA 10 60 mV Output voltage temperature ΔVO1/ΔTj Ta = -25 to 75°C, IO = 30mA ±100 V ppm/°C coefficient Ripple rejection VR1 VBAT = 3.6V, IO = 30mA, VRR = -20dBV, 65 dB 75 μVrms fRR = 1kHz Output noise voltage VON1 IO = 30mA, 20Hz < f < 20kHz REG2 Output voltage 1 VO2 IO = 30mA, ECO = H 2.55 Output voltage 2 VO2E IO = 30mA, ECO = L 2.53 Drop out voltage VDR1 VBAT = 2.5V, IO = 30mA Load regulation ΔVOLO2 IO = 1 to 100mA Line regulation ΔVOLN2 VBAT = 3.3 to 4.5V, IO = 1mA Output voltage temperature ΔVO2/ΔTj Ta = -25 to 75°C, IO = 30mA 2.6 2.65 V 2.6 2.67 V 0.06 0.12 V 10 100 mV 10 60 ±100 mV ppm/°C coefficient Ripple rejection VR2 VBAT = 3.6V, IO = 30mA, VRR = -20dBV, 65 dB 75 μVrms fRR = 1kHz Output noise voltage VON2 IO = 30mA, 20Hz < f < 20kHz Continued on next page. No.8931-2/6 LV5106FN Continued from preceding page. Parameter Symbol Ratings Conditions min typ Unit max REG3 Output voltage 1 VO3 IO = 30mA, ECO = H 2.45 2.5 2.55 V Output voltage 2 VO3E IO = 30mA, ECO = L 2.43 2.5 2.57 V Drop out voltage VDR3 0.06 0.12 Load regulation ΔVOLO3 IO = 1 to 50mA VBAT = 2.4V, IO = 30mA 10 50 mV Line regulation ΔVOLN3 VBAT = 3.3 to 4.5V, IO = 1mA 10 60 mV Output voltage temperature ΔVO3/ΔTj Ta = -25 to 75°C, IO = 30mA ±100 V ppm/°C coefficient Ripple rejection VR3 VBAT = 3.6V, IO = 30mA, VRR = -20dBV, 65 dB 75 μVrms fRR = 1kHz Output noise voltage VON3 IO = 30mA, 20Hz < f < 20kHz REG4 Output voltage VO4 IO = 30mA 2.91 VBAT = 2.9V, IO = 30mA 3 3.09 V Drop out voltage VDR3 0.06 0.12 Load regulation ΔVOLO4 IO = 1 to 50mA 10 50 mV Line regulation ΔVOLN4 VBAT = 3.3 to 4.5V, IO = 1mA 10 60 mV Output voltage temperature ΔVO4/ΔTj Ta = -25 to 75°C, IO = 30mA ±100 V ppm/°C coefficient Ripple rejection VR4 VBAT = 3.6V, IO = 30mA, VRR = -20dBV, 55 dB 75 μVrms fRR = 1kHz Output noise voltage VON4 IO = 30mA, 20Hz < f < 20kHz DET1 Detection voltage VD1 Hysteresis width ΔVH1 Detection voltage temperature ΔVD1/ΔTj H→L 2.45 2.5 2.55 V 75 125 175 mV ±100 Ta = -25 to 75°C ppm/°C coefficient VBATDET Detection voltage VDB Hysteresis width ΔVHB Output pull-up resistance RPDETB Detection voltage temperature ΔVDB/ΔTj H→L 3.04 3.1 3.16 V 93 155 217 mV 1.8 2.2 1.4 ±100 Ta = -25 to 75°C MΩ ppm/°C coefficient Charge pump Output voltage 1 VCPO1 Oscillation frequency CPOSC Output ripple Efficiency VBAT = 3.2 to 5.9V, Load current 80mA 4.8 5 5.2 V 0.7 1 1.3 MHz VRCP VBAT = 3.6, Load current 80mA ±200 η VBAT = 3.2, Load current 80mA 72 mVp-p % LED driver LEDR output voltage VLR IO = 40mA 0 0.1 0.2 V LEDG output voltage VLG IO = 40mA 0 0.1 0.2 V LEDB output voltage VLB IO = 40mA 0 0.1 0.2 V LEDF output voltage VLF IO = 40mA 0 0.15 0.3 V LEDR OFF leak ILR 0 1 μA LEDG OFF leak ILG 0 1 μA LEDB OFF leak ILB 0 1 μA LEDF OFF leak ILF 0 1 μA Mic bias Output ON resistance RMO OFF leakage current ILM IO = 10mA Ω 10 0 1 μA REG10 V 0.3 V Output voltage (GP_0, 1) Output H level VOH IO = 1mA REG10 -0.3 Output L level VOL IO = 1mA 0 Continued on next page. No.8931-3/6 LV5106FN Continued from preceding page. Parameter Symbol Ratings Conditions min typ Unit max Input voltage 1 (SDATA, SEN, SCLK) H level VINH1 Input H level REG10 REG10 V REG10 V ×0.8 L level VINL1 Input L level 0 ×0.2 Input voltage 2 (T_CNT, TCXOCNT, ECO, REG3CTL, REG12CTL, PWRON, RTCINT, MSSELO, MSSELOC, KEYSENSE4, HWRESET) H level VINH2 Input H level REG40 REG40 V REG40 V ×0.8 L level VINL2 Input L level 0 ×0.2 Input voltage 3 (RESOUT_N) H level VINH3 Input H level REG40 REG40 V REG40 V ×0.8 L level VINL3 Input L level 0 ×0.2 Input voltage 4 (CHG_G) H level VINH4 Input H level REG40 6 V REG40 V ×0.8 L level VINL4 Input L level 0 ×0.2 Input voltage 5 (Vcharge) H level VINH5 Input H level 4.4 6 V L level VINL5 Input L level 0 3.6 V VINH6 Input H level REG40 VBAT V REG40 V Input voltage 6 (VBATBK) H level ×0.8 L level VINL6 Input L level 0 ×0.2 Serial bus : Serial transfer timing Cycle time tcy1 SCLK clock cycle 300 ns Data setup time 1 ts0 SDEN setup time for rise of SCLK 150 ns Data setup time 2 ts1 SDATA setup time for rise of SCLK 150 ns Data hold time 1 th0 SDEN hold time for fall of SCLK 150 ns Data hold time 2 th1 SDATA hold time for rise of SCLK 150 ns Pulse width 1 tw1L SCLK L-period pulse width 150 ns Pulse width 2 tw1H SCLK H-period pulse width 150 ns Pulse width 3 tw2L SDEN L-period pulse width 1 μs Package Dimensions unit : mm (typ) 3272 Top View Bottom View 0.2 7.2 7.0 36 25 5.0 5.0 0.3 7.0 7.2 48 0.4 24 37 13 1 12 0.5 Side View 4 - Do Not Connect 0.2 (0.8) 0.85MAX (0.75) 0.4 0.3 SANYO : VQFN48(7X7) No.8931-4/6 LV5106FN Serial transfer timing conditions 50% SDEN th0 ts0 tw2L SCLK 50% tw1L tw1H th1 ts1 tcy1 SDATA A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D3 Address D2 D1 D0 A7 Data Data length : 24bit Clock frequency : 3MHz or les "SDATA" is taken in at fall of "SDEN" when "SCLK" of 24 clock is entered during H period of "SDEN." (Note) "SDATA" is not taken in when "SCLK" is 23 clock or less during H period of "SDEN." When "SCLOCK" exceeds 25 clock, "SDATA" is taken in at the 24th clock, and subsequent "SDATA" is ignored. PWRON RTCINT RREF 0.1μF 0.1μF BG GNDR TEST2 MSSELO 31 30 2.8V 150mA 29 28 27 ECO DET1 REG1O REG1OS 4.7μF 4.7μF 3.0V 50mA 32 VBAT14 33 REG4O 34 REG3O VBAT23 35 REG3CTL REG2O 36 MICBIAS REG12CTL 4.7μF 4.7μF 2.5V 50mA 2.6V 100mA Block Diagram 26 25 1MΩ 37 24 Seril 38 39 REG 3 REG 2 REG 4 REG 1 22 REG12CTL REG12CTL REG3CTL 40 DET1 REG12CTL 41 VBAT VBATDET BGR 21 20 1.8MΩ VBAT 42 23 19 43 18 44 17 MSSELOC 16 15 PWM_B 5 6 7 8 9 10 FLED 4 BLED 3 GNDLED 2 GLED 1 RLED 48 11 12 SDATE Serial CTL TEST CHARGE PUMP 47 PWM_G PWM_R 46 CPOUT VCHARGE Counter C+ HWRESET OSC 45 VBATCP RESOUT_N C- KEYSENSE4 GNDCP XXμF 14 13 RESETL CD 0.1μF TCXOCNT P_CNT T_CNT TT XXμF VBATBK CHG_G XXμF GP_1 GP_0 SCLK SEN 0.22μF 1μF 4.7μF Top view No.8931-5/6 LV5106FN Power Control Block Diagram REG4O PWRON P_CNT 1000kΩ REG4O REG4O MSSELO 1000kΩ REG4O 10kΩ MSSELOC REG4O REG4O REG4O RTCINT REG4O 10kΩ T_CNT REG4O KEYSENSE4 2000kΩ REG4O RESOUT_N REG4O REG4O HWRESET 100kΩ 2kΩ 120kΩ REG4O REG4O VCHARGE 10kΩ 100kΩ REG4O CHG(G) REG4O REG4O VBATBK VBAT 1000kΩ REG4O TCXOCNT TT 1000kΩ SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2007. Specifications and information herein are subject to change without notice. PS No.8931-6/6