TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 200-mA, Low-IQ, Low-Dropout Regulator for Portable Devices FEATURES 1 • Very Low Dropout: – 43 mV at IOUT = 50 mA, VOUT = 2.8 V – 85 mV at IOUT = 100 mA, VOUT = 2.8 V – 175 mV at IOUT = 200 mA, VOUT = 2.35 V • 2% Accuracy • Low IQ: 31 mA • Available in Fixed-Output Voltages from 0.7 V to 4.8 V • High PSRR: 68 dB at 1 kHz • Stable with Effective Capacitance of 0.1 mF • Thermal Shutdown and Overcurrent Protection • Available in 1,5-mm × 1,5-mm SON-6, SOT23-5, and SC-70 packages 234 APPLICATIONS • • • • • • • Wireless Handsets Smart Phones, PDAs MP3 Players ZigBee® Networks Bluetooth® Devices Li-Ion Operated Handheld Products WLAN and Other PC Add-on Cards DESCRIPTION The TLV700xx/TLV701xx series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have thermal shutdown and current limit for safety. Furthermore, these devices are stable with an effective output capacitance of only 0.1 mF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load. The TLV700xx series of LDOs are available in 1,5-mm x 1,5-mm SON-6, TSOT23-5, and SC-70 packages. The TLV701xx series of LDOs are available in a 1,5-mm x 1,5-mm SON-6 package. space space TLV700xxDDC TSOT23-5 (TOP VIEW) VIN IN OUT CIN COUT VOUT 1 mF Ceramic TLV700xx 1 IN On 5 OUT Off EN GND GND 2 EN 3 N/C 4 TLV700xx DSE 1,5-mm x 1,5-mm SON (TOP VIEW) 6 EN GND 2 5 N/C OUT 3 4 N/C IN 1 TLV700xx DCK SC70-5 PACKAGE (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 N/C Typical Application Circuit (Fixed-Voltage Versions) 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG. ZigBee is a registered trademark of the ZigBee Alliance. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT TLV700xx yyy z TLV701xx yyy z (1) (2) (2) XX is nominal output voltage (for example, 28 = 2.8 V). YYY is the package designator. Z is tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Output voltages from 0.7 V to 4.8 V in 50-mV increments are available. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND. PARAMETER TLV700xx/TLV701xx UNIT Input voltage range, VIN –0.3 to +6.0 V Enable voltage range, VEN –0.3 to +6.0 V Output voltage range, VOUT –0.3 to +6.0 V Maximum output current, IOUT Internally limited Output short-circuit duration Indefinite Total continuous power dissipation, PDISS ESD rating See Dissipation Ratings Table Human body model (HBM) 2 500 V Operating junction temperature range, TJ –55 to +150 °C Storage temperature range, TSTG –55 to +150 °C (1) Charged device model (CDM) kV Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DISSIPATION RATINGS PACKAGE RqJC RqJA DERATING FACTOR ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C (1) DCK 165°C/W 395°C/W 2.5 mW/°C 250 mW 140 mW 100 mW High-K (2) DCK 165°C/W 315°C/W 3.2 mW/°C 320 mW 175 mW 130 mW High-K (2) DSE 67°C/W 180°C/W 4.55 mW/°C 555 mW 305 mW 222 mW Low-K (1) DDC 90°C/W 280°C/W 3.6 mW/°C 360 mW 200 mW 145 mW (2) DDC 90°C/W 200°C/W 5.0 mW/°C 500 mW 275 mW 200 mW BOARD Low-K High-K (1) (2) 2 The JEDEC low-K (1s) board used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the board. The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS At VIN = VOUT(Typ) + 0.3 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = 0.9 V, COUT = 1.0 mF, and TJ = –40°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. space PARAMETER TEST CONDITIONS VIN Input voltage range VOUT DC output accuracy –40°C ≤ TJ ≤ +125°C ΔVO/ΔVIN Line regulation VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA ΔVO/ΔIOUT Load regulation 0 mA ≤ IOUT ≤ 200 mA VDO ICL Output current limit TYP MAX 2.0 UNIT 5.5 V VOUT ≥ 1 V –2 +2 % VOUT < 1 V –20 +20 mV 1 5 mV 1 15 mV VIN = 0.98 × VOUT(NOM), IOUT = 50 mA, VOUT = 2.8 V 43 mV VIN = 0.98 × VOUT(NOM), IOUT = 100 mA, VOUT = 2.8 V 85 mV VIN = 0.98 × VOUT(NOM), IOUT = 200 mA, VOUT = 2.35 V 175 250 mV 350 550 mA 31 55 mA VOUT = 0.9 × VOUT(NOM) 220 IOUT = 0 mA IGND Ground pin current ISHDN Ground pin current (shutdown) PSRR Power-supply rejection ratio VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz 68 dB VN Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA 48 mVRMS tSTR Startup time (2) COUT = 1.0 mF, IOUT = 200 mA 100 ms IOUT = 200 mA, VIN = VOUT + 0.5 V 270 VEN ≤ 0.4 V, VIN = 2.0 V 400 VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V 1 mA nA 2 mA VEN(HI) Enable pin high (enabled) 0.9 VIN VEN(LO) Enable pin low (disabled) 0 0.4 V 0.5 mA IEN UVLO RDISCHARGE (1) (2) Dropout voltage (1) MIN Enable pin current VIN = VEN = 5.5 V Undervoltage lockout VIN rising 1.9 V Active pulldown resistance (TLV701xx only) VEN = 0 V 120 Ω +160 °C TSD Thermal shutdown temperature TJ Operating junction temperature 0.04 V Shutdown, temperature increasing Reset, temperature decreasing +140 –40 °C +125 °C VDO is measured for devices with VOUT(NOM) ≥ 2.35 V. Startup time = time from EN assertion to 0.98 × VOUT(NOM). Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAMS IN OUT Current Limit Thermal Shutdown UVLO EN Bandgap LOGIC TLV700xx Series GND Figure 1. TLV700xx IN OUT Current Limit Thermal Shutdown UVLO EN 120W Bandgap LOGIC TLV701xx Series GND Figure 2. TLV701xx 4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 PIN CONFIGURATIONS DDC PACKAGE TSOT23-5 (TOP VIEW) IN 1 GND 2 EN 5 3 4 DCK PACKAGE SC70-5 (TOP VIEW) OUT N/C IN 1 GND 2 EN 3 5 OUT 4 N/C (1) (1) DSE PACKAGE SON-6 (TOP VIEW) (1) IN 1 6 EN GND 2 5 N/C OUT 3 4 N/C (1) (1) No connection. PIN DESCRIPTIONS NAME SON-6 DSE SC70-5 DCK TSOT23-5 DDC DESCRIPTION IN 1 1 1 Input pin. A small 1-mF ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. See Input and Output Capacitor Requirements in the Application Information section for more details. GND 2 2 2 Ground pin EN 6 3 3 Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode and reduces operating current to 1 mA, nominal. For TLV701xx, output voltage is discharged through an internal 120-Ω resistor when device is shut down. NC 4, 5 4 4 No connection. This pin can be tied to ground to improve thermal dissipation. OUT 3 5 5 Regulated output voltage pin. A small 1-mF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. TLV70018 LINE REGULATION 1.90 TLV70018 LINE REGULATION 1.90 IOUT = 10 mA 1.88 1.88 1.86 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 Output Voltage (V) Output Voltage (V) 1.86 IOUT = 200 mA 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 1.70 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 2.1 2.6 Input Voltage (V) DROPOUT VOLTAGE vs INPUT VOLTAGE VOUT = 4.8V 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 60 80 100 120 140 Output Current (mA) Figure 5. Submit Documentation Feedback 160 180 200 Dropout Voltage (mV) Output Voltage (V) 5.1 TLV70018 LOAD REGULATION 1.86 6 4.6 Figure 4. 250 40 4.1 Figure 3. 1.88 20 3.6 5.6 Input Voltage (V) 1.90 0 3.1 IOUT = 200 mA 200 150 100 +125°C +85°C +25°C -40°C 50 0 2.25 2.75 3.25 3.75 4.25 4.75 Input Voltage (V) Figure 6. Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. TLV70018 OUTPUT VOLTAGE vs TEMPERATURE 180 1.90 160 1.88 140 1.86 120 100 80 60 +125°C +85°C +25°C -40°C 40 20 Output Voltage (V) Dropout Voltage (V) TLV70048 DROPOUT VOLTAGE vs OUTPUT CURRENT 30 60 90 120 150 180 1.82 1.80 1.78 1.76 IOUT = 200 mA IOUT = 10 mA IOUT = 150 mA 1.74 1.72 1.70 0 0 1.84 -40 -25 -10 210 5 20 Ground Pin Current (mA) 45 50 65 80 95 Figure 7. Figure 8. TLV70018 GROUND PIN CURRENT vs INPUT VOLTAGE TLV70018 GROUND PIN CURRENT vs LOAD 110 125 300 IOUT = 0 mA 40 35 30 25 20 15 +125°C +85°C +25°C -40°C 10 5 Ground Pin Current (mA) 50 35 Temperature (°C) Output Current (mA) 250 200 150 100 +125°C +85°C +25°C -40°C 50 0 0 2.1 2.6 3.1 3.6 4.1 4.6 Input Voltage (V) Figure 9. Copyright © 2009–2010, Texas Instruments Incorporated 5.1 5.6 0 20 40 60 80 100 120 140 160 180 200 Output Current (mA) Figure 10. Submit Documentation Feedback 7 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. TLV70018 SHUTDOWN CURRENT vs INPUT VOLTAGE 40 2.0 35 1.8 Shutdown Current (mA) Ground Pin Current (mA) TLV70018 GROUND PIN CURRENT vs TEMPERATURE 30 25 20 15 10 5 1.6 1.4 1.2 1.0 0.8 0.6 +125°C +85°C +25°C 0.4 0.2 IOUT = 0 mA 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.1 2.6 3.1 4.1 4.6 5.1 5.6 Figure 11. Figure 12. TLV70018 CURRENT LIMIT vs INPUT VOLTAGE TLV70018 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 440 100 430 90 420 80 IOUT = 10 mA IOUT = 150 mA 70 410 400 390 380 60 50 40 30 370 20 360 TA = +25°C 350 2.0 2.5 3.0 3.5 Input Voltage (V) Figure 13. 8 3.6 Input Voltage (V) PSRR (dB) Current Limit (mA) Temperature (°C) Submit Documentation Feedback 4.0 4..5 10 VIN - VOUT = 0.5 V 0 10 100 1k 10 k 100 k 1M 10 M Frequency (Hz) Figure 14. Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. TLV70018 OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT VOLTAGE TLV70018 POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE 1 kHz 70 60 PSRR (dB) Output Spectral Noise Density (mV/ÖHz) 80 10 kHz 50 100 kHz 40 30 20 10 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 10 1 0.1 0.01 IOUT = 10 mA CIN = COUT = 1 mF 0 10 2.8 100 100 k Figure 16. TLV70018 LOAD TRANSIENT RESPONSE TLV70018 LOAD TRANSIENT RESPONSE 0 mA 5 mV/div VOUT 20 mA/div IOUT 10 mA 0 mA IOUT VOUT VIN = 2.3 V 10 ms/div 10 ms/div Figure 17. Figure 18. TLV70018 LOAD TRANSIENT RESPONSE TLV70018 LINE TRANSIENT RESPONSE Slew Rate = 1 V/ms tR = tF = 1 ms IOUT 0 mA 1 V/div 50 mA VIN 2.9 V 2.3 V 5 mV/div 50 mA/div 10 M tR = tF = 1 ms 200 mA VIN = 2.1 V 20 mV/div 1M Figure 15. tR = tF = 1 ms 100 mA/div 10 k Frequency (Hz) Input Voltage (V) 50 mV/div 1k VOUT VIN = 2.3 V VOUT IOUT = 200 mA 10 ms/div 1 ms/div Figure 19. Figure 20. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. VIN TLV70018 LINE TRANSIENT RESPONSE Slew Rate = 1 V/ms Slew Rate = 1 V/ms 2.7 V 1 V/div 1 V/div TLV70018 LINE TRANSIENT RESPONSE 2.3 V VIN 5.5 V 10 mV/div 5 mV/div 2.1 V VOUT VOUT IOUT = 200 mA IOUT = 1 mA 1 ms/div 1 ms/div Figure 21. Figure 22. TLV70018 VIN RAMP UP, RAMP DOWN RESPONSE IOUT = 1 mA 1 V/div VIN VOUT 200 ms/div Figure 23. 10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 APPLICATION INFORMATION The TLV700xx/TLV701xx belong to a new family of next-generation value LDO regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for RF portable applications. This family of regulators offers sub-bandgap output voltages down to 0.7 V, current limit, and thermal protection, and is specified from –40°C to +125°C. Input and Output Capacitor Requirements 1.0-mF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV700xx/TLV701xx are designed to be stable with an effective capacitance of 0.1 mF or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 mF. This effective capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-mF effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications. Note that using a 0.1-mF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions would be less than 0.1 mF. Maximum ESR should be less than 200 mΩ. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-mF to 1.0-mF, low ESR capacitor across the IN pin and GND in of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-mF input capacitor may be necessary to ensure stability. Board Layout Recommendations to Improve PSRR and Noise Performance Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR performance. Internal Current Limit The TLV700xx/TLV701xx internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details. The PMOS pass element in the TLV700xx/TLV701xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. Shutdown The enable pin (EN) is active high. The device is enabled when voltage at EN pin goes above 0.9V. This relatively lower value of voltage required to turn the LDO on can be exploited to power the LDO with a GPIO of recent processors whose GPIO Logic 1 voltage level is lower than traditional microcontrollers. The device is turned OFF when the EN pin is held at less than 0.4V. When shutdown capability is not required, EN can be connected to the IN pin. The TLV701 has an internal active pull-down circuitry that discharges the output with a time constant of: (120 · RL) t= · COUT (120 + RL) with: • • Copyright © 2009–2010, Texas Instruments Incorporated RL = Load resistance COUT = Output capacitor Submit Documentation Feedback (1) 11 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 Dropout Voltage The TLV700xx/TLV701xx use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 15 in the Typical Characteristics section. Transient Response As with any regulator, increasing the size of the output capacitor reduces over-/undershoot magnitude but increases the duration of the transient response. Undervoltage Lockout (UVLO) The TLV700xx/TLV701xx use an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating properly. Thermal Information Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. 12 Submit Documentation Feedback www.ti.com For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TLV700xx/TLV701xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV700xx/TLV701xx into thermal shutdown degrades device reliability. Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 2. PD = (VIN - VOUT) ´ IOUT (2) Package Mounting Solder pad footprint recommendations for the TLV700xx/TLV701xx are available from the Texas Instruments web site at www.ti.com. The recommended land patterns for the DSE, DDC, and DCK packages are shown in Figure 24, Figure 25, and Figure 26, respectively. Figure 27, Figure 28, and Figure 29 show the mechanical package dimensions for the DSE, DDC, and DCK packages, respectively. Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 (1) Publication IPC-7351 is recommended for alternate designs. (2) For more information, refer to TI application notes SCBA017 and SLUA271 (Quad Flatpack No-Lead Logic Packages and QFN/SON PCB Attachment, respectively) for specific thermal information, via requirements, and additional recommendations for board layout. These documents are available at the Texas Instruments web site (http://www.ti.com) by searching for the literature number. (3) Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for stencil design considerations. (4) Customers should contact their board fabrication site for minimum solder mask tolerances between signal pads. Figure 24. Recommended Land Pattern for DSE Package Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 Example Board Layout www.ti.com Stencil Openings Based on Stencil Thickness of 0,127 mm (.005 in) (1) All linear dimensions are in millimeters. (2) Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined pad. (3) Publication IPC-7351 is recommended for alternate designs. (4) Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Example stencil design based on a 50% volumetric load solder paste. Refer to IPC-7525 for other stencil recommendations. Figure 25. Recommended Land Pattern for DDC Package 14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 Example Board Layout Stencil Openings Based on Stencil Thickness of 0,127 mm (.005 in) (1) All linear dimensions are in millimeters. (2) Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined pad. (3) Publication IPC-7351 is recommended for alternate designs. (4) Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Example stencil design based on a 50% volumetric load solder paste. Refer to IPC-7525 for other stencil recommendations. Figure 26. Recommended Land Pattern for DCK Package Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 15 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 (1) All linear dimensions are in millimeters. (2) Small outline no-lead (SON) package configuration. www.ti.com Figure 27. DSE Package Dimensions 16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 (1) All linear dimensions are in millimeters. (2) Body dimensions do not include mold flash or protrusion. (3) Falls within JEDEC MO-193 variation AB (pin 5). Figure 28. DDC Package Dimensions Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 17 TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 www.ti.com (1) All linear dimensions are in millimeters. (2) Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0,15 per side. (3) Falls within JEDEC MO-203 variation AA. Figure 29. DCK Package Dimensions 18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TLV700xx TLV701xx www.ti.com SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September, 2009) to Revision A Page • Changed Very low dropout bullet in Features list ................................................................................................................. 1 • Revised SOT23-5 package name to TSOT23-5 throughout document ................................................................................ 1 • Added TLV701xx device to document; updated references to specific devices to reflect new device availability ............... 1 • Changed last sentence of Description section ..................................................................................................................... 1 • Deleted Revised condition statement for Electrical Characteristics ..................................................................................... 3 • Updated test conditions for Line regulation parameter ......................................................................................................... 3 • Changed Dropout voltage parameter; added separate performance specifications and different test conditions ............... 3 • Added new test condition and performance specification for Ground pin current (shutdown) parameter ............................ 3 • Changed test condition for Enable pin current parameter .................................................................................................... 3 • Added Active pulldown resistance parameter ....................................................................................................................... 3 • Added figure number to TLV700xx functional block diagram ............................................................................................... 4 • Added Figure 2 ..................................................................................................................................................................... 4 • Revised Shutdown section ................................................................................................................................................. 11 Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 14-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV70012DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70012DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70012DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70012DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70012DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70012DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70015DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70015DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70015DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70015DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70015DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70015DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70018DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70018DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70018DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70018DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70018DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70018DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70025DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70025DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70025DSER PREVIEW WSON DSE 6 3000 TBD Call TI Call TI TLV70025DSET PREVIEW WSON DSE 6 250 TBD Call TI Call TI TLV70028DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70028DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70028DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70028DDCT ACTIVE SOT DDC 5 250 CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 Green (RoHS & Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 14-May-2010 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV70028DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70028DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70029DSER ACTIVE WSON DSE 6 3000 TBD Call TI Call TI TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) TLV70029DSET ACTIVE WSON DSE 6 250 TLV70030DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70030DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70030DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70030DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70030DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70030DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70033DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70033DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70033DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70033DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70033DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70033DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70133DSER PREVIEW WSON DSE 6 3000 TBD Call TI Call TI TLV70133DSET PREVIEW WSON DSE 6 250 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 14-May-2010 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV70033 : • Automotive: TLV70033-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TLV70012DSER WSON DSE 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70012DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70015DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70015DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70015DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70015DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70015DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70015DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70018DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70018DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70018DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70018DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70018DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70018DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70028DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70028DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70028DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70028DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2010 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV70028DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70028DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70030DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70030DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70030DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70030DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70030DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70030DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70033DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70033DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70033DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70033DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70033DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70033DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70012DSER WSON DSE 6 3000 195.0 200.0 45.0 TLV70012DSET WSON DSE 6 250 195.0 200.0 45.0 TLV70015DCKR SC70 DCK 5 3000 195.0 200.0 45.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2010 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70015DCKT SC70 DCK 5 250 195.0 200.0 45.0 TLV70015DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70015DDCT SOT DDC 5 250 195.0 200.0 45.0 TLV70015DSER WSON DSE 6 3000 195.0 200.0 45.0 TLV70015DSET WSON DSE 6 250 195.0 200.0 45.0 TLV70018DCKR SC70 DCK 5 3000 195.0 200.0 45.0 TLV70018DCKT SC70 DCK 5 250 195.0 200.0 45.0 TLV70018DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70018DDCT SOT DDC 5 250 195.0 200.0 45.0 TLV70018DSER WSON DSE 6 3000 195.0 200.0 45.0 TLV70018DSET WSON DSE 6 250 195.0 200.0 45.0 TLV70028DCKR SC70 DCK 5 3000 195.0 200.0 45.0 TLV70028DCKT SC70 DCK 5 250 195.0 200.0 45.0 TLV70028DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70028DDCT SOT DDC 5 250 195.0 200.0 45.0 TLV70028DSER WSON DSE 6 3000 195.0 200.0 45.0 TLV70028DSET WSON DSE 6 250 195.0 200.0 45.0 TLV70030DCKR SC70 DCK 5 3000 195.0 200.0 45.0 TLV70030DCKT SC70 DCK 5 250 195.0 200.0 45.0 TLV70030DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70030DDCT SOT DDC 5 250 195.0 200.0 45.0 TLV70030DSER WSON DSE 6 3000 195.0 200.0 45.0 TLV70030DSET WSON DSE 6 250 195.0 200.0 45.0 TLV70033DCKR SC70 DCK 5 3000 195.0 200.0 45.0 TLV70033DCKT SC70 DCK 5 250 195.0 200.0 45.0 TLV70033DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70033DDCT SOT DDC 5 250 195.0 200.0 45.0 TLV70033DSER WSON DSE 6 3000 195.0 200.0 45.0 TLV70033DSET WSON DSE 6 250 195.0 200.0 45.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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