TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 300-mA, Low-IQ, Low-Dropout Regulator FEATURES DESCRIPTION • Very Low Dropout: – 37 mV at IOUT = 50 mA, VOUT = 2.8 V – 75 mV at IOUT = 100 mA, VOUT = 2.8 V – 220mV at IOUT = 300 mA, VOUT = 2.8 V • 2% Accuracy • Low IQ: 35 μA • Fixed-Output Voltage Combinations Possible from 1.2 V to 4.8 V • High PSRR: 68 dB at 1 kHz • Stable with Effective Capacitance of 0.1 μF(1) • Thermal Shutdown and Overcurrent Protection • Packages: SOT23-5 and 1,5mm × 1,5mm SON-6 The TLV702xx series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low-dropout voltage make this series of devices ideal for a wide selection of battery-operated handheld equipment. All device versions have thermal shutdown and current limit for safety. 1 234 (1) See the Input and Output Capacitor Requirements in the Application Information section. The TLV702xxP series also provides an active pulldown circuit to quickly discharge the outputs. APPLICATIONS • • • • • • • Furthermore, these devices are stable with an effective output capacitance of only 0.1 μF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load. Wireless Handsets Smart Phones, PDAs MP3 Players ZigBee® Networks Bluetooth® Devices Li-Ion Operated Handheld Products WLAN and Other PC Add-on Cards The TLV702xx series of LDO linear regulators are available in SOT23-5 and 1,5mm × 1,5mm SON-6 packages. VIN IN OUT CIN COUT VOUT 1 mF Ceramic TLV702xx TLV702xxDBV SOT23-5 (TOP VIEW) IN 1 GND 2 EN 3 5 4 TLV702xxDSE 1,5mm ´ 1,5mm SON (TOP VIEW) OUT IN 1 6 EN GND 2 5 N/C OUT 3 4 N/C On Off EN GND Typical Application Circuit (Fixed-Voltage Versions) N/C 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG. ZigBee is a registered trademark of the ZigBee Alliance. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (2) PRODUCT VOUT TLV702xx(x)Pyyyz XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475 = 4.75 V). P is optional; devices with P have an LDO regulator with an active output discharge. YYY is the package designator. Z is package quantity. Use "R" for reel (3000 pieces), and "T" for tape (250 pieces). (1) (2) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Output voltages from 1.2 V to 4.8 V in 50-mV increments are available. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Voltage (2) Current (source) MAX IN –0.3 +6.0 V EN –0.3 +6.0 V OUT –0.3 +6.0 V OUT Internally Limited Output short-circuit duration Indefinite Temperature Operating virtual junction, TJ –55 +150 Storage, Tstg –55 +150 °C 2 kV 500 V Human Body Model (HBM) QSS 009-105 (JESD22-A114A) Electrostatic Discharge Rating (3) (1) (2) (3) UNIT MIN Charge Device Model (CDM) QSS 009-147 (JESD22-C101B.01) °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. DISSIPATION RATINGS (1) (1) 2 PACKAGE RθJA TA < +25°C TA = +70°C TA = +85°C DBV 200°C/W 500mW 275mW 200mW DSE 180°C/W 555mW 305mW 222mW For board details, see the Thermal Information section. Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = 0.9 V, COUT = 1.0 μF, and TJ = –40°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. SPACE PARAMETER TEST CONDITIONS VIN Input voltage range VOUT DC output accuracy –40°C ≤ TJ ≤ +125°C ΔVO/ΔVIN Line regulation ΔVO/ΔIOUT Load regulation VDO ICL IGND Output current limit Ground pin current TYP MAX 2.0 UNIT 5.5 V 0.5 +2 % VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA 1 5 mV 0 mA ≤ IOUT ≤ 300 mA 1 15 mV –2 VIN = 0.98 × VOUT(NOM), IOUT = 50 mA, VOUT = 2.8 V 37 mV VIN = 0.98 × VOUT(NOM), IOUT = 100 mA, VOUT = 2.8 V 75 mV VIN = 0.98 × VOUT(NOM), IOUT = 300 mA, VOUT = 2.35 V 260 375 mV 500 860 mA 35 55 μA VOUT = 0.9 × VOUT(NOM) 320 IOUT = 0 mA IOUT = 300 mA, VIN = VOUT + 0.5 V 370 μA VEN ≤ 0.4 V, VIN = 2.0 V 400 nA ISHDN Ground pin current (shutdown) PSRR Power-supply rejection ratio VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz 68 dB Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA 48 μVRMS VN tSTR Startup time (2) VEN(HI) Enable pin high (enabled) VEN(LO) Enable pin low (disabled) IEN UVLO RDISCHARGE (1) (2) Dropout voltage (1) MIN VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V, TJ = –40°C to +85°C COUT = 1.0 μF, IOUT = 300 mA V μA VIN rising 1.9 V VEN = 0 V 120 Ω Shutdown, temperature increasing +165 °C Reset, temperature decreasing +145 °C Active pulldown resistance (TLV702xxP only) Operating junction temperature 0.4 V 0.04 Undervoltage lockout TJ μs VIN 0 VIN = VEN = 5.5 V Thermal shutdown temperature μA 2 100 0.9 Enable pin current TSD 1 –40 +125 °C VDO is measured for devices with VOUT(NOM) ≥ 2.35 V. Startup time = time from EN assertion to 0.98 × VOUT(NOM). © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3 TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAMS IN OUT Current Limit Thermal Shutdown UVLO EN Bandgap LOGIC TLV702xx Series GND Figure 1. TLV702xx IN OUT Current Limit Thermal Shutdown UVLO EN 120W Bandgap LOGIC TLV702xxP Series GND Figure 2. TLV702xxP 4 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PIN CONFIGURATIONS DBV PACKAGE SOT23-5 (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 NC DSE PACKAGE 1,5mm × 1,5mm SON-6 (TOP VIEW) IN 1 6 EN GND 2 5 N/C OUT 3 4 N/C PIN DESCRIPTIONS PIN NAME SOT23-5 DBV SON-6 DSE DESCRIPTION IN 1 1 Input pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. See Input and Output Capacitor Requirements in the Application Information section for more details. GND 2 2 Ground pin Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode and reduces operating current to 1 μA, nominal. For TLV702xxP, output voltage is discharged through an internal 120-Ω resistor when device is shut down. EN 3 6 NC 4 4, 5 OUT 5 3 No connection. This pin can be tied to ground to improve thermal dissipation. Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = +25°C. LINE REGULATION LINE REGULATION 1.90 1.90 VOUT = 1.8 V IOUT = 10 mA 1.86 1.86 1.84 1.84 1.82 1.82 1.80 1.78 1.76 1.72 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 VOUT = 1.8 V IOUT = 300 mA 1.88 VOUT (V) VOUT (V) 1.88 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 1.70 2.1 2.6 3.1 3.6 4.1 VIN (V) 4.6 5.1 2.3 5.6 2.7 3.1 Figure 3. 3.5 3.9 VIN (V) 4.3 4.7 5.5 5.1 Figure 4. LOAD REGULATION DROPOUT VOLTAGE vs INPUT VOLTAGE 350 1.90 IOUT = 300mA VOUT = 1.8 V 1.88 300 1.86 250 1.82 VDO (mV) VOUT (V) 1.84 1.80 1.78 1.76 1.72 50 100 150 200 250 +125°C +85°C +25°C -40°C 50 0 2.25 1.70 0 150 100 +125°C +85°C +25°C -40°C 1.74 200 300 2.75 3.25 IOUT (mA) Figure 5. DROPOUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs TEMPERATURE 1.90 VOUT = 4.8 V VOUT = 1.8 V 1.88 250 1.86 1.84 VOUT (V) 200 VDO (mV) 4.75 4.25 Figure 6. 300 150 100 +125°C +85°C +25°C -40°C 50 0 1.82 1.80 1.78 1.76 10mA 150mA 200mA 1.74 1.72 1.70 0 50 100 150 IOUT (mA) Figure 7. 6 3.75 VIN (V) Submit Documentation Feedback 200 250 300 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 8. © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = +25°C. GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs LOAD 450 50 VOUT = 1.8 V 45 40 350 35 300 30 IGND (mA) IGND (mA) VOUT = 1.8 V 400 25 20 250 200 150 15 +125°C +85°C +25°C -40°C 10 5 +125°C +85°C +25°C -40°C 100 50 0 0 2.1 2.6 3.1 3.6 4.1 VIN (V) 4.6 5.1 0 5.6 100 50 Figure 9. 200 150 IOUT (mA) 250 300 Figure 10. GROUND PIN CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs INPUT VOLTAGE 2.5 50 VOUT = 1.8 V 45 VOUT = 1.8 V 2 40 ISHDN (mA) IGND (mA) 35 30 25 20 1.5 1 15 +125°C +85°C +25°C -40°C 0.5 10 5 0 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 2.1 110 125 2.6 3.1 3.6 4.1 VIN (V) Figure 11. 4.6 5.1 5.6 Figure 12. CURRENT LIMIT vs INPUT VOLTAGE POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 100 700 VOUT = 1.8 V IOUT = 10 mA 90 600 80 IOUT = 150 mA 70 PSRR (dB) ILIM (mA) 500 400 300 200 +125°C +85°C +25°C -40°C 100 60 50 40 30 20 10 VIN - VOUT = 0.5 V 0 0 2.3 2.7 3.1 3.5 3.9 VIN (V) Figure 13. © 2010–2011, Texas Instruments Incorporated 4.3 4.7 5.1 5.5 10 100 1k 10 k 100 k 1M 10 M Frequency (Hz) Figure 14. Submit Documentation Feedback 7 TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = +25°C. POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE VOUT = 1.8 V 1 kHz 70 PSRR (dB) 60 10 kHz 50 100 kHz 40 30 20 10 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY Output Spectral Noise Density (mV/ÖHz) 80 10 VOUT = 1.8 V IOUT = 10 mA CIN = COUT = 1 mF 1 0.1 0.01 0.001 10 2.8 100 1k LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE IOUT 0 mA 5 mV/div VOUT 10 mA 0 mA IOUT VOUT VOUT = 1.8 V 10 ms/div 10 ms/div Figure 17. Figure 18. LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE tR =tF = 1 ms 50 mA 0 mA 200 mA/div 300mA IOUT 100 mV/div 50 mA/div tR = tF = 1 ms 20 mV/div 10 M tR = tF = 1 ms 200 mA VOUT = 1.8 V VOUT IOUT 0 mA VOUT VOUT = 1.8 V 8 1M Figure 16. 20 mA/div 100 mA/div 100 k Figure 15. tR = tF = 1 ms 50 mV/div 10 k Frequency (Hz) Input Voltage (V) VOUT = 1.8 V 10 ms/div 10 ms/div Figure 19. Figure 20. Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = +25°C. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE 1 V/div 2.9 V VIN Slew Rate = 1 V/ms 2.9 V 2.3 V VIN VOUT VOUT = 1.8 V IOUT = 300 mA 5 mV/div 2.3 V 5 mV/div 1 V/div Slew Rate = 1 V/ms VOUT VOUT = 1.8 V IOUT = 1 mA 1 ms/div Figure 22. LINE TRANSIENT RESPONSE VIN RAMP UP, RAMP DOWN RESPONSE Slew Rate = 1 V/ms VOUT = 1.8 V IOUT = 300 mA 5.5 V 10 mV/div 2.1 V VIN VOUT = 1.8 V IOUT = 1 mA VIN 1 V/div 1 V/div 1 ms/div Figure 21. VOUT VOUT 1 ms/div Figure 23. © 2010–2011, Texas Instruments Incorporated 200 ms/div Figure 24. Submit Documentation Feedback 9 TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION The TLV702xx belongs to a new family of next-generation value LDO regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise and very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for portable RF applications. This family of regulators offers current limit and thermal protection, and is specified from –40°C to +125°C. INPUT AND OUTPUT CAPACITOR REQUIREMENTS 1.0-μF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV702xx is designed to be stable with an effective capacitance of 0.1 μF or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of lower-cost dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications. NOTE: Using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions would be less than 0.1 μF. Maximum ESR should be less than 200 mΩ. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1.0-μF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR performance. INTERNAL CURRENT LIMIT The TLV702xx internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details. The PMOS pass element in the TLV702xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. SHUTDOWN The enable pin (EN) is active high. The device is enabled when voltage at EN pin goes above 0.9V. This relatively lower value of voltage required to turn the LDO on can be exploited to power the LDO with a GPIO of recent processors whose GPIO Logic 1 voltage level is lower than traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4V. When shutdown capability is not required, EN can be connected to the IN pin. The TLV702xxP version has internal active pull-down circuitry that discharges the output with a time constant of: (120 · RL) t= · COUT (120 + RL) where: • • 10 Submit Documentation Feedback RL = Load resistance COUT = Output capacitor (1) © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com DROPOUT VOLTAGE The TLV702xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 15 in the Typical Characteristics section. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over-/undershoot magnitude but increases the duration of the transient response. UNDERVOLTAGE LOCKOUT (UVLO) The TLV702xx uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating properly. THERMAL INFORMATION Thermal protection disables the output when the junction temperature rises to approximately +165°C, allowing the device to cool. When the junction temperature cools to approximately +145°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. The internal protection circuitry of the TLV702xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV702xx into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Thermal performance data for TLV702xx were gathered using the TLV700 evaluation module (EVM), a 2-layer board with two ounces of copper per side. The dimensions and layout for the SOT23-5 (DBV) EVM are shown in Figure 25 and Figure 26. Corresponding thermal performance data are given in Table 1. Note that this board has provision for soldering not only the SOT23-5 package on the bottom layer, but also the SC-70 package on the top layer. The dimensions and layout of the SON-6 (DSE) EVM is shown in Figure 27 and Figure 28. Corresponding thermal performance data is again given in Table 1. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 2. PD = (VIN - VOUT) ´ IOUT (2) PACKAGE MOUNTING Solder pad footprint recommendations for the TLV702xx are available from the Texas Instruments web site at www.ti.com. The recommended land pattern for the DBV and DSE packages are shown in Figure 29 and Figure 30, respectively. Table 1. EVM Dissipation Ratings PACKAGE RθJA TA < +25°C TA = +70°C TA = +85°C DBV 200°C/W 500mW 275mW 200mW DSE 180°C/W 555mW 305mW 222mW © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 18.16 mm 20.7 mm Figure 25. HPA503 EVM Top Layer 18.16 mm 20.7 mm Figure 26. HPA503 EVM Bottom Layer 12 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 17 mm 20.5 mm Figure 27. DSE EVM Top Layer 17 mm 20.5 mm Figure 28. DSE EVM Bottom Layer © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 13 TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 Example Board Layout www.ti.com Stencil Openings Based on Stencil Thickness of 0,127 mm (.005 in) (1) All linear dimensions are in millimeters. (2) Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined pad. (3) Publication IPC-7351 is recommended for alternate designs. (4) Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Example stencil design based on a 50% volumetric load solder paste. Refer to IPC-7525 for other stencil recommendations. Figure 29. Recommended Land Pattern for DBV Package 14 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Figure 30. Recommended Land Pattern for DSE Package © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15 TLV702xx SLVSAG6B – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2010) to Revision B • Added SON-6 (DSE) package and related references to data sheet ................................................................................... 1 Changes from Original (September 2010) to Revision A • 16 Page Page Updated ordering number in Ordering Information table ...................................................................................................... 2 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) TLV70212DBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI TLV70212DBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI TLV70218DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70218DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70220PDBVR PREVIEW SOT-23 DBV 5 3000 TBD TLV70220PDBVT PREVIEW SOT-23 DBV 5 250 TBD TLV70225DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70225DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70225DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70225DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70228DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70228DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70228PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70228PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70229DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70229DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70230DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70230DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Call TI Call TI Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 21-Mar-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV70231DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70231DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70233DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70233DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70237DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70237DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV702475DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV702475DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2011 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TLV70218DBVR SOT-23 DBV 5 3000 180.0 8.4 TLV70225DBVR SOT-23 DBV 5 3000 180.0 TLV70225DBVT SOT-23 DBV 5 250 180.0 TLV70225DSER WSON DSE 6 3000 TLV70225DSET WSON DSE 6 TLV70228DBVR SOT-23 DBV TLV70228DBVT SOT-23 DBV TLV70228PDBVR SOT-23 TLV70228PDBVT TLV70229DSER W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 8.4 3.23 3.17 1.37 4.0 8.0 Q3 8.4 3.23 3.17 1.37 4.0 8.0 Q3 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70229DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70230DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV70230DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV70231DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV70231DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV70233DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV70233DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV70237DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2011 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV70237DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV702475DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV702475DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70218DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV70225DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV70225DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TLV70225DSER WSON DSE 6 3000 202.0 201.0 28.0 TLV70225DSET WSON DSE 6 250 202.0 201.0 28.0 TLV70228DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV70228DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TLV70228PDBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV70228PDBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TLV70229DSER WSON DSE 6 3000 202.0 201.0 28.0 TLV70229DSET WSON DSE 6 250 202.0 201.0 28.0 TLV70230DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV70230DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TLV70231DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2011 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70231DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TLV70233DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV70233DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TLV70237DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV70237DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 TLV702475DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TLV702475DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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