SC1486A Complete DDR1/2/3 Power Supply Controller POWER MANAGEMENT Description Features 1% DC accuracy Compatible with DDR1, DDR2 and DDR3 memory The SC1486A is a dual output constant on-time synchronous buck PWM controller optimized for cost effective mobile DDR1, DDR2 and DDR3 applications. Features include high efficiency, a fast dynamic response with no minimum on time, a REFIN input and a buffered REFOUT pin capable of sourcing 3mA. The excellent transient response means that SC1486A based solutions will require less output capacitance than competing fixed frequency converters. power requirements Constant on-time for fast dynamic response VBAT range = 1.8V – 25V DC current sense using low-side RDS(ON) sensing The output voltage of the first controller can be adjusted from 0.5V to VCCA. In DDR1 applications, this voltage is set to 2.5 volts, and in DDR2, 1.8V. A resistor divider from this supply is used to drive the REFIN pin of the second controller. A unity gain buffer drives the REFOUT pin to the same potential as REFIN. The second controller regulates its output to REFOUT. Two frequency setting resistors set the on-time for each buck controller. The frequency can thus be tailored to minimize crosstalk. The integrated gate drivers feature adaptive shoot-through protection and soft switching, requiring no gate resistors for the top MOSFET. Additional features include cycleby-cycle current limit, digital soft-start, over-voltage and under-voltage protection, and a Power Good output for each controller. or sense resistor Integrated reference buffer for VTT Low power S3 state with high-Z VTT Resistor programmable on-time Cycle-by-cycle current limit Digital soft-start PSAVE option for VDDQ Over-voltage/under-voltage fault protection <20µA shutdown current Low quiescent power dissipation Two Power Good indicators Separate enable for each switcher Integrated gate drivers with soft switching - no gate resistors required Efficiency >90% 28 Lead TSSOP (Lead-free available, fully WEEE and RoHS compliant) Applications Notebook computers CPU I/O supplies Handheld terminals and PDAs Typical Application Circuit VBAT 5VSUS 5VSUS VBAT D1 R1 U1 R2 RTON1 22 10R 23 VDDQ 24 R3 25 R5 26 27 PGOOD 28 R7 C5 C6 1nF 1uF EN/PSV1 TON1 SC1486A BST1 LX1 VCCA1 ILIM1 PGD1 VSSA1 0.1uF Q1 6 DH1 VOUT1 FB1 C1 7 C2 10uF 5 L1 R4 4 VDDQ + 3 VDDP1 Q2 R6 C3 0R 2 DL1 1 PGND1 VSSA1 C4 1uF VSSA1 VBAT 5VSUS VDDQ R8 10k 5VSUS 5VRUN D2 R10 8 RTON2 9 REFOUT R11 10 R12 10R 11 VTT 12 13 PGOOD C11 C12 1nF 100nF R15 10k VBAT R9 10R 14 C13 C14 1uF 1uF REFIN TON2 REFOUT VCCA2 FB2 PGD2 VSSA2 BST2 C7 21 0.1uF Q3 20 DH2 LX2 10uF 19 L2 18 ILIM2 C8 R13 VTT + 17 VDDP2 Q4 C9 R14 0R 16 DL2 15 PGND2 C10 VSSA2 1uF VSSA2 Revision: September 20, 2006 1 www.semtech.com SC1486A POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units TON1 to VSSA1, TON2 to VSSA2 -0.3 to +25.0 V DH1, BST1 to PGND1 and DH2, BST2 to PGND2 -0.3 to +30.0 V LX1 to PGND1 and LX2 to PGND2 -2.0 to +25.0 V VSSA1 to PGND1, and VSSA2 to PGND2 -0.3 to +0.3 V BST1 to LX1 and BST2 to LX2 -0.3 to +6.0 V DL1, ILIM1, VDDP1 to PGND1 and DL2, ILIM2, VDDP2 to PGND2 -0.3 to +6.0 V EN/PSV1, FB1, PGOOD1, VCCA1, VOUT1 to VSSA1 -0.3 to +6.0 V FB2, PGOOD2, VCCA2, REFIN, REFOUT to VSSA2 -0.3 to +6.0 V VCCA1 to EN/PSV1, FB1, PGOOD1, VOUT1 -0.3 to +6.0 V VCCA2 to FB2, PGOOD2, REFIN, REFOUT -0.3 to +6.0 V Thermal Resistance Junction to Ambient(5) θJA 70 °C/W Operating Junction Temperature Range TJ -40 to +125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C Electrical Characteristics Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Max Units Input Supplies V C C A 1, V C C A 2 5.0 4.5 5.5 V V D D P 1, V D D P 2 5.0 4.5 5.5 V VDDP2 Undervoltage Threshold VDDP2 falling VDDP2 Undervoltage Hysteresis 3.5 V 250 mV VDDP1, VDDP2 Operating Current FB > regulation point, ILOAD = 0A 70 150 µA VCCA1, VCCA2 Operating Current FB > regulation point, ILOAD = 0A 700 1100 µA VCCA2 Standby Current VDDP2 < VDDP2 UV threshold, no load on REFOUT 125 µA RTON = 1M 15 µA TON1, TON2 Operating Current REFIN Bias Current 2006 Semtech Corp. REFIN = 1.25 2 1 µA www.semtech.com SC1486A POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Units Max Input Supplies (Cont.) Shutdown Current EN/PSV1 = 0V -5 -10 µA V C C A 1, V C C A 2 5 10 µA TON1, TON2, VDDP1 0 1 µA VCCA = 4.5V to 5.5V 0.500 -1% +1% V 0.5 VC C A V Controller Error Comparator Threshold (FB1 Turn ON Threshold) VDDQ Output Voltage Range REFOUT Source Capability 3 REFOUT DC Accuracy no load, REFIN = 1.25 Error Comparator Threshold (FB2 Turn ON Threshold) VCCA = 4.5V to 5.5V On-Time, VBAT = 2.5V 1.24 1.26 mA 1.238 1.262 V REFOUT REFOUT -10mV REFOUT +10mV V RTON = 1MΩ, VOUT = 1.25V 1761 1497 2025 ns RTON = 500kΩ, VOUT = 1.25V 936 796 1076 ns 550 ns Minimum Off Time 400 VOUT Input Resistance (VDDQ Controller) 500 FB1 Input Bias Current kΩ -1.0 FB2 Input Bias Current +1.0 2.5 µA µA Over-Current Sensing ILIM Source Current DL High Current Comparator Offset 10 PGND - ILIM 9 11 µA -10 +10 mV PSAVE Zero-Crossing Threshold PGND - LX EN/PSV1 = 5V 5 mV RILIM = 5kΩ 50 35 65 mV RILIM = 10kΩ 100 80 120 mV RILIM = 20kΩ 200 170 230 mV -125 -160 -90 mV Fault Protection Current Limit (Positive) (PGND-LX) (2) Current Limit (Negative) (PGND-LX) 2006 Semtech Corp. 3 www.semtech.com SC1486A POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Max Units Fault Protection (Cont.) VDDQ - Output Under-Voltage Fault With respect to internal ref. -30 -40 -25 % VTT - Output Under-Voltage Fault With respect to REFOUT -20 -28 -15 % VDDQ Output Over-Voltage Fault With respect to internal ref. +10 +8 +12 % 2.0 1.9 2.1 V VTT Output Over-Voltage Fault Over-Voltage Fault Delay FB forced above OV threshold PGD Low Output Voltage Sink 1mA 0.4 V FB in regulation, PGD = 5V 1 µA PGD Leakage Current PGD UV Threshold PGD OV Threshold (VDDQ) VCCA1,VCCA2 Under Voltage Over Temperature Lockout µs With respect to internal reference for VDDQ and REFOUT for VTT -10 -15 -8 % With respect to internal ref. +10 +8 +12 % 2.0 1.9 2.1 V PGD OV Threshold (VTT) PGD Fault Delay 5 FB forced outside PGD window 5 Falling (100mV hysteresis) 4.0 10°C Hysteresis 165 µs 3.7 4.3 V °C Inputs/Outputs Logic Input Low Voltage EN/PSV1 low Logic Input High Voltage EN High, PSV low (Floating) Logic Input High Voltage EN/PSV1 high REFIN EN Threshold REFIN rising REFIN EN Hysteresis EN/PSV1 Input Resistance 1.2 2.0 V 3.1 0.50 V V 0.60 V 30 mV R pullup to VCCA1 1.5 MΩ R pulldown to VSSA1 1.0 EN/PSV1 high to PGD1 high, REFIN high to PGD2 high 440 clks(3) EN/PSV1 high to UV high, REFIN high to UV high 440 clks(3) Soft Start Soft-Start Ramp Time Under-Voltage Blank Time 2006 Semtech Corp. 4 www.semtech.com SC1486A POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Units Max Gate Drivers DH or DL rising 30 DL low 0.8 DL = 2.5V 3.1 DL high 2 DL = 2.5V 1.3 DH Pull-Down Resistance DH low, BST - LX = 5V 2 4 Ω DH Pull-Up Resistance DH high, BST - LX = 5V 2 4 Ω DH Sink/Source Current DL = 2.5V 1.3 Shoot-Through Delay (4) DL Pull-Down Resistance DL Sink Current DL Pull-Up Resistance DL Source Current ns 1.6 Ω Α 4 Ω A A Notes: (1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests. (3) clks = switching cycles. (4) Guaranteed by design. See Shoot-Through Delay Timing Diagram below. (5) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7. (6) This device is ESD sensitive. Use of standard ESD handling precautions is required. Shoot-Through Delay Timing Diagram LX DH DL DL tplhDL 2006 Semtech Corp. tplhDH 5 www.semtech.com SC1486A POWER MANAGEMENT Pin Configuration Ordering Information Top View DEVICE PACKAGE(1) SC1486AITSTR TSSOP-28 SC1486AITSTRT(2) TSSOP-28 SC1486AEVB(3) Evaluation Board Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead-free option. This product is fully WEEE, RoHS and J-STD-020B compliant. (3) Specify DDR, DDR2 or DDR3. (TSSOP-28) Pin Descriptions Pin # Pin Name Pin Function 1 PGND1 Power ground. 2 D L1 3 VD D P1 +5V supply voltage input for the gate drivers. Decouple this pin with a 1µF ceramic capacitor to PGND1. 4 ILIM1 Current limit input pin. Connect to drain of low-side MOSFET for RDS(ON) sensing or the source for resistor sensing through a threshold sensing resistor. 5 LX 1 Phase node (junction of top and bottom MOSFETs and the output inductor) connection. 6 DH1 Gate drive output for the high side MOSFET switch. 7 BST1 Boost capacitor connection for the high side gate drive. 8 REFIN Reference input. A 10kOhm + 10kOhm resistor divider from VDDQ to VSSA2 sets this voltage. A 0.1µF input filter capacitor is recommended. 9 TON2 This pin is used to sense VBAT through a pullup resistor, RTON2, and to set the top MOSFET on-time. Bypass this pin with a 1nF ceramic capacitor to VSSA2. 10 REFOUT Buffered REFIN output. The second controller regulates to this voltage. Connect a series 10 Ohm and 1µF from this pin to VSSA2. 11 VC C A2 Supply voltage input for the analog supply. Use a 10 Ohm/1µF RC filter from 5VSUS to VSSA2. 12 FB 2 13 PGD2 Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. 14 VSSA2 Ground reference for analog circuitry for output 2. Connect to bottom of output capacitor for output 2. 2006 Semtech Corp. Gate drive output for the low side MOSFET switch. Feedback input for output 2. Connect to the output at the output capacitor. 6 www.semtech.com SC1486A POWER MANAGEMENT Pin Descriptions (Cont) 15 PGND2 16 D L2 17 VD D P2 +5V supply voltage input for the gate drivers. Decouple this pin with a 1µF ceramic capacitor to PGND2. 18 ILIM2 Current limit input pin. Connect to drain of low-side MOSFET for RDS(ON) sensing or the source for resistor sensing through a threshold sensing resistor. 19 LX 2 Phase node (junction of top and bottom MOSFETs and the output inductor) connection. 20 DH2 Gate drive output for the high side MOSFET switch. 21 BST2 Boost capacitor connection for the high side gate drive. 22 EN/PSV1 Enable/Power Save input pin. Pull down to VSSA1 to shut down this output. Pull up to enable this output and activate PSAVE mode. Float to enable this output and activate continuous conduction mode (CCM). If floated, bypass to VSSA1 with a 10nF ceramic capacitor. 23 TON1 This pin is used to sense VBAT through a pullup resistor, RTON1, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA1. 24 VOUT1 Output voltage sense input for output 1. Connect to the output at the output capacitor. 25 VC C A1 Supply voltage input for the analog supply. Use a 10Ohm/ 1µF RC filter from 5VSUS to VSSA1. 26 FB 1 27 PGD1 Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. 28 VSSA1 Ground reference for analog circuitry for output 1. Connect to bottom of output capacitor for output 1. 2006 Semtech Corp. Power ground. Gate drive output for the low side MOSFET switch. Feedback input. Connect to a resistor divider located at the IC from VOUT1 to VSSA1 to set the output voltage from 0.5V to VCCA1. 7 www.semtech.com SC1486A POWER MANAGEMENT Block Diagram VCCA1 (25) POR / SS OT EN/SPV1 (22) BST1 (7) TON1 (23) ON TON VOUT1 (24) OFF PWM HI CONTROL LOGIC DH1 (6) LX1 (5) TOFF OC 1.5V REF ISENSE ZERO I + FB1 (26) ILIM1 (4) VDDP1 (3) X3 LO PGD1 (27) DL1 (2) PGND1 (1) OV FAULT MONITOR VSSA1 (28) UV REF + 10% REF - 10% REF - 30% VCCA2 (11) POR / SS REFIN (8) OT VDDP2 REF BUFFER BST2 (21) TON2 (9) ON TON OFF PWM CONTROL LOGIC HI DH2 (20) LX2 (19) TOFF OC REFOUT (10) ZERO I + ISENSE FB2 (12) ILIM2 (18) VDDP2 (17) + LO PGD2 (13) DL2 (16) PGND2 (15) OV VSSA2 (14) FAULT MONITOR UV 2V REF - 10% REF - 20% FIGURE 1 - SC1486A Block Diagram 2006 Semtech Corp. 8 www.semtech.com SC1486A POWER MANAGEMENT Application Information This input voltage-proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need for a clock generator. For VOUT < 3.3V: +5V Bias Supplies The SC1486A requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator. To minimize channel to channel crosstalk, each controller has 4 supply pins, VDDP, PGND, VCCA and VSSA. To avoid interference between outputs, each controller has its own ground reference, VSSA, which should be tied by a single trace to PGND at the negative terminal of that controller’s output capacitor (see Layout Guidelines). All external components referenced to VSSA in the schematic should be connected to the appropriate VSSA trace. The supply decoupling capacitor for controller 1 should be tied between VCCA1 and VSSA1. Likewise, the supply decoupling capacitor for controller 2 should be tied between VCCA2 and VSSA2. A 10Ω resistor should be used to decouple each VCCA supply from the main VDDP supplies. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to the ground plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, VSSA1 and VSSA2 must be connected to the PGND plane at the negative terminal of their respective output capacitors only. The VDDP1 and VDDP2 inputs provide power to the upper and lower gate drivers. A decoupling capacitor for each supply is required. No series resistor between VDDP and 5V is required. See layout guidelines for more details. V t ON = 3.3 x10 −12 • (R TON + 37 x10 3 ) • OUT + 50ns VIN For 3.3V ≤ VOUT ≤ 5V: V t ON = 0.85 • 3.3 x10 −12 • (R TON + 37 x10 3 ) • OUT + 50ns VIN RTON is a resistor connected from the input supply to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1nF ceramic capacitor. Enable & Psave The EN/PSV pin enables the VDDQ (2.5V or 1.8V) supply. REFIN and VDDP2 enable the VTT (1.25V or 0.9V) supply. The VTT and VDDQ supplies may be enabled independently, however it is usual to use a resistor divider from VDDQ to generate REFIN, so if VDDQ is not present, VTT will not be present. When EN/PSV1 is tied to VCCA the VDDQ controller is enabled and power save will also be enabled. When the EN/PSV pin is tri-stated, an internal pull-up will activate the VDDQ controller and power save will be disabled. If PSAVE is enabled, the SC1486A PSAVE comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (LX) to PGND. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve light-load efficiency and add hysteresis, the on-time is increased by 50% in power save. The efficiency improvement at light-loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when psave is enabled. Pseudo-fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (see Figure 1, SC1486A Block Diagram). The output ripple voltage developed across the output filter capacitor’s ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. On-Time One-Shot (tON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. 2006 Semtech Corp. 9 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) OUT1 Output Voltage Selection The output voltage is set by the feedback resistors R10 & R13 of Figure 2 below. The internal reference is 1.5V, so the voltage at the feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can be set to a minimum of 0.5V. The equation for setting the output voltage is: 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below: INDUCTOR CURRENT R10 VOUT= 1+ • 0.5 R13 PWR_SRC 5VSUS VCCA1 R1 C4 C3 C2 C1 10u/25V 1210 10u/25V 1210 0u1/25V 0603 2n2/50V 0402 1.8V, 10A C12 0u1 0402 L1 + C13 330u/25m 7343 + 10R 0402 U1 IRF7811AV Q2 8 S 7 D S 6 D S 5 D D G 2u4 C14 FDS6676S 8 7 D 6 D 5 D D 330u/25m 7343 R3 1M 0402 1 2 3 4 D1 C8 3 SOD 323 1u 0603 1 6 C10 0u1 0603 7 Q3 S S S G 5 1 2 3 4 R5 13k3 4 0402 2 PGD1 27 VCCA1 22 TON1 R7 0R 0402 24 PGOOD1 C17 5VSUS R10 26 27p 0402 R14 470k 0402 1.8V VSSA1 45k3 0402 R13 17k4 0402 23 C20 VCCA1 C21 1n 0402 1u 0603 25 28 SC1486A VDDP1 VDDP2 PGND1 PGND2 DH1 DH2 BST1 BST2 LX1 ILIM1 DL1 PGD1 EN/PSV1 VOUT1 FB1 TON1 LX2 ILIM2 DL2 PGD2 FB2 REFIN REFOUT TON2 VCCA1 VCCA2 VSSA1 VSSA2 ILOAD ILIMIT 17 15 20 21 19 TIME 18 16 13 Valley Current-Limit Threshold Point 12 8 10 Figure 3: Valley Current Limiting 9 11 14 The equation for the current limit threshold is as follows: Figure 2: Setting VDDQ Output Voltage ILIMIT = 10e -6 • Current Limit Circuit Current limiting of the SC1486A can be accomplished in two ways. The on-state resistance of the low-side MOSFETs can be used as the current sensing element or sense resistors in series with the low-side sources can be used if greater accuracy is desired. R DS(ON) sensing is more efficient and less expensive. In both cases, the RILIM resistors between the ILIM pin and LX pin set the over current threshold. This resistor R ILIM is connected to a 10µA current source within the SC1486A which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resisor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. In an extreme overcurrent situation, the top MOSFET will never turn back on and eventually the part will latch off due to output undervoltage (see Output Undervoltage Protection). RILIM A R SENSE Where (referring to Figure 2) RILIM is R5 and RSENSE is the RDS(ON) of Q3. For resistor sensing, a sense resistor is placed between the source of Q3 and PGND. The current through the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches the voltage drop across RILIM, a positive over-current exists and the high side MOSFET will not be allowed to turn on. When using an external sense resistor RSENSE is the resistance of the sense resistor. The current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to PGND through the inductor and bottom MOSFET). In this case, when the bottom MOSFET is turned on, the phase node, LX, will be higher than PGND initially. The SC1486A monitors the voltage at LX, and if it is greater than a set threshold voltage of 140mV (nom.) the bottom MOSFET is turned off. The device then waits for approximately 2µs and then DL goes high for 300ns (typ.) once more to sense the current. This repeats until either the over-current condition goes away or the part The current sensing circuit actually regulates the inductor valley current (see Figure 3). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 2006 Semtech Corp. IPEAK 10 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Current Limit Circuit (Cont.) latches off due to output overvoltage (see Output Overvoltage Protection). period of 440 switching cycles. The VTT switcher operates slightly differently in order to implement Suspend to RAM (S3) mode. VDDP2 is used to enable the switcher. If REFIN is greater than ~0.5V and VDDP2 is less than ~3.25V, REFOUT will be present but the VTT switcher will be disabled (VTT = high-Z). If REFIN is greater than ~0.5V and VDDP2 is greater than ~3.25V both REFOUT and the VTT switcher will be enabled. Power Good Output Each controller has its own power good output. Power good is an open-drain output and requires a pull-up resistor. When VDDQ is 10% above or below its set voltage, or VTT is 2V or 10% below REFOUT, PGD for that output gets pulled low. It is held low until the output voltage returns to within these limits. PGD is also held low during start-up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5µs delay built into the PGD circuitry to prevent false transitions. The ramp occurs in four steps: 1) 110 cycles at 25% ILIM with double minimum off-time (for purposes of the on-time one-shot there is an internal positive offset of 120mV to VOUT during this period to aid in startup) 2) 110 cycles at 50% ILIM with normal minimum off-time 3) 110 cycles at 75% ILIM with normal minimum off-time 4) 110 cycles at 100% ILIM with normal minimum off-time. At this point the output undervoltage and power good circuitry is enabled. There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V (nom.) the output drivers are shut down and tristated. Output Overvoltage Protection When VDDQ exceeds 10% of its set voltage or VTT exceeds 2V, the low side MOSFET for that output is latched on. It stays latched on and the controller is latched off until reset (see below). There is a 5µs delay built into the OV protection circuit to prevent false transitions. An OV fault in VTT will not affect VDDQ. An OV fault in VDDQ will shut down VTT if VDDQ is used to generate REFIN. Note: to reset VDDQ from any fault, VCCA1 or EN/PSV1 must be toggled. To reset VTT from a fault, VCCA2 or REFIN must be toggled. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off (below ~1V). Conversely, it monitors the phase node, LX, to determine the state of the high side MOSFET, and prevents the low-side MOSFET from turning on until DH is fully off (LX below ~1V). Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. Output Undervoltage Protection When the output is 30% (20% for VTT) below its set voltage the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset (see below). There is a 5µs delay built into the UV protection circuit to prevent false transitions. A UV fault in VTT will not affect VDDQ. A UV fault in VDDQ will shut down VTT if VDDQ is used to generate REFIN. Note: to reset VDDQ from any fault, VCCA1 or EN/PSV1 must be toggled. To reset VTT from a fault, VCCA2 or REFIN must be toggled. DDR Reference Buffer The reference buffer is capable of driving 3mA and sinking 25µA. Since the output is class A, if additional sinking is required an external pulldown resistor can be added. Make sure that the ground side of this pulldown is tied to VSSA2. As with most opamps, a small resistor is required when driving a capacitive load. To ensure stability use either a 10Ω resistor in series with a 1µF capacitor or a 100Ω resistor in series with a 0.1µF capacitor from REFOUT to AGND2. Since it is possible to have as much as 10µF to 20µF of capacitance at the memory socket or on-board the DIMMs, it is recommended that a 0Ω resistor is placed between REFOUT and the DIMM sockets. This allows the POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA1 and VCCA2 exceed 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high until VCCA rises above 4.2V. At this time the circuit will come out of UVLO and begin switching, and with the softstart circuit enabled, will progressively limit the output current (by limiting the current out of the ILIM pin) over a predetermined time 2006 Semtech Corp. 11 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) addition of extra resistance between REFOUT and the DIMMs to avoid spurious OVP at startup, which can occur if REFOUT rises really slowly and VTT overshoots it. The extra resistance allows REFOUT to rise faster, avoiding this issue. ripple is 40mV with VIN = 25V, then the DC output voltage will be 1.27V. 1486 System DC Accuracy (VDDQ Controller) Two IC parameters affect system DC accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. REFIN should also be filtered so that VDDQ ripple does not appear at the REFIN pin. If a resistor divider is used to create REFIN from VDDQ, then a 0.1µF capacitor from REFIN to VSSA2 will provide adequate filtering. The error comparator threshold does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by: DUTY = The on pulse in the SC1486A is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be 2.5V. If the ripple is 50mV with VIN = 6V, then the measured DC output will be 2.525V. If the ripple increases to 80mV with VIN = 25V, then the measured DC output will be 2.540V. t ON( MIN ) t ON( MIN ) + t OFF(MAX ) Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC1486A System DC Accuracy (VTT Controller) Two IC parameters effect system DC accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. The SC1486A regulates to the REFOUT voltage not the REFIN voltage. Since DDR specifications are written with respect to REFOUT, the offset of the reference buffer does not create a regulation error. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. It will not change the frequency. Switching frequency variation with load can be minimized by choosing MOSFETs with lower R DS(ON). High R DS(ON) MOSFETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. The error comparator offset does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. DDR Supply Selection The SC1486A can be configured so that VTT and VDDQ are generated directly from the battery. Alternatively, the VTT supply can be generated from the VDDQ supply. Since the battery configuration generally yields better efficiency and performance, the evaluation board is configured to generate both supplies from the battery. The on pulse in the SC1486A is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if REFOUT=1.25V, then the valley of the output ripple will be 1.25V. If the ripple is 20mV with VIN = 6V, then the DC output voltage will be 1.26V. If the 2006 Semtech Corp. 12 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Design Procedure Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. For purposes of demonstrating the procedure the VDDQ output for the schematic on page 17 will be designed. fSW _ VIN(MIN) = VOUT (VIN(MIN) • t ON _ VIN(MIN) )Hz and fSW _ VIN(MAX ) = The maximum input voltage (VIN(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (VIN(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a VIN range of 7.5V to 20.5V. VOUT (VIN(MAX ) • t ON _ VIN(MAX ) )Hz tON is generated by a one-shot comparator that samples VIN via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. For our DDR2 VDDQ example we select RtON = 1MΩ: Four parameters are needed for the output: 1) nominal output voltage, VOUT (for DDR2 this is 1.8V) 2) static (or DC) tolerance, TOL ST (for DDR2 this is +/-0.1V) 3) transient tolerance, TOLTR and size of transient (for DDR2 this is undefined, so assume +/-8% for purposes of this demonstration). 4) maximum output current, IOUT (we will design for 10A) tON_VIN(MIN) = 871ns and tON_VIN(MAX) = 350ns fSW_VIN(MIN) = 275kHz and fSW_VIN(MAX) = 251kHz Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place. Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. It is recommended that the two outputs are designed to operate at frequencies approximately 25% apart to avoid any possible interaction. It is also recommended that the higher frequency output is the lower output voltage output, since this will tend to have lower output ripple and tighter specifications. The default RtON values of 1MΩ and 649kΩ are suggested as a starting point, but these are not set in stone. The first thing to do is to calculate the on-time, tON, at VIN(MIN) and VIN(MAX), since this depends only upon VIN, VOUT and RtON. For VOUT < 3.3V: L VIN(MIN) = (VIN(MIN) − VOUT ) • t ON _ VIN(MIN) (0.5 • I ) H OUT and L VIN(MAX ) = (VIN(MAX ) − VOUT ) • t ON _ VIN(MAX ) (0.5 • I ) H OUT For our DDR2 VDDQ example: LVIN(MIN) = 1µH and LVIN(MAX) = 1.3µH We will select an inductor value of 2.4µH to reduce the ripple current, which can be calculated as follows: V t ON _ VIN(MIN) = 3.3 • 10 −12 • (R tON + 37 • 10 3 ) • OUT + 50 • 10 −9 s VIN(MIN) IRIPPLE _ VIN(MIN) = (VIN(MIN) − VOUT ) • t ON _ VIN(MIN) L A P −P and and V t ON _ VIN(MAX ) = 3.3 • 10 −12 • (R tON + 37 • 103 ) • OUT + 50 • 10 −9 s V IN( MAX ) IRIPPLE _ VIN(MAX ) = (VIN(MAX ) − VOUT ) • From these values of tON we can calculate the nominal switching frequency as follows: 2006 Semtech Corp. 13 t ON _ VIN(MAX ) L A P −P www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Design Procedure (Cont.) For our DDR2 VDDQ example: ERRTR = 144mV and ERRDC = 36mV, therefore RESR_TR(MAX) = 9.5mΩ for a full 10A load transient IRIPPLE_VIN(MIN) = 2.07AP-P and IRIPPLE_VIN(MAX) = 2.73AP-P We will select a value of 12.5mΩ maximum for our design, which would be achieved by using two 25mΩ output capacitors in parallel. From this we can calculate the minimum inductor current rating for normal operation: IINDUCTOR(MIN) = IOUT (MAX ) + IRIPPLE _ VIN(MAX ) 2 Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows: A (MIN) For our DDR2 VDDQ example: RESR (MIN ) = IINDUCTOR(MIN) = 11.4A(MIN) This criteria should be checked once the output capacitance has been determined. Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (R ESR_ST(MAX)) and transient ESR (R ESR_TR(MAX)): RESR _ ST (MAX ) = (ERR ST − ERRDC ) • 2 IRIPPLE _ VIN( MAX ) Now that we know the output ESR we can calculate the output ripple voltage: VRIPPLE _ VIN(MAX) = RESR • IRIPPLE _ VIN(MAX) VP −P Ohms and VRIPPLE _ VIN(MIN) = RESR • IRIPPLE _ VIN(MIN) VP−P Where ERRST is the static output tolerance and ERRDC is the DC error. The DC error will be 1% plus the tolerance of the feedback resistors, thus 2% total for 1% feedback resistors. For our DDR2 VDDQ example: VRIPPLE_VIN(MAX) = 34mVP-P and VRIPPLE_VIN(MIN) = 26mVP-P For our DDR2 VDDQ example: Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mVP-P at minimum V IN , and worst case no smaller than 10mV P-P . If VRIPPLE_VIN(MIN) is less than 15mVP-P the above component values should be revisited in order to improve this. Quite often a small capacitor, CTOP, is required in parallel with the top feedback resistor, RTOP, in order to ensure that V FB is large enough. C TOP should not be greater than 100pF. The value of CTOP can be calculated as follows, where R BOT is the bottom feedback resistor. Firstly calculating the value of ZTOP required: ERRST = 100mV and ERRDC = 36mV, therefore RESR_ST(MAX) = 47mΩ RESR _ TR (MAX ) = (ERR TR − ERR DC ) I IOUT + RIPPLE _ VIN(MAX ) 2 Ohms Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. For half of full load, divide the IOUT term by 2. Z TOP = RBOT • (VRIPPLE _ VIN(MIN) − 0.015 ) Ohms 0.015 Secondly calculating the value of CTOP required to achieve this: For our DDR2 VDDQ example: 2006 Semtech Corp. 3 2 • π • COUT • fSW 14 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Design Procedure (Cont.) C TOP 2 1 1 − Z TOP R TOP F = 2 • π • fSW _ VIN(MIN) C OUT (MIN) ZTOP = 12.8kΩ and CTOP = 32pF We will select a value of CTOP = 27pF. Calculating the value of VFB based upon the selected CTOP: VFB _ VIN(MIN) ( ) This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps my be calculated by substituting the desired current for the IOUT term. For our DDR2 VDDQ example we will use RTOP = 45.3kΩ and RBOT = 17.4kΩ, therefore: RBOT = VRIPPLE _ VIN(MIN) • 1 RBOT + 1 + 2 • π • fSW _ VIN(MIN) • CTOP R TOp I IOUT + RIPPLE _ VIN(MAX ) 2 =L• F 2 2 POSLIM TR − VOUT _ ST _ POS For our DDR2 VDDQ example: VP−P COUT(MIN) = 760µF. We will select 660µF, using two 330µF, 25mΩ capacitors in parallel. For our DDR2 VDDQ example: Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage: VFB_VIN(MIN) = 14.2mVP-P - good IIN(RMS ) = VOUT • (VIN(MIN) − VOUT ) • Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs: For our DDR2 VDDQ example: IIN(RMS) = 4.27ARMS Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10µF, 1210 size, 25V ceramic capacitor can handle a little more than 2ARMS. Refer to manufacturer’s data sheets. VOUT _ ST _ POS = VOUT + ERRDC V For our DDR2 VDDQ example: Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the “valley current”, which is the average output current minus half the ripple current. We use the maximum room temperature specification for MOSFET RDS(ON) at VGS = 4.5V for purposes of this calculation: VOUT_ST_POS = 1.836V POSLIM TR = VOUT • TOL TR V Where TOLTR is the transient tolerance. For our DDR2 VDDQ example: IVALLEY = IOUT − POSLIMTR = 1.944V IRIPPLE _ VIN(MIN) 2 A The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions. The minimum output capacitance is calculated as follows: 2006 Semtech Corp. IOUT A RMS VIN _ MIN 15 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Design Procedure (Cont.) RILIM = (IVALLEY • 1.2) • RDS( ON) • 1.4 10 • 10 − 6 Ohms For our DDR2 VDDQ example: IVALLEY = 8.97A and RILIM = 13.6kΩ We select the next lowest 1% resistor value: 13.3kΩ Thermal Considerations The junction temperature of the device may be calculated as follows: TJ = TA + PD • θ JA °C Where: TA = ambient temperature (°C) PD = power dissipation in (W) θJA = thermal impedance junction to ambient from absolute maximum ratings (°C/W) The power dissipation may be calculated as follows: ( PD = 2 • VCCA • IVCCA + Vg • Q g • f ) W Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) Inserting the following values as an example: TA = 85°C θJA = 37°C/W VCCA = 5V IVCCA = 1100µA (data sheet maximum) Vg = 5V Qg = 60nC f = 300kHz (enter the higher of the two set frequencies here) gives us: ( ) TJ = 85 + 2 • 5 • 1100 • 10 −6 + 5 • 60 • 10 −9 • 300 • 103 • 70 = 98 °C As can be seen, the heating effects due to internal power dissipation are minor, thus requiring no special consideration thermally during layout. 2006 Semtech Corp. 16 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Layout Guidelines One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2 should connect to power ground at their respective output capacitors only. Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip. Run them in a “quiet layer” if possible. Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the same side. Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer Current sense connections must always be made using Kelvin connections to ensure an accurate signal. We will examine the SC1486A DDR2 reference design used in the Design Procedure section while explaining the layout guidelines in more detail. PWR_SRC 5VSUS 5VRUN VCCA1 R1 C4 C3 C2 C1 10u/25V 1210 10u/25V 1210 0u1/25V 0603 2n2/50V 0402 1.8V, 10A C12 0u1 0402 L1 + C13 330u/25m 7343 + IRF7811AV 8 7 D 6 D 5 D D 2u4 C14 FDS6676S 8 7 D 6 D 5 D D 330u/25m 7343 Q2 S S S G Q3 S S S G R3 1M 0402 1 2 3 4 10R 0402 R5 R2 10R 0402 D1 C8 3 SOD 323 1u 0603 1 C10 0u1 0603 1 2 3 4 6 7 5 13k3 4 0402 2 PGD1 TON1 R7 0R 0402 VCCA1 27 22 24 PGOOD2 5VSUS PGOOD1 R14 470k 0402 C17 27p 0402 R15 470k 0402 1.8V VSSA1 R10 26 45k3 0402 R13 17k4 0402 PWR_SRC VCCA2 23 C20 VCCA1 C21 1n 0402 1u 0603 25 28 U1 SC1486A VDDP1 VDDP2 PGND1 PGND2 DH1 DH2 BST1 BST2 LX1 ILIM1 DL1 PGD1 EN/PSV1 VOUT1 FB1 TON1 LX2 ILIM2 DL2 PGD2 FB2 REFIN REFOUT TON2 VCCA1 VCCA2 VSSA1 VSSA2 5 17 C9 D2 R4 15 1u 0603 SOD 323 649k 0402 20 21 19 R6 8 4k32 10u/25V 1210 L2 1 1.8V REFOUT R9 R11 10R 0402 VCCA2 C22 C23 1u 0603 1n 0402 0.9V VSSA2 + 220u/25m 7343 TON2 9 0.9V, 1.5A 3u9 C15 2 PGD2 8 14 C5 0u1/25V 0603 7 12 11 C6 2n2/50V 0402 0402 16 10 C7 4 C11 0u1 0603 3 18 13 6 Q1 FDS6982S C18 C19 1u 0603 0u1 0402 R12 10k0 0402 C16 0u1 0402 R8 0R 0402 10k0 0402 Figure 4: DDR2 Reference Design and Layout Example Sample DDR2 Design Using SC1486A PWR_SRC = 7.5V to 20.5V VDDQ = 1.8V @ 10A VTT = 0.9V @ 1.5A Schematic is drawn to emphasize required grounding scheme 2006 Semtech Corp. 17 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Layout Guidelines (Cont.) PWR_SRC 5VSUS VCCA1 R1 C4 C3 C2 C1 10u/25V 1210 10u/25V 1210 0u1/25V 0603 2n2/50V 0402 1.8V, 10A L1 C12 + 0u1 0402 C13 + 330u/25m 7343 IRF7811AV Q2 8 S 7 D S 6 D S 5 D D G 2u4 C14 FDS6676S 8 7 D 6 D 5 D D 330u/25m 7343 Q3 S S S G R3 1M 0402 1 2 3 4 D1 C8 3 SOD 323 1u 0603 1 6 C10 0u1 0603 1 2 3 4 R5 7 5 13k3 4 0402 2 TON1 R7 0R 0402 PGOOD1 10R 0402 C17 5VSUS 27p 0402 R14 470k 0402 1.8V VSSA1 PGD1 27 VCCA1 22 24 R10 26 45k3 0402 23 R13 17k4 0402 C20 VCCA1 C21 1n 0402 1u 0603 25 28 U1 SC1486A VDDP1 VDDP2 PGND1 PGND2 DH1 DH2 BST1 BST2 LX2 LX1 ILIM2 ILIM1 DL1 DL2 PGD1 PGD2 EN/PSV1 FB2 REFIN VOUT1 REFOUT FB1 TON2 TON1 VCCA1 VCCA2 VSSA1 VSSA2 17 15 20 21 19 18 16 13 12 8 10 9 11 14 Figure 5: VDDQ Side Detail Note R7 is present to facilitate isolation of power ground and VSSA1 during layout 5VSUS 5VRUN R15 470k 0402 3 1 6 7 5 4 2 27 22 24 26 23 25 28 PWR_SRC VCCA2 PGOOD2 U1 R2 10R 0402 SC1486A VDDP1 VDDP2 PGND1 PGND2 DH1 BST1 LX1 ILIM1 DL1 DH2 BST2 LX2 ILIM2 DL2 PGD1 PGD2 EN/PSV1 FB2 VOUT1 FB1 TON1 REFIN REFOUT TON2 VCCA1 VCCA2 VSSA1 VSSA2 5 17 C9 D2 R4 15 1u 0603 SOD 323 649k 0402 20 21 19 8 4k32 PGD2 L2 1.8V REFOUT R9 VCCA2 C22 C23 1u 0603 1n 0402 0.9V VSSA2 + 220u/25m 7343 1 R11 10R 0402 0.9V, 1.5A 3u9 C15 TON2 9 14 10u/25V 1210 2 8 11 C5 0u1/25V 0603 7 12 10 C6 2n2/50V 0402 0402 16 13 C7 4 C11 0u1 0603 3 R6 18 6 Q1 FDS6982S C18 C19 1u 0603 0u1 0402 R12 10k0 0402 C16 0u1 0402 R8 0R 0402 10k0 0402 Figure 6: VTT Side Detail Note R8 is present to facilitate isolation of power ground and VSSA2 during layout 2006 Semtech Corp. 18 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Layout Guidelines (Cont.) The layout can be considered in two parts, the control section referenced to VSSA1/2 and the power section. Looking at the control section first, locate all components referenced to VSSA1/2 on the schematic and place these components at the chip. Connect VSSA1 and VSSA2 using either a wide (>0.020”) trace or a copper pour if room allows. Very little current flows in the chip ground therefore large areas of copper are not needed. 5VSUS 5VRUN VCCA1 VCCA2 R1 10R 0402 R2 10R 0402 C8 3 1u 0603 1 6 7 PWR_SRC 5 4 R3 1M 1.8V C17 27p 0402 VSSA1 2 PGD1 27 VCCA1 22 24 R10 26 45k3 0402 R13 17k4 0402 C20 1n 0402 TON1 23 VCCA1 C21 25 1u 0603 28 U1 VDDP1 PGND1 PWR_SRC SC1486A VDDP2 PGND2 DH1 DH2 BST1 BST2 LX1 ILIM1 DL1 PGD1 EN/PSV1 VOUT1 FB1 TON1 LX2 ILIM2 DL2 PGD2 FB2 REFIN REFOUT TON2 VCCA1 VCCA2 VSSA1 VSSA2 17 C9 R4 15 1u 0603 649k 0402 20 21 19 18 16 13 PGD2 12 1.8V 8 10 REFOUT 9 TON2 11 VCCA2 14 R9 R11 10R 0402 C22 C23 1u 0603 1n 0402 C18 C19 1u 0603 0u1 0402 R12 10k0 0402 10k0 0402 0.9V VSSA2 Figure 7: Components Connected to VSSA1 and VSSA2 Figure 8: ExampleVSSA Copper Pours (Left) and 0.020” Traces (Right) 2006 Semtech Corp. 19 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Layout Guidelines (Cont.) In Figure 8 on Page 19, all components referenced to VSSA1 and VSSA2 have been placed and have been connected using copper pours (left) or 0.020” traces (right). Note that there are two separate copper pours or traces, one for VSSA1 and one for VSSA2. Decoupling capacitors C2 and C22 are as close as possible to their pins, as are VDDP decoupling capacitors C8 and C9. C8 and C9 should connect to the ground plane using two vias each. 3 1 6 1.8V, 10A 7 C12 0u1 0402 + C13 330u/25m 7343 + 5 C14 4 2 330u/25m 7343 27 22 R7 0R 0402 C17 27p 0402 1.8V VSSA1 24 R10 26 45k3 0402 23 R13 17k4 0402 C20 VCCA1 C21 1n 0402 1u 0603 25 28 U1 SC1486A VDDP1 VDDP2 PGND1 PGND2 DH1 DH2 BST1 BST2 LX1 LX2 ILIM1 ILIM2 DL1 DL2 PGD1 PGD2 EN/PSV1 FB2 VOUT1 REFIN FB1 REFOUT TON1 TON2 VCCA1 VCCA2 VSSA1 VSSA2 17 15 20 21 19 18 16 13 12 8 10 9 11 14 ROUTE AS DIFFERENTIAL PAIR TO OUTPUT CAPACITORS 3 1 6 7 5 4 2 27 22 24 26 23 25 28 U1 SC1486A VDDP1 VDDP2 PGND1 PGND2 DH1 DH2 BST1 BST2 LX1 ILIM1 DL1 LX2 ILIM2 DL2 PGD1 PGD2 EN/PSV1 FB2 VOUT1 FB1 TON1 VCCA1 VSSA1 REFIN REFOUT TON2 VCCA2 VSSA2 17 15 20 21 0.9V, 1.5A 19 18 C15 C16 + 16 220u/25m 7343 13 12 0u1 0402 R8 0R 0402 8 10 9 11 VCCA2 C22 14 1u 0603 0.9V VSSA2 ROUTE AS DIFFERENTIAL PAIR TO OUTPUT CAPACITORS Figure 9: Differential Routing of Feedback and Ground Reference Traces 2006 Semtech Corp. 20 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Layout Guidelines (Cont.) Next, looking at the power section, the schematics in Figures 10 and 11 below show the power sections for VDDQ and VTT: C4 C3 C2 C1 10u/25V 1210 10u/25V 1210 0u1/25V 0603 2n2/50V 0402 1.8V, 10A L1 C12 + 0u1 0402 C13 + 330u/25m 7343 2u4 C14 330u/25m 7343 5 IRF7811AV Q2 8 S 7 D S 6 D D S 5 D G 1 2 3 4 Q1 FDS6982S FDS6676S 8 7 D 6 D 5 D D 1 2 3 4 8 Q3 S S S G 6 4 0603 3 7 C7 C6 C5 2n2/50V 0402 0u1/25V 0603 10u/25V 1210 L2 0.9V, 1.5A 3u9 C15 2 0u1 0402 220u/25m 7343 R7 0R 0402 1 Figure 10: VDDQ Power Section C16 + R8 0R 0402 Figure 11: VTT Power Section The highest di/dts occur in the input loops (see Figures 12 and 13 below) and thus these should be kept as small as possible. C4 C3 C2 C1 10u/25V 1210 10u/25V 1210 0u1/25V 0603 2n2/50V 0402 IRF7811AV Q2 8 S 7 D S 6 D S 5 D D G 4 3 2 1 1 2 3 4 5 6 Q1 FDS6982S C7 C6 C5 2n2/50V 0402 0u1/25V 0603 10u/25V 1210 4 Q3 FDS6676S 5 G D 6 S D 7 S D 8 S D 3 8 7 2 1 Figure 12: VDDQ Input Loop Figure 13: VTT Input Loop The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. See Figures 14 and 15 below for examples. Figure 14: VDDQ Power Component Placement And Copper Pours 2006 Semtech Corp. Figure 15: VTT Power Component Placement And Copper Pours 21 www.semtech.com SC1486A POWER MANAGEMENT Application Information (Cont.) Layout Guidelines (Cont.) Key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND (component-side) copper pours. 5) The two output inductors should not be placed adjacent to each other to avoid crosstalk. 6) Notice in Figures 10 and 11 on the previous page placement of 0Ω resistor at the bottom of the output capacitor to connect to VSSA1/2 for each output. Connecting the control and power sections should be accomplished as follows (see Figure 16 below): 1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a “quiet” layer away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3) BST is also a noisy node and should be kept as short as possible. 4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground plane. L1 2u4 IRF7811AV Q2 8 S 7 D S 6 D D S 5 D G 1 2 3 4 3 1 6 7 FDS6676S 8 7 D 6 D 5 D D Q3 S S S G 1 2 3 4 5 4 2 27 22 24 26 23 25 28 U1 SC1486A VDDP1 VDDP2 PGND1 PGND2 DH1 DH2 BST1 BST2 LX2 LX1 ILIM2 ILIM1 DL1 DL2 PGD2 PGD1 FB2 EN/PSV1 REFIN VOUT1 FB1 REFOUT TON2 TON1 VCCA1 VCCA2 VSSA1 VSSA2 5 17 15 20 21 19 6 Q1 FDS6982S 4 3 8 7 L2 3u9 18 16 2 13 12 1 8 10 9 11 14 PHASE NODES (BLACK) TO BE COPPER ISLANDS (PREFERRED) OR WIDE COPPER TR GATE DRIVE TRACES (RED) AND PHASE NODE TRACES (BLUE) TO BE WIDE COPPER TRACES (L:W < 20:1) AND AS SHORT AS POSSIBLE, WITH DL THE MOST CRITICAL Figure 16: Connecting Control and Power Sections 2006 Semtech Corp. 22 www.semtech.com SC1486A POWER MANAGEMENT Typical Characteristics VDDQ Efficiency (Power Save Mode) VDDQ Output Voltage (Power Save Mode) vs. Output Current vs. Input Voltage vs. Output Current vs. Input Voltage 100 1.820 VBAT = 8V 95 1.816 90 1.812 VBAT = 20V VBAT = 20V 1.808 80 VOUT (V) Efficiency (%) 85 75 70 1.804 1.800 65 1.792 60 1.788 55 1.784 50 VBAT = 8V 1.796 1.780 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 IOUT (A) 7 8 9 10 VDDQ Output Voltage (Continuous Conduction Mode) vs. Output Current vs. Input Voltage vs. Output Current vs. Input Voltage 1.820 VBAT = 8V 95 1.816 90 1.812 85 1.808 VBAT = 20V 80 VOUT (V) Efficiency (%) 6 VDDQ Efficiency (Continuous Conduction Mode) 100 75 70 VBAT = 20V 1.804 1.800 VBAT = 8V 1.796 65 1.792 60 1.788 55 1.784 50 1.780 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 IOUT (A) 5 6 7 8 9 10 IOUT (A) VTT Efficiency vs. VTT Output Voltage vs. Output Current vs. Input Voltage Output Current vs. Input Voltage 100 0.910 95 0.906 0.904 80 0.902 VOUT (V) 85 75 VBAT = 20V 70 REFIN = 0.9V 0.908 VBAT = 8V 90 Efficiency (%) 5 IOUT (A) 0.898 65 0.896 60 0.894 55 0.892 50 VBAT = 20V 0.900 VBAT = 8V 0.890 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.2 0.4 0.6 IOUT (A) 0.8 1.0 1.2 1.4 1.6 IOUT (A) Please refer to Figure 4 on Page 17 for test schematic 2006 Semtech Corp. 23 www.semtech.com SC1486A POWER MANAGEMENT Typical Characteristics (Cont.) VDDQ Switching Frequency (Continuous Conduction VTT Switching Frequency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage Mode) vs. Output Current vs. Input Voltage 350 450 REFIN = 0.9V 425 325 VBAT = 8V 400 VBAT = 8V fSW (kHz) fSW (kHz) 300 275 VBAT = 20V 250 375 350 325 300 225 VBAT = 20V 275 200 250 0 1 2 3 4 5 6 7 8 9 10 0.0 0.2 0.4 0.6 IOUT (A) 0.8 1.0 1.2 1.4 1.6 IOUT (A) VDDQ Switching Frequency (Power Save Mode) vs. Output Current vs. Input Voltage 350 VBAT = 8V 300 250 fSW (kHz) VBAT = 20V 200 150 100 50 0 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Please refer to Figure 4 on Page 17 for test schematic 2006 Semtech Corp. 24 www.semtech.com SC1486A POWER MANAGEMENT Typical Characteristics (Cont.) VDDQ Load Transient Response, Continuous Conduction Mode, 0A to 10A to 0A Trace 1: VDDQ, 100mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 10A/div Timebase: 40µs/div. VDDQ Load Transient Response, Continuous Conduction Mode, 0A to 10A Zoomed Trace 1: VDDQ, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 10A/div Timebase: 10µs/div. VDDQ Load Transient Response, Continuous Conduction Mode, 10A to 0A Zoomed Trace 1: VDDQ, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 10A/div Timebase: 10µs/div. Please refer to Figure 4 on Page 17 for test schematic 2006 Semtech Corp. 25 www.semtech.com SC1486A POWER MANAGEMENT Typical Characteristics (Cont.) VDDQ Load Transient Response, Power Save Mode, 0A to 10A to 0A Trace 1: VDDQ, 100mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 10A/div Timebase: 40µs/div. VDDQ Load Transient Response, Power Save Mode, 0A to 10A Zoomed Trace 1: VDDQ, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 10A/div Timebase: 10µs/div. VDDQ Load Transient Response, Power Save Mode, 10A to 0A Zoomed Trace 1: VDDQ, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 10A/div Timebase: 10µs/div. Please refer to Figure 4 on Page 17 for test schematic 2006 Semtech Corp. 26 www.semtech.com SC1486A POWER MANAGEMENT Typical Characteristics (Cont.) VTT Load Transient Response, 0A to 1.5A to 0A Trace 1: VTT, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 1A/div Timebase: 40µs/div. VTT Load Transient Response, 0A to 1.5A Zoomed Trace 1: VTT, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 1A/div Timebase: 10µs/div. VTT Load Transient Response, 1.5A to 0A Zoomed Trace 1: VTT, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 1A/div Timebase: 10µs/div. Please refer to Figure 4 on Page 17 for test schematic 2006 Semtech Corp. 27 www.semtech.com SC1486A POWER MANAGEMENT Typical Characteristics (Cont.) Startup (CCM), EN/PSV1 Going 0V to Floating Trace 1: VDDQ, 1V/div. Trace 2: VTT, 0.5V/div Trace 3: REFOUT, 0.5V/div Trace 4: En/PSV1, 2V/div. Timebase: 2ms/div. Startup (CCM) Showing PGD1 and PGD2 Trace 1: VDDQ, 1V/div. Trace 2: VTT, 0.5V/div. Trace 3: PGD1, 5V/div. Trace 4: PGD2, 5V/div Timebase: 2ms/div. Please refer to Figure 4 on Page 17 for test schematic 2006 Semtech Corp. 28 www.semtech.com SC1486A POWER MANAGEMENT Outline Drawing - TSSOP-28 A DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX D e N A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc 2X E/2 E1 E PIN 1 INDICATOR ccc C 2X N/2 TIPS 1 23 e/2 B aaa C SEATING PLANE D .047 .006 .002 .042 .031 .007 .012 .007 .003 .378 .382 .386 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 28 0° 8° .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.20 0.09 9.60 9.70 9.80 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 28 0° 8° 0.10 0.10 0.20 A2 A C bxN bbb H A1 C A-B D c GAGE PLANE 0.25 SIDE VIEW SEE DETAIL A L (L1) DETAIL 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE. 2006 Semtech Corp. 29 www.semtech.com SC1486A POWER MANAGEMENT Land Pattern - TSSOP-28 X DIM (C) G Z Y C G P X Y Z DIMENSIONS INCHES MILLIMETERS (.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2006 Semtech Corp. 30 www.semtech.com