19-0739; Rev 0; 1/07 KIT ATION EVALU E L B AVAILA Single Quick-PWM Step-Down Controller with Dynamic REFIN Ordering Information PART PKG CODE PIN-PACKAGE TOP MARK MAX8792ETD+T 14 TDFN-EP* 3mm x 3mm T1433-1 ADC Note: This device is specified over the -40°C to +80°C operating temperature range. +Denotes a lead-free package. REF REFIN ILIM FB TOP VIEW SKIP Pin Configuration VCC The controller senses the current across the synchronous rectifier to achieve a low-cost and highly efficient valley current-limit protection. The adjustable currentlimit threshold provides a high degree of flexibility, allowing thermally compensated protection using an NTC or foldback current-limit protection using a voltage-divider derived from the output. The MAX8792 includes a voltage-controlled soft-start and soft-shutdown in order to limit the input surge current, provide a monotonic power-up (even into a precharged output), and provide a predictable powerup time. The controller also includes output fault protection—undervoltage and overvoltage protection—as well as thermal-fault protection. The MAX8792 is available in a tiny 14-pin, 3mm x 3mm TDFN package. For space-constrained applications, refer to the MAX17016 single step-down with 10A, 26V internal MOSFETs available in a small 40-pin, 6mm x 6mm TQFN package. Applications . Notebook Computers PGOOD The MAX8792 pulse-width modulation (PWM) controller provides high efficiency, excellent transient response, and high DC-output accuracy needed for stepping down high-voltage batteries to generate low-voltage core or chipset/RAM bias supplies in notebook computers. The output voltage can be dynamically controlled using the dynamic REFIN, which supports input voltages between 0 to 2V. The REFIN adjustability combined with a resistive voltage-divider on the feedback input allows the MAX8792 to be configured for any output voltage between 0 to 0.9 VIN. Maxim’s proprietary Quick-PWM™ quick-response, constant-on-time PWM control scheme handles wide input/output voltage ratios (low-duty-cycle applications) with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. Strong drivers allow the MAX8792 to efficiently drive large synchronous-rectifier MOSFETs. Features o Quick-PWM with Fast Transient Response o Supports Any Output Capacitor No Compensation Required with Polymers/Tantalum Stable with Ceramic Output Capacitors Using External Compensation o Precision 2V ±10mV Reference o Dynamically Adjustable Output Voltage (0 to 0.9 VIN Range) Feedback Input Regulates to 0 to 2V REFIN Voltage 0.5% VOUT Accuracy Over Line and Load o 26V Maximum Input Voltage Rating o Adjustable Valley Current-Limit Protection Thermal Compensation with NTC Supports Foldback Current Limit o Resistively Programmable Switching Frequency o Overvoltage Protection o Undervoltage/Thermal Protection o Voltage Soft-Start and Soft-Shutdown o Monotonic Power-Up with Precharged Output o Power-Good Window Comparator 14 13 12 11 10 9 8 I/O and Chipset Supplies GPU Core Supply MAX8792 DDR Memory—VDDQ or VTT Point-of-Load Applications GND Quick-PWM is a trademark of Maxim Integrated Products, Inc. 5 6 7 DH TON 4 BST VDD 3 LX 2 DL 1 EN Step-Down Power Supply TDFN (3mm x 3mm) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8792 General Description MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN ABSOLUTE MAXIMUM RATINGS TON to GND ...........................................................-0.3V to +28V VDD to GND ..............................................................-0.3V to +6V VCC to GND ................................................-0.3V to (VDD + 0.3V) EN, SKIP, PGOOD to GND.......................................-0.3V to +6V REF, REFIN to GND ....................................-0.3V to (VCC + 0.3V) ILIM, FB to GND .........................................-0.3V to (VCC + 0.3V) DL to GND ..................................................-0.3V to (VDD + 0.3V) BST to GND .................................................(VDD - 0.3V) to +34V BST to LX..................................................................-0.3V to +6V BST to VDD .............................................................-0.3V to +28V DH to LX ....................................................-0.3V to (VBST + 0.3V) REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70°C) 14-Pin 3mm x 3mm TDFN (derated 24.4mW/°C above +70°C)....................1951mW Operating Temperature Range (extended) .........-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature.........................................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = ILIM = REF, SKIP = GND. TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 26 V PWM CONTROLLER Input Voltage Range VIN 2 Quiescent Supply Current (VDD) IDD + ICC FB forced above REFIN 0.7 1.2 mA Shutdown Supply Current (VDD) ISHDN EN = GND, TA = +25°C 0.1 2 µA VDD-to-VCC Resistance RCC On-Time tON Minimum Off-Time tOFF(MIN) TON Shutdown Supply Current REFIN Voltage Range FB Voltage Range FB Voltage Accuracy RTON = 97.5kΩ (600kHz) 118 139 160 RTON = 200kΩ (300kHz) 250 278 306 RTON = 302.5kΩ (200kHz) 354 417 480 (Note 3) 200 300 ns EN = GND, VTON = 26V, VCC = 0V or 5V, TA = +25°C 0.01 1 µA VIN = 12V, VFB = 1.0V (Note 3) ns VREFIN (Note 2) 0 VREF V VFB (Note 2) 0 VREF V VFB VREFIN = 0.5V, TA = +25°C measured at FB, VIN = 2V to 26V, TA = 0°C to +85°C SKIP = VDD VREFIN = 1.0V VREFIN = 2.0V FB Input Bias Current Ω 20 IFB 0.495 0.493 0.505 0.507 V TA = +25°C 0.995 TA = 0°C to +85°C 0.993 TA = 0°C to +85°C 1.990 VFB = 0.5V to 2.0V, TA = +25°C 0.5 1.0 1.005 2.0 2.010 1.007 -0.1 +0.1 µA Load-Regulation Error ILOAD = 0 to 3A, SKIP = VDD 0.1 % Line-Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V 0.25 % Soft-Start/-Stop Slew Rate tSS Rising/falling edge on EN 1 mV/µs Dynamic REFIN Slew Rate tDYN Rising edge on REFIN 8 mV/µs VREF VCC = 4.5V to 5.5V REFERENCE Reference Voltage 2 No load 1.990 IREF = -10µA to +50µA 1.98 2.00 _______________________________________________________________________________________ 2.010 2.02 V Single Quick-PWM Step-Down Controller with Dynamic REFIN (Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = ILIM = REF, SKIP = GND. TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 250 300 350 mV FAULT DETECTION Output Overvoltage-Protection Trip Threshold With respect to the internal target voltage (error comparator threshold); rising edge; hysteresis = 50mV OVP VREF + 0.30 Dynamic transition Minimum OVP threshold V 0.7 Output Overvoltage Fault-Propagation Delay tOVP FB forced 25mV above trip threshold Output Undervoltage-Protection Trip Threshold UVP With respect to the internal target voltage (error comparator threshold) falling edge; hysteresis = 50mV -240 -200 -160 mV Output Undervoltage Fault-Propagation Delay tUVP FB forced 25mV below trip threshold 100 200 350 µs 5 UVP falling edge, 25mV overdrive PGOOD Propagation Delay tPGOOD PGOOD Output-Low Voltage PGOOD Leakage Current IPGOOD VCC Undervoltage Lockout Threshold TSHDN VUVLO(VCC) µs 5 100 200 ISINK = 3mA Dynamic REFIN Transition Fault Blanking Threshold Thermal-Shutdown Threshold 5 OVP rising edge, 25mV overdrive Startup delay µs FB = REFIN (PGOOD high impedance), PGOOD forced to 5V, TA = +25°C 350 0.4 V 1 µA Fault blanking initiated; REFIN deviation from the internal target voltage (error comparator threshold); hysteresis = 10mV ±50 mV Hysteresis = 15°C 160 °C Rising edge, PWM disabled below this level; hysteresis = 100mV 3.95 4.2 4.45 V VREF V CURRENT LIMIT ILIM Input Range 0.4 Current-Limit Threshold VILIMIT Current-Limit Threshold (Negative) VINEG Current-Limit Threshold (Zero Crossing) VZX VILIM = 0.4V 18 20 22 ILIM = REF (2.0V) 92 100 108 VILIM = 0.4V VILIM = 0.4V, VGND - VLX, SKIP = GND or open Ultrasonic Frequency SKIP = open (3.3V); VFB = VREFIN + 50mV Ultrasonic Current-Limit Threshold SKIP = open (3.3V); VFB = VREFIN + 50mV 18 mV -24 mV 1 mV 30 kHz 35 mV _______________________________________________________________________________________ 3 MAX8792 ELECTRICAL CHARACTERISTICS (continued) MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = ILIM = REF, SKIP = GND. TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low state (pulldown) 1.2 3.5 High state (pullup) 1.2 3.5 High state (pullup) 1.7 4 Low state (pulldown) 0.9 2 DH forced to 2.5V, BST - LX forced to 5V 1.5 A 1 A 2.4 A GATE DRIVERS DH Gate Driver On-Resistance RON(DH) DL Gate Driver On-Resistance RON(DL) DH Gate Driver Source/ Sink Current DL Gate Driver Source Current DL Gate Driver Sink Current IDH BST - LX forced to 5V IDL(SOURCE) DL forced to 2.5V IDL(SINK) Driver Propagation Delay DL Transition Time DL forced to 2.5V DH low to DL high 10 25 DL low to DH high 15 35 DL falling, CDL = 3nF 20 DL rising, CDL = 3nF 20 Ω Ω ns ns DH falling, CDH = 3nF 20 DH rising, CDH = 3nF 20 RBST IBST = 10mA, VDD = 5V 4 7 Ω EN Logic-Input Threshold VEN EN rising edge, hysteresis = 450mV (typ) 1.7 2.20 V EN Logic-Input Current IEN EN forced to GND or VDD, TA = +25°C +0.5 µA V DH Transition Time Internal BST Switch On-Resistance ns INPUTS AND OUTPUTS VSKIP SKIP Logic-Input Current ISKIP -0.5 VCC 0.4 High (5V VDD) SKIP Quad-Level Input Logic Levels 1.20 Mid (3.3V) 3.0 3.6 Ref (2.0V) 1.7 2.3 Low (GND) 0.4 SKIP forced to GND to VDD -2 +2 µA ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = ILIM = REF, SKIP = GND. TA = -40°C to +85°C, unless otherwise specified.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS PWM CONTROLLER Input Voltage Range Quiescent Supply Current (VDD) On-Time 4 VIN IDD + ICC tON 2 FB forced above REFIN VIN = 12V VFB = 1.0V (Note 3) 26 V 1.2 mA RTON = 97.5kΩ (600kHz) 115 163 RTON = 200kΩ (300kHz) 250 306 RTON = 302.5kΩ (200kHz) 348 486 _______________________________________________________________________________________ ns Single Quick-PWM Step-Down Controller with Dynamic REFIN (Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = ILIM = REF, SKIP = GND. TA = -40°C to +85°C, unless otherwise specified.) (Note 1) PARAMETER Minimum Off-Time REFIN Voltage Range FB Voltage Range SYMBOL CONDITIONS tOFF(MIN) (Note 3) VREFIN (Note 2) VFB (Note 2) VREFIN = 0.5V MIN MAX UNITS 350 ns 0 VREF V V 0 VREF 0.49 0.51 Measured at FB, VIN = 2V to 26V, VREFIN = 1.0V SKIP = VDD VREFIN = 2.0V 0.99 1.01 1.985 2.015 VREF VDD = 4.5V to 5.5V 1.985 2.015 V Output Overvoltage-Protection Trip Threshold OVP With respect to the internal target voltage (error comparator threshold) rising edge; hysteresis = 50mV 250 350 mV Output Undervoltage-Protection Trip Threshold UVP With respect to the internal target voltage (error comparator threshold); falling edge; hysteresis = 50mV -240 -160 mV Output Undervoltage Fault-Propagation Delay tUVP FB forced 25mV below trip threshold 80 400 µs 0.4 V 3.95 4.45 V V FB Voltage Accuracy VFB V REFERENCE Reference Voltage FAULT DETECTION PGOOD Output Low Voltage VCC Undervoltage Lockout Threshold ISINK = 3mA VUVLO(VCC) Rising edge, PWM disabled below this level, hysteresis = 100mV CURRENT LIMIT ILIM Input Range Current-Limit Threshold VILIMIT Ultrasonic Frequency 0.4 VREF VILIM = 0.4V 17 23 ILIM = REF (2.0V) 90 110 SKIP = open (3.3V), VFB = VREFIN + 50mV 17 mV kHz GATE DRIVERS DH Gate Driver On-Resistance RON(DH) DL Gate Driver On-Resistance RON(DL) Internal BST Switch On-Resistance RBST BST - LX forced Low state (pulldown) to 5V High state (pullup) 3.5 3.5 High state (pullup) 4 Low state (pulldown) 2 IBST = 10mA, VDD = 5V 7 Ω Ω Ω _______________________________________________________________________________________ 5 MAX8792 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = ILIM = REF, SKIP = GND. TA = -40°C to +85°C, unless otherwise specified.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS EN rising edge hysteresis = 450mV (typ) 1.20 2.20 V High (5V VDD) VCC 0.4 V INPUTS AND OUTPUTS EN Logic-Input Threshold VEN SKIP Quad-Level Input Logic Levels VSKIP Mid (3.3V) 3.0 3.6 Ref (2.0V) 1.7 2.3 Low (GND) 0.4 Note 1: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by design and characterization. Note 2: The 0 to 0.5V range is guaranteed by design, not production tested. Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times can differ due to MOSFET switching speeds. Typical Operating Characteristics (MAX8792 Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, RTON = 200kΩ, TA = +25°C, unless otherwise noted.) 70 20V 60 50 40 80 70 60 PWM MODE 50 LOW-NOISE MODE 40 30 0.1 1 LOAD CURRENT (A) LOW-NOISE MODE 1.52 SKIP MODE 1.50 PWM MODE 1.48 20 0.01 1.54 30 SKIP MODE PWM MODE 20 6 90 EFFICIENCY (%) 12V SKIP MODE OUTPUT VOLTAGE (V) 90 100 MAX8792 toc02 7V MAX8792 toc01 100 80 1.5V OUTPUT VOLTAGE vs. LOAD CURRENT 1.5V OUTPUT EFFICIENCY vs. LOAD CURRENT MAX8792 toc03 1.5V OUTPUT EFFICIENCY vs. LOAD CURRENT EFFICIENCY (%) MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN 10 0.01 0.1 1 LOAD CURRENT (A) 10 0 2 4 6 LOAD CURRENT (A) _______________________________________________________________________________________ 8 10 Single Quick-PWM Step-Down Controller with Dynamic REFIN 90 70 20V 12V 60 50 40 30 60 PWM MODE 50 0.1 1 10 1.03 0.01 0.1 1 4 6 8 10 SWITCHING FREQUENCY vs. LOAD CURRENT PWM MODE SWITCHING FREQUENCY vs. INPUT VOLTAGE SWITCHING FREQUENCY vs. TEMPERATURE 100 LOW-NOISE MODE ILOAD = 5A 310 300 290 280 NO LOAD 270 260 300 ILOAD = 10A 290 280 ILOAD = 5A 250 SKIP MODE 270 240 0 0.1 MAX8792 toc09 MAX8792 toc08 320 SWITCHING FREQUENCY (kHz) 150 330 SWITCHING FREQUENCY (kHz) MAX8792 toc07 200 1 6 10 10 14 -40 22 18 -20 0 20 40 60 80 100 LOAD CURRENT (A) INPUT VOLTAGE (V) TEMPERATURE (°C) MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE MAXIMUM OUTPUT CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT IBIAS vs. INPUT VOLTAGE 13.3 13.2 13.1 13.0 18 12 16 15 WITH TEMPERATURE COMPENSATION (FIGURE 1) 14 13 12 15 18 INPUT VOLTAGE (V) 21 24 10 8 6 LOW-NOISE MODE 4 12 2 10 9 PWM MODE 14 17 11 12.9 16 MAX17016 toc12 WITHOUT TEMPERATURE COMPENSATION R4 = R5 = 49.9kΩ IBIAS (mA) 13.4 19 MAX17016 toc11 13.5 20 SWITCHING FREQUENCY (kHz) MAX17016 toc10 13.6 6 2 0 10 LOAD CURRENT (A) 250 0.01 SKIP MODE LOAD CURRENT (A) PWM MODE 50 1.05 LOAD CURRENT (A) 350 300 LOW-NOISE MODE PWM MODE 20 0.01 1.06 1.04 LOW-NOISE MODE 30 SKIP MODE PWM MODE 20 SWITCHING FREQUENCY (kHz) 70 40 1.07 OUTPUT VOLTAGE (V) 80 EFFICIENCY (%) EFFICIENCY (%) 80 MAXIMUM OUTPUT CURRENT (A) SKIP MODE MAX8792 toc06 7V 90 100 MAX8792 toc04 100 1.05V OUTPUT VOLTAGE vs. LOAD CURRENT 1.05V OUTPUT EFFICIENCY vs. LOAD CURRENT MAX8792 toc05 1.05V OUTPUT EFFICIENCY vs. LOAD CURRENT SKIP MODE 0 -40 -20 0 20 40 60 LOAD CURRENT (A) 80 100 6 9 12 15 18 21 24 INPUT VOLTAGE (V) _______________________________________________________________________________________ 7 MAX8792 Typical Operating Characteristics (continued) (MAX8792 Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, RTON = 200kΩ, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (MAX8792 Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, RTON = 200kΩ, TA = +25°C, unless otherwise noted.) REF OUTPUT VOLTAGE vs. LOAD CURRENT PWM MODE 1 LOW-NOISE MODE 0.1 2.01 2.00 1.99 INPUT VOLTAGE (V) LOAD CURRENT (μA) OFFSET VOLTAGE (mV) SOFT-START WAVEFORM (HEAVY LOAD) SOFT-START WAVEFORM (LIGHT LOAD) MAX17016 toc16 +25°C 5V A B 0 A B 0 1.5V 1.5V 20 5V 0 5V 0 5V 30 2.5 MAX17016 toc18 MAX17016 toc17 SAMPLE SIZE = 100 2.0 1.5 1.0 0 0.5 0 -10 0 10 20 30 40 50 60 70 80 90 100 110 24 -0.5 21 -1.0 18 20V ILIM THRESHOLD VOLTAGE DISTRIBUTION +85°C C C 0 8A 0 D A. SHDN, 5V/div B. PWRGD, 5V/div ILIM THRESHOLD VOLTAGE (mV) 0 200μs/div C. VOUT, 1V/div B. INDUCTOR CURRENT, 10A/div A. SHDN, 5V/div B. PWRGD, 5V/div 200μs/div C. VOUT, 1V/div B. INDUCTOR CURRENT, 10A/div LOAD-TRANSIENT RESPONSE (SKIP MODE) LOAD-TRANSIENT RESPONSE (PWM MODE) SHUTDOWN WAVEFORM D 0 22.0 21.6 21.2 20.8 20.4 20.0 19.6 19.2 18.8 18.4 18.0 10 0 20 -1.5 15 50 40 30 -2.0 1.98 12 40 +25°C -2.5 0.01 9 SAMPLE SIZE = 100 +85°C 10 SKIP MODE 6 50 MAX17016 toc15 10 MAX17016 toc14 MAX17016 toc13 2.02 OUTPUT VOLTAGE (V) IIN (mA) 100 REFIN-TO-FB OFFSET VOLTAGE DISTRIBUTION SAMPLE PERCENTAGE (%) NO-LOAD SUPPLY CURRENT IIN vs. INPUT VOLTAGE SAMPLE PERCENTAGE (%) MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX17016 toc21 MAX17016 toc20 MAX17016 toc19 5V A 0 5V 8A 1A A 8A A 1A B 0 5V 1.55V 1.55V C 0 1.5V D 0 B B 1.45V 1.45V 8A 10A C C 0 E A. SHDN, 5V/div B. PWRGD, 5V/div C. DL, 5V/div 8 200μs/div D. VOUT, 1V/div E. INDUCTOR CURRENT, 5A/div 1A 0A 20μs/div A. IOUT = 1A TO 8A, 10A/div C. INDUCTOR CURRENT, B. VOUT, 50mV/div 10A/div 20μs/div A. IOUT = 1A TO 8A, 10A/div C. INDUCTOR CURRENT, B. VOUT, 50mV/div 10A/div _______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN OUTPUT OVERLOAD WAVEFORM (UVP ENABLED) OUTPUT OVERVOLTAGE WAVEFORM MAX17016 toc23 MAX17016 toc22 14A 1.5V A A 0 0 1.5V B 0 5V 5V B 0 C 0 5V 5V C D 0 0 100μs/div 200μs/div A. INDUCTOR CURRENT, C. DL, 5V/div 10A/div D. PWRGD, 5V/div B. VOUT, 1V/div A. VOUT, 1V/div B. DL, 5V/div DYNAMIC OUTPUT-VOLTAGE TRANSITION (PWM MODE) DYNAMIC OUTPUT-VOLTAGE TRANSITION (SKIP MODE) MAX17016 toc24 1.5V C. PWRGD, 5V/div MAX17016 toc25 A 1.05V 1.5V 1.5V A 1.05V 1.5V B 1.05V B 1.05V 10A 0 C C 0 -10A 12V D 0 12V D 0 20μs/div A. REFIN, 500mV/div B. VOUT, 200mV/div C. INDUCTOR CURRENT, 10A/div D. LX, 10V/div 100μs/div A. REFIN, 500mV/div C. INDUCTOR CURRENT, B. VOUT, 200mV/div 10A/div D. LX, 10V/div _______________________________________________________________________________________ 9 MAX8792 Typical Operating Characteristics (continued) (MAX8792 Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, RTON = 200kΩ, TA = +25°C, unless otherwise noted.) Single Quick-PWM Step-Down Controller with Dynamic REFIN MAX8792 Pin Description PIN NAME FUNCTION 1 EN Shutdown Control Input. Connect to VDD for normal operation. Pull EN low to place the controller into its 2µA shutdown state. When disabled, the MAX8792 slowly ramps down the target/output voltage to ground and after the target voltage reaches 0.1V, the controller forces both DH and DL low and enters the low-power shutdown state. Toggle EN to clear the fault-protection latch. 2 VDD Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1µF or greater ceramic capacitor. 3 DL Low-Side Gate Driver. DL swings from GND to VDD. The controller pulls DL high when an output overvoltage fault is detected, overriding any negative current-limit condition that may be present. The MAX8792 forces DL low during VCC UVLO and REFOK lockout conditions. 4 LX Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1. 5 DH High-Side Gate Driver. DH swings from LX to BST. The MAX8792 pulls DH low whenever the controller is disabled. 6 BST Boost Flying-Capacitor Connection. Connect to an external 0.1µF 6V capacitor as shown in Figure 1. The MAX8792 contains an internal boost switch/diode (see Figure 2). Switching Frequency-Setting Input. An external resistor between the input power source and TON sets the switching period (TSW = 1 / fSW) according to the following equation: 7 TON ⎛ V ⎞ TSW = CTON (RTON + 6.5kΩ)⎜ FB ⎟ ⎝ VOUT ⎠ where CTON = 16.26pF and VFB = VREFIN under normal operating conditions. If the TON current drops below 10µA, the MAX8792 shuts down, and enters a high-impedance state. TON is high impedance in shutdown. 10 8 FB 9 ILIM Feedback Voltage-Sense Connection. Connect directly to the positive terminal of the output capacitors for output voltages less than 2V as shown in Figure 1. For fixed-output voltages greater than 2V, connect REFIN to REF and use a resistive divider to set the output voltage (Figure 4). FB senses the output voltage to determine the on-time for the high-side switching MOSFET. Current-Limit Threshold Adjustment. The current-limit threshold is 0.05 times (1/20) the voltage at ILIM. Connect ILIM to a resistive divider (from REF) to set the current-limit threshold between 20mV and 100mV (with 0.4V to 2V at ILIM). External Reference Input. REFIN sets the feedback regulation voltage (VFB = VREFIN) of the MAX8792 using the resistor-divider connected between REF and GND. The MAX8792 includes an internal window comparator to detect REFIN voltage transitions, allowing the controller to blank PGOOD and the fault protection. 10 REFIN 11 REF 2V Reference Voltage. Bypass to analog ground using a 470pF to 10nF ceramic capacitor. The reference can source up to 50µA for external loads. 12 SKIP Pulse-Skipping Control Input. This four-level input determines the mode of operation under normal steady-state conditions and dynamic output-voltage transitions. VDD (5V) = forced-PWM operation. REF (2V) = pulse-skipping mode with forced-PWM during transitions. Open (3.3V)= ultrasonic mode (without forced-PWM during transitions). GND = pulse-skipping mode (without forced-PWM during transitions). 13 VCC 5V Analog Supply Voltage. Internally connected to VDD through an internal 20Ω resistor. Bypass VCC to analog ground using a 1µF ceramic capacitor. ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN PIN NAME FUNCTION 14 PGOOD Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 200mV (typ) below or 300mV (typ) above the target voltage (VREFIN), during soft-start and soft-shutdown. After the soft-start circuit has terminated, PGOOD becomes high impedance if the output is in regulation. PGOOD is blanked—forced high-impedance state—when a dynamic REFIN transition is detected. EP (15) GND Ground/Exposed Pad. Internally connected to the controller’s ground plane and substrate. Connect directly to ground. 2 5V BIAS SUPPLY C1 1μF C2 1μF PWR DH R10 100kΩ 1 OFF 12 GND/OPEN/REF/VCC C3 1000pF AGND 11 AGND LO DL R2 54.9kΩ RTON 200kΩ INPUT 7V TO 24V CIN 6 5 PWR CBST 0.1μF L1 4 3 OUTPUT 1.05V/1.50V 10A (MAX) COUT PGOOD PWR PWR EN MAX8792 FB SKIP 8 NTC 100kΩ B = 4250 REF R1 49.9kΩ 10 R3 97.6kΩ VCC LX 14 ON TON BST 13 AGND VDD 7 REFIN ILIM GND (EP) AGND PWR HI 9 R4 68kΩ REF R5 82kΩ AGND AGND SEE TABLE 1 FOR COMPONENT SELECTION. Figure 1. MAX8792 Standard Application Circuit Standard Application Circuits The MAX8792 standard application circuit (Figure 1) generates a 1.5V or 1.05V output rail for general-purpose use in a notebook computer. See Table 1 for component selections. Table 2 lists the component manufacturers. ______________________________________________________________________________________ 11 MAX8792 Pin Description (continued) MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN Table 1. Component Selection for Standard Applications VOUT = 1.5V/1.05V AT 10A (Figure 1) VOUT = 3.3V AT 6A (Figure 4) VOUT = 1.5V/1.05V AT 10A (Figure 7) VIN = 7V to 20V TON = 200kΩ (300kHz) VIN = 7V to 20V TON = 332kΩ (300kHz) VIN = 4V to 12V TON = 100kΩ (600kHz) Input Capacitor (2x) 10µF, 25V Taiyo Yuden TMK432BJ106KM (2x) 10µF, 25V Taiyo Yuden TMK432BJ106KM (2x) 10µF 25V Taiyo Yuden TMK432BJ106KM Output Capacitor (2x) 330µF, 6mΩ Panasonic EEFSX0D331XR (1x) 330µF, 18mΩ Sanyo 4TPE330MI (2x) 330µF, 7mΩ Nec-Tokin PSGD0E337M7 Inductor 1.0µH, 3.25mΩ Wurth 744 3552 100 3.3µH, 14mΩ NEC-Tokin MPLC1040L3R3 0.68µH, 4.6mΩ Coiltronics FP3-R68 High-Side MOSFET Fairchild (1x) FDS8690 8.6mΩ/11.4mΩ (typ/max) Low-Side MOSFET Fairchild (1x) FDS8670 4.2mΩ/5.0mΩ (typ/max) COMPONENT Siliconix (1x) Si4916DY NH = 18mΩ/22mΩ (typ/max) NL = 15mΩ/18mΩ (typ/max) Fairchild (1x) FDS8690 8.6mΩ/11.4mΩ (typ/max) Fairchild (1x) FDS8670 4.2mΩ/5.0mΩ (typ/max) Table 2. Component Suppliers MANUFACTURER WEBSITE MANUFACTURER WEBSITE AVX www.avxcorp.com Panasonic www.panasonic.com BI Technologies www.bitechnologies.com Pulse www.pulseeng.com Renesas www.renesas.com Sanyo www.secc.co.jp Siliconix (Vishay) www.vishay.com Central Semiconductor www.centralsemi.com Coiltronics www.cooperet.com Sumida www.sumida.com Taiyo Yuden www.t-yuden.com Fairchild Semiconductor www.fairchildsemi.com International Rectifier www.irf.com TDK www.component.tdk.com Kemet www.kemet.com TOKO www.tokoam.com NEC Tokin www.nec-tokin.com Wurth www.we-online.com Detailed Description The MAX8792 step-down controller is ideal for the lowduty-cycle (high-input voltage to low-output voltage) applications required by notebook computers. Maxim’s proprietary Quick-PWM pulse-width modulator in the MAX8792 is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency, current-mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time (regardless of input voltage) PFM control schemes. 12 +5V Bias Supply (VCC/VDD) The MAX8792 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook’s main 95% efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator such as the MAX1615. The 5V bias supply powers both the PWM controller and internal gate-drive power, so the maximum current drawn is determined by: IBIAS = IQ + fSWQG = 2mA to 20mA (typ) ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN relies on the output filter capacitor’s ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode regulator with voltage feed-forward (Figure 2). This architecture TON ON-TIME COMPUTE tON TRIG tOFF(MIN) IN FB BST TRIG Q ONE-SHOT S Q DH Q R LX ONE-SHOT INTEGRATOR (CCV) ERROR AMPLIFIER VDD DL S Q R GND FB QUADLEVEL DECODE SKIP FAULT BLANK EA + 0.3V ZERO CROSSING PGOOD AND FAULT PROTECTION VALLEY CURRENT LIMIT ILIM REF EA - 0.2V EN SOFTSTART/STOP PGOOD 2V REF VCC REFIN EA BLANK MAX8792 DYNAMIC OUTPUT TRANSITION DETECTION Figure 2. MAX8792 Functional Block Diagram ______________________________________________________________________________________ 13 MAX8792 Free-Running Constant-On-Time PWM Controller with Input Feed-Forward MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (200ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. On-Time One-Shot The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to input and output voltage. The high-side switch on-time is inversely proportional to the input voltage as sensed by the TON input, and proportional to the feedback voltage as sensed by the FB input: On-Time (tON) = TSW (VFB / VIN) where TSW (switching period) is set by the resistance (RTON) between TON and VIN. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. Connect a resistor (RTON) between TON and VIN to set the switching period TSW = 1 / fSW: ⎛ V ⎞ TSW = CTON (RTON + 6.5kΩ)⎜ FB ⎟ ⎝ VOUT ⎠ where CTON = 16.26pF. When used with unity-gain feedback (VOUT = VFB), a 96.75kΩ to 303.25kΩ corresponds to switching periods of 167ns (600kHz) to 500ns (200kHz), respectively. High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space. For continuous conduction operation, the actual switching frequency can be estimated by: fSW = VFB + VDROP1 t ON (VIN + VDROP2 ) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board (PCB) resistances; VDROP2 is the sum of the resistances in the charging path, including the high-side switch, inductor, and PCB resistances; and tON is the on-time calculated by the MAX8792. 14 Power-Up Sequence (POR, UVLO) The MAX8792 is enabled when EN is driven high and the 5V bias supply (V DD) is present. The reference powers up first. Once the reference exceeds its UVLO threshold, the internal analog blocks are turned on and masked by a 50µs one-shot delay in order to allow the bias circuitry and analog blocks enough time to settle to their proper states. With the control circuitry reliably powered up, the PWM controller may begin switching. Power-on reset (POR) occurs when VCC rises above approximately 3V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, VCC exceeds 4.25V, and EN is driven high. With the reference in regulation, the controller ramps the output voltage to the target REFIN voltage with a 1mV/µs slew rate: t START = VFB V = FB 1mV / μs 1V / ms The soft-start circuitry does not use a variable current limit, so full output current is available immediately. PGOOD becomes high impedance approximately 200µs after the target REFIN voltage has been reached. The MAX8792 automatically uses pulse-skipping mode during soft-start and uses forced-PWM mode during soft-shutdown, regardless of the SKIP configuration. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling EN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output (DL and DH pulled low). Shutdown When the system pulls EN low, the MAX8792 enters low-power shutdown mode. PGOOD is pulled low immediately, and the output voltage ramps down with a 1mV/µs slew rate: t SHDN = VFB V = FB 1mV / μs 1V / ms ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN Modes of Operation Forced-PWM Mode (SKIP = VDD) The low-noise, forced-PWM mode (SKIP = VDD) disables the zero-crossing comparator, which controls the low-side switch on-time. This forces the low-side gatedrive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while DH maintains a duty factor of VOUT/VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 10mA to 50mA, depending on the switching frequency. The MAX8792 automatically always uses forced-PWM operation during shutdown, regardless of the SKIP configuration. Automatic Pulse-Skipping Mode (SKIP = GND or 3.3V) In skip mode (SKIP = GND or 3.3V), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator threshold is set by the differential across LX to GND. DC output-accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX8792 regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction (SKIP = GND and IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. When SKIP is pulled to GND, the MAX8792 remains in pulse-skipping mode. Since the output is not able to sink current, the timing for negative dynamic output-voltage transitions depends on the load current and output capacitance. Letting the output voltage drift down is typically recommended in order to reduce the potential for audible noise since this eliminates the input current surge during negative output-voltage transitions. Ultrasonic Mode (SKIP = Open = 3.3V) Leaving SKIP unconnected activates a unique pulseskipping mode with a minimum switching frequency of 18kHz. This ultrasonic pulse-skipping mode eliminates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. In ultrasonic mode, the controller automatically transitions to fixed-frequency PWM operation when the load reaches the same critical conduction point (ILOAD(SKIP)) that occurs when normally pulse skipping. An ultrasonic pulse occurs when the controller detects that no switching has occurred within the last 33µs. Once triggered, the ultrasonic controller pulls DL high, turning on the low-side MOSFET to induce a negative inductor current (Figure 3). After the inductor current reaches the negative ultrasonic current threshold, the controller turns off the low-side MOSFET (DL pulled low) 33μs (typ) INDUCTOR CURRENT ZERO-CROSSING DETECTION 0 ISONIC ON-TIME (tON) Figure 3. Ultrasonic Waveform ______________________________________________________________________________________ 15 MAX8792 Slowly discharging the output capacitors by slewing the output over a long period of time (typically 0.5ms to 2ms) keeps the average negative inductor current low (damped response), thereby preventing the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. After the controller reaches the zero target, the MAX8792 shuts down completely—the drivers are disabled (DL and DH pulled low)—the reference turns off, and the supply currents drop to about 0.1µA (typ). When a fault condition—output UVP or thermal shutdown—activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle EN or cycle VCC power below 0.5V. The MAX8792 automatically uses pulse-skipping mode during soft-start and uses forced-PWM mode during soft-shutdown, regardless of the SKIP configuration. MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN and triggers a constant on-time (DH driven high). When the on-time has expired, the controller reenables the low-side MOSFET until the controller detects that the inductor current dropped below the zero-crossing threshold. Starting with a DL pulse greatly reduces the peak output voltage when compared to starting with a DH pulse. The output voltage at the beginning of the ultrasonic pulse determines the negative ultrasonic current threshold, resulting in the following equation: VISONIC = ILRCS = (VREFIN − VFB ) × 0.7 where VFB > VREFIN and RCS is the current-sense resistance seen across GND to LX. Valley Current-Limit Protection The current-limit circuit employs a unique “valley” current-sensing algorithm that senses the inductor current through the low-side MOSFET. If the current through the low-side MOSFET exceeds the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle. The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value and input voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. In forced-PWM mode, the MAX8792 also implements a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit. 16 Integrated Output Voltage The MAX8792 regulates the valley of the output ripple, so the actual DC output voltage is higher than the slope-compensated target by 50% of the output ripple voltage. Under steady-state conditions, the MAX8792’s internal integrator corrects for this 50% output ripplevoltage error, resulting in an output voltage that is accurately defined by the following equation: ⎛V ⎞ VFB = VREFIN + ⎜ RIPPLE ⎟ ⎝ A CCV ⎠ where VREFIN is the nominal feedback voltage, ACCV is the integrator’s gain, and VRIPPLE is the feedback ripple voltage (VRIPPLE = ESR x ΔIINDUCTOR as described in the Output Capacitor Selection section). Therefore, the feedback-voltage accuracy specification provided in the Electrical Characteristics table actually refers to the integrated feedback threshold and primarily reflects the offset voltage of the integrator amplifier. Dynamic Output Voltages The MAX8792 regulates OUT to the voltage set at REFIN. By changing the voltage at REFIN (Figure 1), the MAX8792 can be used in applications that require dynamic output-voltage changes between two set points. For a step-voltage change at REFIN, the rate of change of the output voltage is limited either by the internal 8mV/µs slew-rate circuit or by the component selection—inductor current ramp, the total output capacitance, the current limit, and the load during the transition—whichever is slower. The total output capacitance determines how much current is needed to change the output voltage, while the inductor limits the current ramp rate. Additional load current slows down the output voltage change during a positive REFIN voltage change, and speeds up the output voltage change during a negative REFIN voltage change. ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN C1 1μF C2 1μF PWR DH VCC LX R10 100kΩ 14 ON TON BST 13 AGND VDD 1 OFF 12 GND/OPEN/REF/VCC C3 1000pF DL 7 INPUT 7V TO 24V CIN 6 5 PWR CBST 0.1μF L1 4 3 OUTPUT 3.3V 5A (MAX) PWR PWR EN FB SKIP 8 R7 20.0kΩ REF AGND R4 0Ω AGND 10 COUT R6 13.0kΩ PGOOD MAX8792 11 MAX8792 2 5V BIAS SUPPLY RTON 332kΩ REFIN ILIM GND (EP) AGND PWR 9 REF R5 OPEN AGND SEE TABLE 1 FOR COMPONENT SELECTION. Figure 4. High Output-Voltage Application Using a Feedback Divider Output Voltages Greater than 2V Although REFIN is limited to a 0 to 2V range, the output-voltage range is unlimited since the MAX8792 utilizes a high-impedance feedback input (FB). By adding a resistive voltage-divider from the output to FB to analog ground (Figure 4), the MAX8792 supports output voltages above 2V. However, the controller also uses FB to determine the on-time, so the voltage-divider influences the actual switching frequency, as detailed in the On-Time One-Shot section. Internal Integration An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This internal amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 2), allowing accurate DC output-voltage regulation regardless of the compensated feedback ripple voltage and internal slope-compensation variation. The integrator amplifier has the ability to shift the output voltage by ±55mV (typ). The MAX8792 disables the integrator by connecting the amplifier inputs together at the beginning of all downward REFIN transitions done in pulse-skipping mode. The integrator remains disabled until 20µs after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). Power-Good Outputs (PGOOD) and Fault Protection PGOOD is the open-drain output that continuously monitors the output voltage for undervoltage and overvoltage conditions. PGOOD is actively held low in shutdown (EN = GND), during soft-start, and soft-shutdown. Approximately 200µs (typ) after the soft-start terminates, PGOOD becomes high impedance as long as the feedback voltage is above the UVP threshold (REFIN - 200mV) and below the OVP threshold (REFIN + 300mV). PGOOD goes low if the feedback voltage drops 200mV below the target voltage (REFIN) or rises 300mV above the target voltage (REFIN), or the SMPS controller is shut down. For a logic-level PGOOD output ______________________________________________________________________________________ 17 MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN TARGET + 300mV TARGET - 200mV POWER-GOOD AND FAULT PROTECTION FB EN OVP SOFT-START COMPLETE UVP OVP ENABLED ONESHOT 200μs FAULT LATCH FAULT POWER-GOOD IN OUT CLK Figure 5. Power-Good and Fault Protection voltage, connect an external pullup resistor between PGOOD and VDD. A 100kΩ pullup resistor works well in most applications. Figure 5 shows the power-good and fault-protection circuitry. Overvoltage Protection (OVP) When the internal feedback voltage rises 300mV above the target voltage and OVP is enabled, the OVP comparator immediately pulls DH low and forces DL high, pulls PGOOD low, sets the fault latch, and disables the SMPS controller. Toggle EN or cycle VCC power below the VCC POR to clear the fault latch and restart the controller. Undervoltage Protection (UVP) When the feedback voltage drops 200mV below the target voltage (REFIN), the controller immediately pulls PGOOD low and triggers a 200µs one-shot timer. If the feedback voltage remains below the undervoltage fault threshold for the entire 200µs, then the undervoltage fault latch is set and the SMPS begins the shutdown sequence. When the internal target voltage drops below 0.1V, the MAX8792 forces DL low. Toggle EN or cycle VCC power below VCC POR to clear the fault latch and restart the controller. 18 Thermal-Fault Protection (TSHDN) The MAX8792 features a thermal fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor activates the fault latch, pulls PGOOD low, and shuts down the controller. Both DL and DH are pulled low. Toggle EN or cycle VCC power below VCC POR to reactivate the controller after the junction temperature cools by 15°C. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate driver (DH) sources and sinks 1.5A, and the low-side gate driver (DL) sources 1.0A and sinks 2.4A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET driver is powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier driver is powered directly by the 5V bias supply (VDD). ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN BST Alternatively, shoot-through currents can be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5Ω in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 6). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise. (RBST)* INPUT (VIN) CBST DH NH L LX VDD CBYP DL NL (CNL)* PGND (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS. Figure 6. Gate Drive Circuit ⎛C ⎞ VGS(TH) > VIN ⎜ RSS ⎟ ⎝ CISS ⎠ Typically, adding a 4700pF between DL and power ground (C NL in Figure 6), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. MAX8792 Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX8792 interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL low is robust, with a 0.9Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high-input voltages and long inductive driver traces may require rising LX edges do not pull up the low-side MOSFETs’ gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: Quick-PWM Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case input supply voltage allowed by the notebook’s AC adapter voltage. The minimum value (V IN(MIN) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Maximum load current: There are two values to consider. The peak load current (I LOAD(MAX) ) determines the instantaneous component stresses and filtering requirements, and thus drives output ______________________________________________________________________________________ 19 MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Most notebook loads generally exhibit ILOAD = ILOAD(MAX) x 80%. • • Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. Inductor Selection The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: ⎛ ⎞ ⎛ VOUT ⎞ VIN − VOUT L=⎜ ⎟ ⎜⎝ V ⎟⎠ f I LIR ⎝ SW LOAD(MAX) ⎠ IN Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + ΔIL 2 Transient Response The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, 20 which can be calculated from the on-time and minimum off-time. The worst-case output sag voltage can be determined by: VSAG = ⎤ T ⎞ 2 ⎡⎛ V L( ΔILOAD(MAX) ) ⎢⎜ OUT SW ⎟ + t OFF(MIN) ⎥ ⎠ VIN ⎣⎝ ⎦ ⎡⎛ (VIN − VOUT )TSW ⎞ ⎤ ⎥ − t 2COUT VOUT ⎢⎜ ( ) OFF MIN ⎟ VIN ⎢⎣⎝ ⎥⎦ ⎠ where tOFF(MIN) is the minimum off-time (see the Electrical Characteristics table). The amount of overshoot due to stored inductor energy when the load is removed can be calculated as: VSOAR ≈ (ΔILOAD(MAX) )2L 2COUT VOUT Setting the Valley Current Limit The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the inductor ripple current (ΔIL); therefore: ILIMIT(LOW) > ILOAD(MAX) − ΔIL 2 where I LIMIT(LOW) equals the minimum current-limit threshold voltage divided by the low-side MOSFETs onreistance (RDS(ON)). The valley current-limit threshold is precisely 1/20 the voltage seen at ILIM. Connect a resistive divider from REF to ILIM to analog ground (GND) in order to set a fixed valley current-limit threshold. The external 400mV to 2V adjustment range corresponds to a 20mV to 100mV valley current-limit threshold. When adjusting the currentlimit threshold, use 1% tolerance resistors and a divider current of approximately 5µA to 10µA to prevent significant inaccuracy in the valley current-limit tolerance. The MAX8792 uses the low-side MOSFET’s on-resistance as the current-sense element (R SENSE = RDS(ON)). Therefore, special attention must be made to the tolerance and thermal variation of the on-resistance. Use the worst-case maximum value for RDS(ON) from the MOSFET data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each °C of temperature rise, which must be included in the design margin unless the design includes an NTC thermistor in the ILIM resistive voltage-divider to thermally compensate the current-limit threshold. ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN In core and chipset converters and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: (RESR + RPCB ) ≤ ΔI LOAD(MAX) In low-power applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. The maximum ESR to meet ripple requirements is: ⎡ ⎤ VIN fSW L RESR ≤ ⎢ ⎥VRIPPLE ⎢⎣ (VIN − VOUT )VOUT ⎥⎦ Output Capacitor Selection The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements. Additionally, the ESR impacts stability requirements. Capacitors with a high ESR value (polymers/tantalums) will not need additional external compensation components. 2 5V BIAS SUPPLY C1 1μF C2 1μF PWR DH R10 100kΩ 1 OFF 12 GND/OPEN/REF/VCC C3 1000pF AGND 11 AGND LO DL where fSW is the switching frequency. 7 R2 54.9kΩ RTON 100kΩ INPUT 4V TO 12V CIN 6 5 PWR CBST 0.1μF L1 4 3 OUTPUT 1.50V 10A 1.05V 7A COUT PGOOD PWR PWR EN MAX8792 FB SKIP 8 REF R8 100kΩ R1 49.9kΩ 10 R3 97.6kΩ VCC LX 14 ON TON BST 13 AGND VDD VSTEP REFIN ILIM GND (EP) AGND PWR 9 R4 100kΩ REF R5 100kΩ HI AGND AGND SEE TABLE 1 FOR COMPONENT SELECTION. Figure 7. Standard Application with Foldback Current-Limit Protection ______________________________________________________________________________________ 21 MAX8792 Foldback Current Limit Including an additional resistor between ILIM and the output automatically creates a current-limit threshold that folds back as the output voltage drops (see Figure 7). The foldback current limit helps limit the inductor current under fault conditions, but must be carefully designed in order to provide reliable performance under normal conditions. The current-limit threshold must not be set too low, or the controller will not reliably power up. To ensure the controller powers up properly, the minimum current-limit threshold (when VOUT = 0V) must always be greater than the maximum load during startup (which at least consists of leakage currents), plus the maximum current required to charge the output capacitors: ISTART = COUT x 1mV/µs + ILOAD(START) MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN With most chemistries (polymer, tantalum, aluminum electrolytic), the actual capacitance value required relates to the physical size needed to achieve low ESR and the chemistry limits of the selected capacitor technology. Ceramic capacitors provide low ESR, but the capacitance and voltage rating (after derating) are determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). Thus, the output capacitor selection requires carefully balancing capacitor chemistry limitations (capacitance vs. ESR vs. voltage rating) and cost. For a standard 300kHz application, the effective zero frequency must be well below 95kHz, preferably below 50kHz. With these frequency requirements, standard tantalum and polymer capacitors already commonly used have typical ESR zero frequencies below 50kHz, allowing the stability requirements to be achieved without any additional current-sense compensation. In the standard application circuit (Figure 1), the ESR needed to support a 15mVP-P ripple is 15mV / (10A x 0.3) = 5mΩ. Two 330µF, 9mΩ polymer capacitors in parallel provide 4.5mΩ (max) ESR and 1 / (2π x 330µF x 9mΩ) = 53kHz ESR zero frequency. TON Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the in-phase feedback ripple relative to the switching frequency, which is typically dominated by the output ESR. The boundary of instability is given by the following equation: fSW 1 ≥ π 2πREFFCOUT REFF = RESR + RPCB + RCOMP PWR DH L1 LX COUT PWR MAX8792 PWR FB GND AGND PWR STABILITY REQUIREMENT 1 RESRCOUT ≥ 2fSW Figure 8. Standard Application with Output Polymer or Tantalum INPUT PCB PARASITIC RESISTANCE SENSE RESISTANCE FOR EVALUATION CIN BST OUTPUT DL where COUT is the total output capacitance, RESR is the total equivalent-series resistance of the output capacitors, RPCB is the parasitic board resistance between the output capacitors and feedback sense point, and RCOMP is the effective resistance of the DC- or AC-coupled current-sense compensation (see Figure 10). TON INPUT CIN BST PWR DH L1 LX OUTPUT COUT DL CLOAD PWR PWR PWR MAX8792 RCOMP 100Ω FB OUTPUT VOLTAGE REMOTELY SENSED NEAR POINT OF LOAD GND AGND PWR STABILITY REQUIREMENT 1 1 RESRCOUT ≥ AND RCOMPCCOMP ≥ 2fSW fSW FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT Figure 9. Remote-Sense Compensation for Stability and Noise Immunity 22 ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN The DC-coupling requires fewer external compensation capacitors, but this also creates an output load line that depends on the inductor’s DCR (parasitic resistance). Alternatively, the current-sense information may be ACcoupled, allowing stability to be dependent only on the inductance value and compensation components and eliminating the DC load line. OPTION A: DC-COUPLED CURRENT-SENSE COMPENSATION TON DC COMPENSATION <> FEWER COMPENSATION COMPONENTS <> CREATES OUTPUT LOAD LINE <> LESS OUTPUT CAPACITANCE REQUIRED FOR TRANSIENT RESPONSE INPUT CIN BST PWR DH L LX OUTPUT COUT RSENA DL RSENB MAX8792 PWR PWR CSEN FB GND AGND STABILITY REQUIREMENT PWR ⎛ ⎞ L RSENBRDCR 1 AND LOAD LINE = ⎜ R ⎟ COUT ≥ 2f || R C RSENA + RSENB SW ⎝ ( SENA SENB ) SEN ⎠ FEEDBACK RIPPLE IN-PHASE WITH INDUCTOR CURRENT OPTION B: AC-COUPLED CURRENT-SENSE COMPENSATION TON AC COMPENSATION <> NOT DEPENDENT ON ACTUAL DCR VALUE <> NO OUTPUT LOAD LINE INPUT CIN BST PWR DH L LX OUTPUT COUT RSEN DL CSEN MAX8792 PWR PWR CCOMP FB RCOMP GND STABILITY REQUIREMENT AGND PWR ⎛ L ⎞ 1 1 AND RCOMPCCOMP ≥ ⎜ ⎟ COUT ≥ ⎝ RSENCSEN ⎠ 2fSW fSW FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT Figure 10. Feedback Compensation for Ceramic Output Capacitors ______________________________________________________________________________________ 23 MAX8792 Ceramic capacitors have a high ESR zero frequency, but applications with sufficient current-sense compensation may still take advantage of the small size, low ESR, and high reliability of the ceramic chemistry. Using the inductor DCR, applications using ceramic output capacitors may be compensated using either a DC compensation or AC compensation method (Figure 10). MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value may allow significant output overshoot when stepping from full-load to no-load conditions, unless designed with a small inductance value and high switching frequency to minimize the energy transferred from the inductor to the capacitor during load-step recovery. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and feedbackloop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements may be determined by the following equation: ⎛I ⎞ IRMS = ⎜ LOAD ⎟ VOUT (VIN − VOUT ) ⎝ VIN ⎠ The worst-case RMS current requirement occurs when operating with VIN = 2VOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity. 24 Power-MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur (see the MOSFET Gate Drivers section). MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: ⎛V ⎞ PD (NH Re sistive) = ⎜ OUT ⎟ (ILOAD )2RDS(ON) ⎝ VIN ⎠ Generally, a small high-side MOSFET is desired to reduce switching losses at high-input voltages. However, the RDS(ON) required to stay within packagepower dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in the high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN ⎛ QG(SW) ⎞ PD (NH Switching) = VIN(MAX)ILOADfSW ⎜ ⎟+ ⎝ IGATE ⎠ COSSVIN2fSW 2 where COSS is the NH MOSFET’s output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: ⎡ ⎛ V ⎞⎤ 2 PD (NL Re sistive) = ⎢1 − ⎜ OUT ⎟ ⎥(ILOAD ) RDS(ON) ⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦ The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can “overdesign” the circuit to tolerate: ΔI ILOAD = IVALLEY(MAX) + L 2 ⎛ ILOAD(MAX)LIR ⎞ = IVALLEY(MAX) + ⎜ ⎟ 2 ⎝ ⎠ where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current during the dead times. This diode is optional and can be removed if efficiency is not critical. Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low- power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side, MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high-side MOSFETs’ gates: CBST = N × QGATE 200mV where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET’s data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 2 × 24nC = 0.24μF 200mV Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor. Minimum Input-Voltage Requirements and Dropout Performance The output voltage-adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time settings. When working with low-input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the on-times. This error is greater at higher frequencies. Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Quick-PWM Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). The ratio h = ΔIUP / ΔIDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used. ______________________________________________________________________________________ 25 MAX8792 rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: ⎛ V −V ⎞ +V VIN(MIN) = ⎜ FB DROOP DROPCHG ⎟ 1− (h × t OFF(MIN)fSW ) ⎝ ⎠ where VFB is the voltage-positioning droop, VDROPCHG is the parasitic voltage drop in the charge path, and tOFF(MIN) is from the Electrical Characteristics table. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. Dropout Design Example: VFB = 1.5V fSW = 300kHz tOFF(MIN) = 350ns No droop/load line (VDROOP = 0) VDROPCHG = 150mV (10A load) h = 1.5: ⎡ ⎤ 1.5V − 0V + 150mV VIN(MIN) = ⎢ ⎥ = 1.96V ⎣ 1− (1.5 × 350ns × 300kHz) ⎦ Calculating again with h = 1 gives the absolute limit of dropout: ⎡ ⎤ 1.5V − 0V + 150mV VIN(MIN) = ⎢ ⎥ = 1.84V ( . ) ns kHz − × × 1 1 0 350 300 ⎣ ⎦ 2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the VCC bypass capacitor, REF bypass capacitors, REFIN components, and feedback compensation/dividers. 3) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty. 4) Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. 5) When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. 6) Route high-speed switching nodes away from sensitive analog areas (REF, REFIN, FB, ILIM). Layout Procedure 1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copperfilled areas. Therefore, VIN must be greater than 1.84V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 2.0V. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). Applications Information 3) Group the gate-drive components (BST capacitors, VDD bypass capacitor) together near the controller IC. PCB Layout Guidelines 4) Make the DC-DC controller ground connections as shown in the Standard Application Circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and V DD bypass capacitor go; the master’s analog ground plane where sensitive analog components, the master’s GND pin, and VCC bypass capacitor go; and the slave’s analog ground plane where the slave’s GND Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PCB layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. 26 ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. Chip Information TRANSISTOR COUNT: 7169 PROCESS: BiCMOS ______________________________________________________________________________________ 27 MAX8792 pin and VCC bypass capacitor go. The master’s GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS MAX8792 Single Quick-PWM Step-Down Controller with Dynamic REFIN 28 ______________________________________________________________________________________ Single Quick-PWM Step-Down Controller with Dynamic REFIN COMMON DIMENSIONS PACKAGE VARIATIONS SYMBOL MIN. MAX. PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e A 0.70 0.80 T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF D 2.90 3.10 T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF E 2.90 3.10 T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF A1 0.00 0.05 T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF L 0.20 0.40 T1033-2 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF k 0.25 MIN. T1433-1 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF A2 0.20 REF. T1433-2 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF Note: MAX8792ETD+ Package Code = T1433-1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 29 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc. MAX8792 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)