19-2682; Rev 1; 10/08 Notebook CPU Step-Down Controller The MAX1718T step-down controller is intended for core CPU DC-to-DC converters in notebook computers. It features a dynamically adjustable output, ultra-fast transient response, high-DC accuracy, and high efficiency needed for leading-edge CPU core power supplies. Maxim’s proprietary Quick-PWM™ quick-response, constant-ontime PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. The output voltage can be dynamically adjusted through the 5-bit digital-to-analog converter (DAC) over a 0.6V to 1.75V range. The MAX1718T has an internal multiplexer that accepts three unique 5-bit VID DAC codes corresponding to performance, battery, and suspend modes. Precision slew-rate control provides “justin-time” arrival at the new DAC setting, minimizing surge currents to and from the battery. A pair of complementary offset control inputs allows easy compensation for IR drops in PCB traces or creation of a voltage-positioned power supply. Voltage positioning modifies the load-transient response to reduce output capacitor requirements and total system power dissipation. Single-stage buck conversion allows these devices to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery) at a higher switching frequency allows the minimum possible physical size. Features o o o o o o o o o o o o o o o o o Quick-PWM Architecture ±1% VOUT Accuracy Over Line and Load 5-Bit On-Board DAC with Input Muxes Precision-Adjustable VOUT Slew Control 0.6V to 1.75V Output Adjust Range Precision Offset Control Supports Voltage-Positioned Applications 2V to 28V Battery Input Range Requires a Separate 5V Bias Supply 200kHz/300kHz/550kHz/1000kHz Switching Frequency Overvoltage/Undervoltage Protection Drives Large Synchronous-Rectifier FETs 700µA (typ) ICC Supply Current 2µA (typ) Shutdown Supply Current 2V ±1% Reference Output VGATE Blanking During Transition Small 28-Pin QSOP Package Ordering Information PART MAX1718TEEI TEMP RANGE PIN-PACKAGE -40°C to +85°C 28 QSOP Minimal Operating Circuit 5V INPUT VCC SKP/SDN The MAX1718T is available in a 28-pin QSOP package. SHUTDOWN ILIM Applications 2-Cell to 4-Cell Li+ Battery to CPU Core Supply Converters 5V to CPU Core Supply Converters VDD V+ BST MAX1718T DH D0 D1 DUAL MODE™ VID MUX INPUTS MUX CONTROL SUSPEND INPUT DECODER BATT 2V TO 28V D2 D3 D4 OUTPUT 0.6V TO 1.75V LX DL GND ZMODE SUS S0 S1 FB TIME NEG CC POS VCC REF TON VGATE OVP POWER-GOOD OUTPUT Pin Configuration appears at end of data sheet. Quick-PWM is a trademark of Maxim Integrated Products, Inc. Dual Mode is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1718T General Description MAX1718T Notebook CPU Step-Down Controller ABSOLUTE MAXIMUM RATINGS V+ to GND ..............................................................-0.3V to +30V VCC, VDD to GND .....................................................-0.3V to +6V D0–D4, ZMODE, VGATE, OVP, SUS to GND ..........-0.3V to +6V SKP/SDN to GND ...................................................-0.3V to +16V ILIM, CC, REF, POS, NEG, S1, S0, TON, TIME to GND .....................................-0.3V to (VCC + 0.3V) DL to GND ..................................................-0.3V to (VDD + 0.3V) BST to GND ............................................................-0.3V to +36V DH to LX .....................................................-0.3V to (BST + 0.3V) LX to BST..................................................................-6V to +0.3V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation 28-Pin QSOP (derate 10.8mW/°C above +70°C).........860mW Operating Temperature Range ..........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VV+ = 15V, VCC = VDD = VSKP/SDN = 5V, VOUT = 1.25V, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range DC Output Voltage Accuracy Battery voltage, V+ 2 28 4.5 5.5 DAC codes from 0.9V to 1.75V -1 +1 DAC codes from 0.6V to 0.875V -1.5 +1.5 VCC, VDD VV+ = 4.5V to 28V, includes load regulation error % Line Regulation Error VCC = 4.5V to 5.5V, VBATT = 4.5V to 28V Input Bias Current FB, POS, NEG POS, NEG Common-Mode Range 5 +0.2 µA 0.4 2.5 V +80 mV 0.91 V/V POS - NEG -80 POS, NEG Offset Gain ΔVFB / (POS - NEG); POS - NEG = 50mV 0.81 On-Time (Note 1) mV -0.2 POS, NEG Differential Range TIME Frequency Accuracy 0.86 150kHz nominal, RTIME = 120kΩ -8 +8 380kHz nominal, RTIME = 47kΩ -12 +12 38kHz nominal, RTIME = 470kΩ -12 VV+ = 5V, FB = 1.2V, TON = GND (1000kHz) 230 260 TON = REF (550kHz) 165 190 215 TON = open (300kHz) 320 355 390 TON = VCC (200kHz) 465 VV+ = 12V, FB = 1.2V V % +12 290 ns 515 565 TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz) 400 500 TON = GND (1000kHz) 300 375 Quiescent Supply Current (VCC) Measured at VCC, FB forced above the regulation point 700 1200 µA Quiescent Supply Current (VDD) Measured at VDD, FB forced above the regulation point <1 5 µA 25 40 µA Minimum Off-Time (Note 1) ns BIAS AND REFERENCE Quiescent Battery Supply Current (V+) Shutdown Supply Current (VCC) SKP/SDN = GND 2 5 µA Shutdown Supply Current (VDD) SKP/SDN = GND <1 5 µA Shutdown Battery Supply Current (V+) SKP/SDN = GND, VCC = VDD = 0V or 5V <1 5 µA 2 _______________________________________________________________________________________ Notebook CPU Step-Down Controller (Circuit of Figure 1, VV+ = 15V, VCC = VDD = VSKP/SDN = 5V, VOUT = 1.25V, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS 1.98 2 2.02 V Reference Voltage VCC = 4.5V to 5.5V, no REF load Reference Load Regulation IREF = 0 to 50µA REF Sink Current REF in regulation 10 Overvoltage Trip Threshold Measured at FB 1.95 Overvoltage Fault Propagation Delay FB forced 2% above trip threshold Output Undervoltage Fault Protection Threshold With respect to unloaded output voltage Output Undervoltage Fault Propagation Delay FB forced 2% below trip threshold 10 µs Output Undervoltage Fault Blanking Time From SKP/SDN signal going high, clock speed set by RTIME 256 clks Current-Limit Threshold Voltage (Positive, Default) GND - LX, ILIM = VCC Current-Limit Threshold Voltage (Positive, Adjustable) GND - LX Current-Limit Threshold Voltage (Negative) LX - GND, ILIM = VCC Current-Limit Threshold Voltage (Zero Crossing) GND - LX 0.01 V µA FAULT PROTECTION 2.00 2.05 10 65 TA = +25°C to +85°C 90 TA = 0°C to +85°C 85 70 100 µs 75 110 115 VILIM = 0.5V 35 50 65 ILIM = REF (2V) 165 200 230 -140 -117 -95 Current-Limit Default Switchover Threshold 4 3 V % mV mV mV mV VCC - 1 VCC - 0.4 150 V Thermal Shutdown Threshold Hysteresis = +10°C VCC Undervoltage Lockout Threshold Rising edge, hysteresis = 20mV, PWM disabled below this level °C 4.1 VGATE Lower Trip Threshold Measured at FB with respect to unloaded output voltage -12 -10 -8 % VGATE Upper Trip Threshold Measured at FB with respect to unloaded output voltage +8 +10 +12 % VGATE Propagation Delay FB forced 2% outside VGATE trip threshold VGATE Output Low Voltage ISINK = 1mA VGATE Leakage Current High state, forced to 5.5V 4.4 10 V µs 0.4 V 1 µA Ω GATE DRIVERS DH Gate-Driver On-Resistance BST - LX forced to 5V 1.0 3.5 DL, high state (pullup) 1.0 3.5 DL, low state (pulldown) 0.4 1.0 DH Gate-Driver Source/Sink Current DH forced to 2.5V, BST - LX forced to 5V 1.6 A DL Gate-Driver Sink Current DL forced to 2.5V 4 A DL Gate-Driver Source Current DL forced to 2.5V 1.6 A DL Gate-Driver On-Resistance Ω _______________________________________________________________________________________ 3 MAX1718T ELECTRICAL CHARACTERISTICS (continued) MAX1718T Notebook CPU Step-Down Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VV+ = 15V, VCC = VDD = VSKP/SDN = 5V, VOUT = 1.25V, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER Dead Time CONDITIONS MIN TYP DL rising 35 DH rising 26 MAX UNITS ns LOGIC AND I/O Logic Input High Voltage D0–D4, ZMODE, SUS, OVP Logic Input Low Voltage D0–D4, ZMODE, SUS, OVP 0.8 V DAC B-Mode Programming Resistor, Low D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, ZMODE = VCC 1.05 kΩ DAC B-Mode Programming Resistor, High D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, ZMODE = VCC D0–D4 Pullup/Pulldown Entering impedance mode Logic Input Current Four Level Input Logic Levels (TON, S0, S1) 2.4 V 95 kΩ Pullup 40 Pulldown 8 D0–D4, ZMODE = GND -1 +1 ZMODE, SUS, OVP -1 +1 For high VCC - 0.4 For open 3.15 3.85 For REF 1.65 2.35 For low SKP/SDN, S0, S1, and TON Input Current SKP/SDN Input Levels SKP/SDN Float Level kΩ µA V 0.5 SKP/SDN, S0, S1, TON forced to GND or VCC -3 +3 SKP/SDN = logic high (SKIP mode) 2.8 6.0 SKP/SDN = open (PWM mode) 1.4 2.2 SKP/SDN = logic low (shutdown mode) 0.5 To enable no-fault mode 12 15 ISKP/SDN = 0µA 1.8 2.2 µA V V ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VV+ = 15V, VCC = VDD = VSKP/SDN = 5V, VOUT = 1.25V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX DAC codes from 0.9V to 1.75V -1.5 +1.5 DAC codes from 0.6V to 0.875V -2.0 +2.0 UNITS PWM CONTROLLER DC Output Voltage Accuracy TIME Frequency Accuracy On-Time (Note 1) 4 VV+ = 4.5V to 28V, includes load regulation error % 150kHz nominal, RTIME = 120kΩ -8 +8 380kHz nominal, RTIME = 47kΩ -12 +12 38kHz nominal, RTIME = 470kΩ -12 +12 VV+ = 5V, VFB = 1.2V, TON = GND (1000kHz) 230 290 TON = REF (550kHz) 165 215 TON = open (300kHz) 320 390 TON = VCC (200kHz) 465 565 VV+ = 12V, VFB = 1.2V _______________________________________________________________________________________ % ns Notebook CPU Step-Down Controller (Circuit of Figure 1, VV+ = 15V, VCC = VDD = VSKP/SDN = 5V, VOUT = 1.25V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)) PARAMETER CONDITIONS MIN TYP MAX UNITS TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz) 500 TON = GND (1000kHz) 375 Quiescent Supply Current (VCC) Measured at VCC, FB forced above the regulation point 1300 µA Quiescent Supply Current (VDD) Measured at VDD, FB forced above the regulation point 5 µA 40 µA Minimum Off-Time (Note 1) ns BIAS AND REFERENCE Quiescent Battery Supply Current (V+) Shutdown Supply Current (VCC) VSKP/SDN = 0 5 µA Shutdown Supply Current (VDD) VSKP/SDN = 0 5 µA Shutdown Battery Supply Current (V+) VSKP/SDN = 0, VCC = VDD = 0 or 5V 5 µA Reference Voltage VCC = 4.5V to 5.5V, no REF load 1.98 2.02 V Overvoltage Trip Threshold Measured at FB 1.95 2.05 V Output Undervoltage Protection Threshold With respect to unloaded output voltage 65 75 % Current-Limit Threshold Voltage (Positive, Default) GND - LX, ILIM = VCC 80 115 mV Current-Limit Threshold Voltage (Positive, Adjustable) GND - LX Current-Limit Threshold Voltage (Negative) LX - GND, ILIM = VCC VCC Undervoltage Lockout Threshold Rising edge, hysteresis = 20mV, PWM disabled below this level VGATE Lower Trip Threshold Measured at FB with respect to unloaded output voltage VGATE Upper Trip Threshold Measured at FB with respect to unloaded output voltage FAULT PROTECTION ILIM = 0.5V 33 65 ILIM = REF (2V) 160 240 -145 -90 mV 4.1 4.4 V -12.5 -7.5 % +7.5 +12.5 % BST - LX forced to 5V 3.5 Ω DL, high state (pullup) 3.5 DL, low state (pulldown) 1.0 mV GATE DRIVERS DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance Ω LOGIC AND I/O Logic Input High Voltage D0–D4, ZMODE, SUS, OVP Logic Input Low Voltage D0–D4, ZMODE, SUS, OVP 2.4 V 0.8 V _______________________________________________________________________________________ 5 MAX1718T ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VV+ = 15V, VCC = VDD = VSKP/SDN = 5V, VOUT = 1.25V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)) PARAMETER CONDITIONS MIN DAC B-Mode Programming Resistor, Low D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, ZMODE = VCC DAC B-Mode Programming Resistor, High D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, ZMODE = VCC TYP MAX UNITS 1.05 kΩ 95 kΩ Note 1: On-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times can be different due to MOSFET switching speeds. Note 2: Specifications to TA = -40°C are guaranteed by design and not production tested. Typical Operating Characteristics (Circuit of Figure 1, VV+ = 12V, VDD = VCC = VSKP/SDN = 5V, VOUT = 1.25V, TA = +25°C, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT 300kHz VOLTAGE POSITIONED 330 PWM MODE V+ = 7V SKIP MODE V+ = 12V 65 PWM MODE V+ = 12V SKIP MODE V+ = 20V 60 SKIP MODE 200 0.1 1 300 290 IOUT = 3A 270 260 250 0 50 10 0 100 5 10 15 7.0 20 10.4 13.8 17.2 LOAD CURRENT (A) INPUT VOLTAGE (V) FREQUENCY vs. TEMPERATURE OUTPUT CURRENT AT CURRENT LIMIT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE 50 CURRENT (A) 325.0 45 324.5 40 35 324.0 30 323.5 25 323.0 20 ICC + IDD 900 800 SUPPLY CURRENT (μA) 325.5 1000 MAX1718T toc05 IOUT = 19A -15 10 35 TEMPERATURE (°C) 6 60 85 24.0 700 600 500 400 300 200 100 -40 20.6 LOAD CURRENT (A) MAX1718T toc04 0.01 IOUT = 18A 310 280 100 PWM MODE V+ = 20V 55 320 MAX1718T toc06 70 FREQUENCY (kHz) 75 326.0 340 300 80 MAX1718T toc03 PWM MODE FREQUENCY (kHz) EFFICIENCY (%) 85 350 MAX1718T toc02 SKIP MODE V+ = 7V 90 FREQUENCY vs. INPUT VOLTAGE FREQUENCY vs. LOAD CURRENT 400 MAX1718T toc01 95 FREQUENCY (kHz) MAX1718T Notebook CPU Step-Down Controller I+ 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 5 10 15 INPUT VOLTAGE (V) _______________________________________________________________________________________ 20 25 Notebook CPU Step-Down Controller MAX1718T Typical Operating Characteristics (continued) (Circuit of Figure 1, VV+ = 12V, VDD = VCC = VSKP/SDN = 5V, VOUT = 1.25V, TA = +25°C, unless otherwise noted.) NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE LOAD-TRANSIENT RESPONSE (SKIP MODE) MAX1718T toc08a MAX1718T toc07 40 35 SUPPLY CURRENT (mA) LOAD-TRANSIENT RESPONSE (PWM MODE) MAX1718T toc08b A A 30 25 20 ICC + IDD 15 I+ 10 0A B 5 B 0A 0 5 10 15 20 25 40μs/div INPUT VOLTAGE (V) 40μs/div A = VOUT, 50mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div STARTUP WAVEFORM (PWM MODE, NO LOAD) A = VOUT, 50mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div STARTUP WAVEFORM (PWM MODE, IOUT = 12A) MAX1718T toc09 DYNAMIC OUTPUT VOLTAGE TRANSITION (PWM MODE) MAX1718T toc10 A MAX1718T toc11 A A B B 0A C B 0A 0A C C D 100μs/div A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div 100μs/div A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div 40μs/div VOUT = 1.15V TO 1.25V IOUT = 3A, RTIME = 62kΩ A = VOUT, 100mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div C = VGATE, 5V/div D = ZMODE, 5V/div _______________________________________________________________________________________ 7 Typical Operating Characteristics (continued) (Circuit of Figure 1, VV+ = 12V, VDD = VCC = VSKP/SDN = 5V, VOUT = 1.25V, TA = +25°C, unless otherwise noted.) SHUTDOWN WAVEFORM (PWM MODE, NO LOAD) DYNAMIC OUTPUT VOLTAGE TRANSITION (PWM MODE) SHUTDOWN WAVEFORM (PWM MODE, IOUT = 12A) MAX1718T toc13 MAX1718T toc12 MAX1718T toc14 A A B A B 0A 0A B C C 0A C D 100μs/div A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div 40μs/div VOUT = 0.7V TO 1.25V IOUT = 3A, RTIME = 62kΩ A = VOUT, 500mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div C = VGATE, 5V/div D = SUS, 5V/div 100μs/div A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div OUTPUT VOLTAGE vs. POS-NEG DIFFERENTIAL OFFSET FUNCTION SCALE FACTOR vs. DAC SETTING 0.875 THEORETICAL 0.850 1.40 1.35 OUTPUT VOLTAGE (V) MEASURED 0.825 0.800 MAX1718T toc16 0.900 1.45 MAX1718T toc15 0.925 POS-NEG SCALE FACTOR MAX1718T Notebook CPU Step-Down Controller 1.30 1.25 1.20 1.15 1.10 0.775 1.05 1.00 0.750 0.5 0.7 0.9 1.1 1.3 DAC SETTING (V) 8 1.5 1.7 1.9 -300 -200 -100 0 100 200 POS-NEG (V) _______________________________________________________________________________________ Notebook CPU Step-Down Controller 15 10 5 0 -0.48 MAX1718T toc18 20 25 SAMPLE PERCENTAGE (%) SAMPLE PERCENTAGE (%) VOUT = 1.25V REFERENCE VOLTAGE DISTRIBUTION MAX1718T toc17 OUTPUT VOLTAGE DISTRIBUTION 25 20 15 10 5 -0.24 0 0.24 0.48 0 1.995 1.998 OUTPUT VOLTAGE ERROR (%) 2.000 2.002 2.005 REFERENCE VOLTAGE (V) Pin Description PIN NAME 1 V+ 2 FUNCTION Battery Voltage Sense Connection. Connect V+ to input power source. V+ is used only for PWM one-shot timing. DH on-time is inversely proportional to input voltage over a range of 2V to 28V. Combined Shutdown and Skip-Mode Control. Drive SKP/SDN to GND for shutdown. Leave SKP/SDN open for low-noise forced-PWM mode, or drive to VCC for pulse-skipping operation. Low-noise forced-PWM mode SKP/SDN causes inductor current recirculation at light loads and suppresses pulse-skipping operation. Forcing SKP/SDN to 12V to 15V disables both the overvoltage protection and undervoltage protection circuits and clears the fault latch, with otherwise normal pulse-skipping operation. Do not connect SKP/SDN to > 15V. Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 470kΩ to 47kΩ resistor sets the clock from 38kHz to 380kHz, fSLEW = 150kHz 5 120kΩ / RTIME. 3 TIME 4 FB 5 NEG Feedback Offset Adjust Negative Input. The output shifts by an amount equal to the difference between POS and NEG multiplied by a scale factor that depends on the DAC codes (see the Integrator Amplifiers/Output Voltage Offsets section). Connect both POS and NEG to REF if the offset function is not used. 6 CC Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF typ) capacitor from CC to GND to set the integration time constant (see the Integrator Amplifiers/Output Voltage Offsets section). 7, 8 S0, S1 Suspend-Mode Voltage Select Input. S0 and S1 are four-level digital inputs that select the suspend-mode VID code for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID code is delivered to the DAC (see the Internal Multiplexers (ZMODE/SUS) section). 9 VCC Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a series 20Ω resistor. Bypass to GND with a 0.22µF (min) capacitor. Feedback Input. Connect FB to the junction of the external inductor and the positioning resistor (Figure 1). _______________________________________________________________________________________ 9 MAX1718T Typical Operating Characteristics (continued) (Circuit of Figure 1, VV+ = 12V, VDD = VCC = VSKP/SDN = 5V, VOUT = 1.25V, TA = +25°C, unless otherwise noted.) Notebook CPU Step-Down Controller MAX1718T Pin Description (continued) PIN NAME FUNCTION 10 TON On-Time Selection Control Input. This is a four-level input that sets the K factor (Table 2) to determine DH on-time. Connect TON to the following pins for the indicated operation: GND = 1000kHz REF = 550kHz Open = 300kHz VCC = 200kHz 11 REF 2V Reference Output. Bypass to GND with 0.22µF (min) capacitor. Can source 50µA for external loads. Loading REF degrades FB accuracy according to the REF load-regulation error. 12 ILIM Current-Limit Adjustment. The GND - LX current-limit threshold defaults to 100mV if ILIM is connected to VCC. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a 0.5V to 3V range. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. Connect ILIM to REF for a fixed 200mV threshold. 13 POS Feedback Offset Adjust Negative Input. The output shifts by an amount equal to the difference between POS and NEG multiplied by a scale factor that depends on the DAC codes (see the Integrator Amplifiers/Output Voltage Offsets section). Connect both POS and NEG to REF if the offset function is not used. 14 VGATE Open-Drain Power-Good Output. VGATE is normally high when the output is in regulation. If VFB is not within a ±10% window of the DAC setting, VGATE is asserted low. During DAC code transitions, VGATE is forced high until 1 clock period after the slew-rate controller finishes the transition. VGATE is low during shutdown. 15 GND 16 DL 17 VDD Supply Voltage Input for the DL Gate Driver, 4.5V to 5.5V. Bypass to GND with a 1µF capacitor. 18 SUS Suspend-Mode Control Input. When SUS is high, the suspend-mode VID code, as programmed by S0 and S1, is delivered to the DAC. Connect SUS to GND if the suspend-mode multiplexer is not used (see the Internal Multiplexers (ZMODE/SUS) section). Analog and Power Ground. Also connects to the current-limit comparator. Low-Side Gate-Driver Output. DL swings GND to VDD. 19 ZMODE Performance-Mode MUX Control Input. If SUS is low, ZMODE selects between two different VID DAC codes. If ZMODE is low, the VID DAC code is set by the logic-level voltages on D0–D4. On the rising edge of ZMODE, during power-up with ZMODE high, or on the falling edge of SUS when ZMODE is high, the VID DAC code is determined by the impedance at D0–D4 (see the Internal Multiplexers (ZMODE/SUS) section). 20 OVP Overvoltage Protection Control Input. Connect OVP low to enable overvoltage protection. Connect OVP high to disable overvoltage protection. The overvoltage trip threshold is approximately 2V. The state of OVP does not affect output undervoltage fault protection or thermal shutdown. 21–25 D4–D0 VID DAC Code Inputs. D0 is the LSB, and D4 is the MSB of the internal 5-bit VID DAC (Table 3). If ZMODE is low, D0–D4 are high-impedance digital inputs, and the VID DAC code is set by the logic-level voltages on D0–D4. On the rising edge of ZMODE, during power-up with ZMODE high, or on the falling edge of SUS when ZMODE is high, the VID DAC code is determined by the impedance at D0–D4 as follows: Logic low = source impedance is ≤1kΩ + 5%. Logic high = source impedance is ≥100kΩ - 5%. 26 BST 27 LX Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It also connects to the current-limit comparator and the skip-mode zero-crossing comparator. 28 DH High-Side Gate-Driver Output. DH swings LX to BST. 10 Boost Flying Capacitor Connection. Connect BST to the external boost diode and capacitor as shown in Figure 1. An optional resistor in series with BST allows the DH pullup current to be adjusted (Figure 8). ______________________________________________________________________________________ Notebook CPU Step-Down Controller C7 1μF 10 SHUTDOWN 25 VCC 24 R2 100kΩ R3 100kΩ 5V INPUT 23 22 21 VDD V+ BST TON D0 DH REF R4 62kΩ MAX1718T DL D4 FB NEG CC POS C5 0.22μF 11 R18 24.9kΩ L1 0.68μH 16 R8 0.004Ω SUMIDA CEP125#4712-TO11 FDS7764A Q2 D2 CENTRAL SEMICONDUCTOR CMSH5-40 OUTPUT 0.6V TO 1.75V C4 6 x 270μF, 2V PANASONIC SP EEFUE0D271R 15 4 5 13 REF ILIM OVP R7 4.75kΩ 5V R6 511kΩ VGATE 12 28 TIME C6 47pF 6 2x IRF7811A Q1 2x 19 ZMODE 18 SUS 3 26 LX 27 D3 7 S0 8 S1 SUSPEND INPUT DECODER C2, 25V, X5R 5 x 10μF D1 CMPSH-3 C3 0.1μF D2 BATT 7V TO 24V 1 D1 GND MUX CONTROL C1 1μF 17 9 VCC 2 SKP/SDN MAX1718T R1 20Ω 14 20 R5 100kΩ POWER-GOOD OUTPUT R19 27.4kΩ Figure 1. Standard Application Circuit ______________________________________________________________________________________ 11 MAX1718T Notebook CPU Step-Down Controller Free-Running, Constant-On-Time PWM Controller with Input Feed Forward Table 1. Component Suppliers MANUFACTURER PHONE FAX Central Semiconductor 516-435-1110 516-435-1824 Dale-Vishay 402-564-3131 402-563-6418 Fairchild 408-721-2181 408-721-1635 International Rectifier 310-322-3331 310-322-3332 Kemet 408-986-0424 408-986-1442 Motorola 602-303-5454 602-994-6430 Nihon 847-843-7500 847-843-2798 Panasonic 714-373-7939 714-373-7183 Sanyo 619-661-6835 619-661-1055 SGS-Thomson 617-259-0300 617-259-9442 Sumida 708-956-0666 708-956-0702 Taiyo Yuden 408-573-4150 408-573-4159 On-Time One-Shot (TON) TDK 847-390-4373 847-390-4428 Toko 800-745-8656 408-943-9790 Zetex 516-543-7100 516-864-7630 The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple: Detailed Description 5V Bias Supply (VCC and VDD) The MAX1718T requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook’s 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator. The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + f (QG1 + QG2) = 10mA to 40mA (typ) where ICC is 800µA (typ), f is the switching frequency, and QG1 and QG2 are the MOSFET data sheet total gate-charge specification limits at VGS = 5V. V+ and VDD can be tied together if the input power source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (SKP/SDN going from low to high or open) must be delayed until the battery voltage is present to ensure startup. 12 The Quick-PWM control architecture is a pseudofixedfrequency, constant-on-time current-mode type with voltage feed forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (400ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time oneshot has timed out. On-time = K (VOUT + 0.075V) / VIN where K is set by the TON pin-strap connection and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch (Table 2). The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics table (±10% at 200kHz and 300kHz, ±12% at 550kHz and 1000kHz). On-times at operating points far removed from the conditions specified in the Electrical Characteristics table can vary over a wider range. For example, the 1000kHz setting typically runs about 10% slower with inputs much greater than +5V due to the very short ontimes required. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the ______________________________________________________________________________________ Notebook CPU Step-Down Controller MAX1718T VBATT 2V TO 28V REF V+ ILIM MAX1718T TOFF TON ON-TIME COMPUTE TON S Q TRIG 5V 1-SHOT TRIG Q FROM D/A 9 BST 1 Q R DH CURRENT LIMIT 1-SHOT Σ LX ERROR AMP SKP/SDN REF ZERO CROSSING VDD 10kΩ OUTPUT 5V 70kΩ CC DL REF S Q R gm gm GND NEG FB POS REF -10% REF +10% FB OVP/UVP DETECT VGATE OVP R-2R D/A CONVERTER CHIP SUPPLY VCC 2V REF REF 5V MUXES AND SLEW CONTROL ZMODE SUS S1 S0 D0 D1 D2 D3 D4 TIME Figure 2. Functional Diagram ______________________________________________________________________________________ 13 MAX1718T Notebook CPU Step-Down Controller Table 2. Approximate K-Factor Errors TON FREQUENCY (kHZ) TON SETTING K-FACTOR (µs) APPROXIMATE K-FACTOR ERROR (%) VOUT = 1.25V (V) VOUT = 1.75V (V) VCC 200 5 ±10 1.7 2.3 OPEN 300 3.3 ±10 1.8 2.5 REF 550 1.8 ±12.5 2.6 3.5 GND 1000 1.0 ±12.5 3.6 4.9 external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PCB copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only in PWM mode (SKP/SDN = open) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: f= (VOUT + VDROP1) tON (VIN + VDROP1 - VDROP2 ) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VDROP2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resistances; and tON is the on-time calculated by the MAX1718T. Integrator Amplifiers/Output Voltage Offsets Two transconductance integrator amplifiers provide a fine adjustment to the output regulation point. One amplifier forces the DC average of the feedback voltage to equal the VID DAC setting. The second amplifier is used to create small positive or negative offsets from the VID DAC setting, using the POS and NEG pins. The integrator block has the ability to lower the output voltage by 8% and raise it by 8%. For each amplifier, the differential input voltage range is at least ±80mV total, including DC offset and AC ripple. The two amplifiers’ outputs are directly summed inside the chip, so the integration time constant can be set easily with one capacitor 14 MIN RECOMMENDED VBATT AT at the CC pin. Use a capacitor value of 47pF to 1000pF (47pF typ). The gm of each amplifier is 160µS (typ). The POS/NEG amplifier is used to add small offsets to the VID DAC setting or to correct for voltage drops. To create an output offset, bias POS and NEG to a voltage (typically V OUT or REF) within their common-mode range, and offset them from one another with a resistive divider (Figures 3 and 4). If VPOS is higher than VNEG, then the output is shifted in the positive direction. If VNEG is higher than VPOS, then the output is shifted in the negative direction. The amount of output offset is less than the difference from POS to NEG by a scale factor that varies with the VID DAC setting as shown in Table 3. The common-mode range of POS and NEG is 0.4V to 2.5V. For applications that require multiple offsets, an external multiplexer can be used to select various resistor values (Figure 5). Both the integrator amplifiers can be disabled by connecting NEG to VCC. Forced-PWM Mode (SKP/SDN Open) The low-noise forced-PWM mode (SKP/SDN open) disables the zero-crossing comparator, allowing the inductor current to reverse at light loads. This causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: The no-load battery current can be 10mA to 40mA, depending on the external MOSFETs and switching frequency. Forced-PWM mode is required during downward output voltage transitions. The MAX1718T uses PWM mode during all transitions, but only while the slew-rate controller is active. Due to voltage positioning, when a transition uses high negative inductor current, the output voltage does not settle to its final intended value until well after the slew-rate controller terminates. Consequently it is possible, at very high negative slew currents, for the output to end up high enough to cause VGATE to go low. ______________________________________________________________________________________ Notebook CPU Step-Down Controller REF MAX1718T POS Automatic Pulse-Skipping Switchover In skip mode (SKP/SDN high), an inherent automatic switchover to PFM takes place at light loads (Figure 6). This switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 6). For a battery range of 7V to 24V, this threshold is relatively constant, with only a minor dependence on battery voltage: NEG Figure 3. Resistive Divider from REF DH DL I LOAD(SKIP) ≈ MAX1718T POS K × VOUT 2 × L × VBATT - VOUT VBATT where K is the on-time scale factor (Table 2). For example, in the standard application circuit this becomes: NEG 3.3μs × 1.25V 12V - 1.25V × = 2.7A 2 × 0.68μH 12V Figure 4. Resistive Divider from OUTPUT The crossover point occurs at a lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. DH DL MAX1718T POS NEG MUX MAX4524 SEL A B Figure 5. Programmable Offset Voltage Current-Limit Circuit The current-limit circuit employs a unique “valley” currentsensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 7). The actual peak current is greater than the ______________________________________________________________________________________ 15 MAX1718T Thus, it is necessary to use forced-PWM mode during all negative transitions. Most applications should use PWM mode exclusively, although there is some benefit to using skip mode while in the low-power suspend state (see the Using Skip Mode During Suspend (SKP/SDN = VCC) section.) Δi VBATT - VOUT = Δt L IPEAK INDUCTOR CURRENT IPEAK ILOAD ILOAD = IPEAK/2 0 ON-TIME TIME Figure 6. Pulse-Skipping/Discontinuous Crossover Point current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the MOSFET on-resistance, inductor value, and battery voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the undervoltage protection circuit, this currentlimit method is effective in almost every circumstance. There is also a negative current limit that prevents excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM. The current-limit threshold voltage adjustment range is from 50mV to 300mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM. The threshold defaults to 100mV when ILIM is connected to VCC. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. The adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see the Design Procedure section). For a high-accuracy current-limit application, see Figure 16. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the currentsense signals seen by LX and GND. Place the IC close to the low-side MOSFET with short, direct traces, making a Kelvin-sense connection to the source and drain terminals. 16 INDUCTOR CURRENT MAX1718T Notebook CPU Step-Down Controller ILIMIT 0 TIME Figure 7. “Valley” Current-Limit Threshold Point MOSFET Gate Drivers (DH, DL) The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VBATT - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in t0he MAX1718T interprets the MOSFET gate as “off” while there is actually still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares (50 mils to 100 mils wide if the MOSFET is 1in from the MAX1718T). The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typ) internal delay. The internal pulldown transistor that drives DL low is robust, with a 0.4Ω (typ) on-resistance. This helps prevent DL from being pulled up during the fast rise time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. However, for high-current applications, you might still encounter some combinations of high- and low-side FETs that causes excessive gate-drain coupling, which can lead to efficiency-killing, EMIproducing shoot-through currents. This is often remedied by adding a resistor in series with BST, which increases the turn-on time of the high-side FET without degrading the turn-off time (Figure 8). POR Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the PWM for operation. V CC undervoltage lockout (UVLO) circuitry inhibits switching, forces VGATE low, ______________________________________________________________________________________ Notebook CPU Step-Down Controller VBATT DAC Inputs D0–D4 BST 5Ω TYP DH LX MAX1718T Figure 8. Reducing the Switching-Node Rise Time and forces the DL gate driver high (to enforce output overvoltage protection). When VCC rises above 4.2V, the DAC inputs are sampled and the output voltage begins to slew to the DAC setting. For automatic startup, the battery voltage should be present before VCC. If the MAX1718T attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The SKP/SDN pin can be toggled to reset the fault latch. Shutdown When SKP/SDN goes low, the MAX1718T enters lowpower shutdown mode. VGATE goes low immediately. The output voltage ramps down to 0V in 25mV steps at the clock rate set by RTIME. When the DAC reaches the 0V setting, DL goes high, DH goes low, the reference is turned off, and the supply current drops to about 2µA. When SKP/SDN goes high or floats, the reference powers up, and after the reference UVLO is passed, the DAC target is evaluated and switching begins. The slewrate controller ramps up from 0V in 25mV steps to the currently selected code value (based on ZMODE and SUS). There is no traditional soft-start (variable current limit) circuitry, so full output current is available immediately. VGATE goes high after the slew-rate controller has terminated and the output voltage is in regulation. UVLO If VCC drops low enough to trip the UVLO comparator, it is assumed that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, DL is forced high in this mode. This forces the output to GND, but it does not use the slewrate controller. This results in large negative inductor current and possibly small negative output voltages. If VCC is likely to drop in this fashion, the output can be The DAC programs the output voltage. It typically receives a preset digital code from the CPU pins, which are either hardwired to GND or left open circuit. They can also be driven by digital logic, general-purpose I/O, or an external mux. Do not leave D0–D4 floating— use 1MΩ or less pullups if the inputs may float. D0–D4 can be changed while the SMPS is active, initiating a transition to a new output voltage level. If this mode of DAC control is used, connect ZMODE and SUS low. Change D0–D4 together, avoiding greater than 1µs skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level, followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are listed in Table 3. Internal Multiplexers (ZMODE, SUS) The MAX1718T has two unique internal VID input multiplexers (muxes) that can select one of three different VID DAC code settings for different processor states. Depending on the logic level at SUS, the suspend (SUS) mode mux selects the VID DAC code settings from either the ZMODE mux or the S0/S1 input decoder. The ZMODE mux selects one of the two VID DAC code settings from the D0–D4 pins, based on either voltage on the pins or the output of the impedance decoder (Figure 9). When SUS is high, the suspend mode mux selects the VID DAC code settings from the S0/S1 input decoder. The outputs of the decoder are determined by inputs S0 and S1 (Table 4). When SUS is low, the suspend mode mux selects the output of the ZMODE mux. Depending on the logic level at ZMODE, the ZMODE mux selects the VID DAC code settings using either the voltage on D0–D4 or the output of the impedance decoder (Table 5). If ZMODE is low, the logic-level voltages on D0–D4 set the VID DAC settings. This is called logic mode. In this mode, the inputs are continuously active and can be dynamically changed by external logic. The logic mode VID DAC code setting is typically used for the battery mode state, and the source of this code is sometimes the VID pins of the CPU with suitable pullup resistors. On the rising edge of ZMODE, during power-up with ZMODE high or on the falling edge of SUS when ZMODE is high, the impedances at D0–D4 are sampled by the impedance decoder to see if a large resistance ______________________________________________________________________________________ 17 MAX1718T clamped with a Schottky diode to GND to reduce the negative excursion. +5V MAX1718T Notebook CPU Step-Down Controller Table 3. Output Voltage vs. DAC Codes 18 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) POS/NEG SCALE FACTOR 0 0 0 0 0 1.75 0.90 0 0 0 0 1 1.70 0.90 0 0 0 1 0 1.65 0.90 0 0 0 1 1 1.60 0.89 0 0 1 0 0 1.55 0.89 0 0 1 0 1 1.50 0.89 0 0 1 1 0 1.45 0.88 0 0 1 1 1 1.40 0.88 0 1 0 0 0 1.35 0.88 0 1 0 0 1 1.30 0.87 0 1 0 1 0 1.25 0.87 0 1 0 1 1 1.20 0.86 0 1 1 0 0 1.15 0.86 0 1 1 0 1 1.10 0.85 0 1 1 1 0 1.05 0.85 0 1 1 1 1 1.00 0.84 1 0 0 0 0 0.975 0.84 1 0 0 0 1 0.950 0.83 1 0 0 1 0 0.925 0.83 1 0 0 1 1 0.900 0.82 1 0 1 0 0 0.875 0.82 1 0 1 0 1 0.850 0.82 1 0 1 1 0 0.825 0.81 1 0 1 1 1 0.800 0.81 1 1 0 0 0 0.775 0.80 1 1 0 0 1 0.750 0.80 1 1 0 1 0 0.725 0.79 1 1 0 1 1 0.700 0.78 1 1 1 0 0 0.675 0.78 1 1 1 0 1 0.650 0.77 1 1 1 1 0 0.625 0.76 1 1 1 1 1 0.600 0.76 ______________________________________________________________________________________ Notebook CPU Step-Down Controller Table 4. Suspend Mode DAC Codes S1 S0 OUTPUT VOLTAGE (V) GND GND 0.975 GND REF 0.950 GND OPEN 0.925 GND VCC 0.900 REF GND 0.875 REF REF 0.850 REF OPEN 0.825 REF VCC 0.800 OPEN GND 0.775 OPEN REF 0.750 OPEN OPEN 0.725 OPEN VCC 0.700 VCC GND 0.675 VCC REF 0.650 Using the ZMODE Mux VCC OPEN 0.625 There are many ways to use the versatile ZMODE mux. The preferred method depends on when and how the VID DAC codes for the various states are determined. If the output voltage codes are fixed at PCB design time, program both codes with a simple combination of pinstrap connections and series resistors (Figure 11). If the output voltage codes are chosen during PCB assembly, both codes can be independently programmed with resistors (Figure 12). This matrix of 10 resistor-footprints can be programmed to all possible logic mode and impedance mode code combinations with only five resistors. VCC VCC 0.600 Often the CPU pins provide one set of codes that are typically used with pullup resistors to provide the logic mode VID code, and resistors in series with D0–D4 set the impedance mode code. Since some of the CPU’s VID pins may float, the open-circuit pins can present a problem for the ZMODE mux’s impedance mode. For the impedance mode to work, any pins intended to be low during impedance mode must appear to be low impedance, at least for the 4µs sampling interval. This can be achieved in several ways, including the following two (Figure 13). By using low-impedance pullup ZMODE MUX D0 D1 D2 D3 D4 1 SUS MUX OUT IMPEDANCE DECODER 0 0 SEL IN OUT VCC POR S0/S1 DECODER ZMODE S0 S1 OUT DAC 1 SEL IN SUS Figure 9. Internal Multiplexers Functional Diagram ______________________________________________________________________________________ 19 MAX1718T is in series with the pin. This is called Impedance mode. If the voltage level on the pin is a logic low, an internal switch connects the pin to an internal 26kΩ pullup for about 4µs to see if the pin voltage can be forced high (Figure 10). If the pin voltage can be pulled to a logic high, the impedance is considered high and so is the Impedance mode logic state. Similarly, if the voltage level on the pin is a logic high, an internal switch connects the pin to an internal 8kΩ pulldown to see if the pin voltage can be forced low. If so, the pin is high impedance and its impedance mode logic state is high. In either sampling condition, if the pin’s logic level does not change, the pin is determined to be low impedance and the impedance mode logic state is low. A high pin impedance (and logic high) is 100kΩ or greater, and a low impedance (and logic low) is 1kΩ or less. The Electrical Characteristics table guaranteed levels for these impedances are 95kΩ and 1.05kΩ to allow the use of standard 100kΩ and 1kΩ resistors with 5% tolerance. MAX1718T Notebook CPU Step-Down Controller +5V VCC MAX1718T 3.0V TO 5.5V 26kΩ 26kΩ 26kΩ 26kΩ 26kΩ D4 100kΩ 100kΩ D3 B-DATA LATCH D2 D1 D0 8kΩ 8kΩ 8kΩ 8kΩ 8kΩ GND Figure 10. Internal Mux Impedance-Mode Data Test and Latch resistors with the CPU’s VID pins, each pin provides the low impedance needed for the mux to correctly interpret the Impedance mode setting. Unfortunately, the low resistances cause several mA quiescent currents for each of the CPU’s grounded VID pins. This quiescent current can be avoided by taking advantage of the fact that D0–D4 need only appear low impedance briefly, not necessarily on a continuous DC basis. Highimpedance pullups can be used if they are bypassed with a large enough capacitance to make them appear low impedance for the 4µs sampling interval. As noted in Figure 13, 4.7nF capacitors allow the inputs to appear low impedance even though they are pulled up with large-value resistors. Each sampling depletes some charge from the 4.7nF capacitors. A minimum interval of 2 R PULLUP 4.7nF is recommended between ZMODE samples. In some cases, it is desirable to determine the Impedance mode code during system boot so that sev- 20 3.0V TO 5.5V D4 100kΩ D3 ZMODE LOW VID = 01100 1.15V MAX1718T D2 100kΩ D1 D0 ZMODE ZMODE HIGH VID = 01010 1.25V ZMODE = HIGH = 1.25V ZMODE = LOW = 1.15V Figure 11. Using the Internal Mux with Hardwired Logic-Mode and Impedance-Mode DAC Codes ______________________________________________________________________________________ Notebook CPU Step-Down Controller MAX1718T 2.7V TO 5.5V 1kΩ 100kΩ D4 MAX1718T D3 D2 D1 D0 ZMODE 1kΩ 100kΩ 1kΩ ZMODE = HIGH = 1.25V ZMODE = LOW = 1.15V NOTE: USE PULLUP FOR LOGIC MODE 1, PULL-DOWN FOR LOGIC MODE 0. USE ≥100kΩ FOR IMPEDANCE MODE 1, ≤1kΩ FOR IMPEDANCE MODE 0. Figure 12. Using the Internal Mux with Both VID Codes Resistor Programmed eral processor types can be used without hardware modifications. Figure 14 shows one way to implement this function. The desired code is determined by the system BIOS and programmed into one register of the MAX1609 using the SMBus™ serial interface. The MAX1609’s other register is left in its power-up state (all outputs high impedance). When SMBSUS is low, the outputs are high impedance and do not affect the logicmode VID code setting. When SMBSUS is high, the programmed register is selected, and the MAX1609 forces a low impedance on the appropriate VID input pins. The ZMODE signal is delayed relative to the SMBSUS pin because the VID pins that are pulled low by the MAX1609 take significant time to rise when they are released. One additional benefit of using the MAX1609 for this application is that the application uses only five of the MAX1609’s high-voltage, open-drain outputs. The other three outputs can be used for other purposes. Output Voltage Transition Timing The MAX1718T is designed to perform output voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output volt- Table 5. DAC Mux Operation ZMODE SUS OUTPUT VOLTAGE DETERMINED BY GND GND Logic level of D0–D4 VCC GND Impedance of D0–D4 X VCC Logic levels of S0, S1 age level with the lowest possible peak currents for a given output capacitance. This makes the IC ideal for mobile CPUs. Mobile CPUs operate at multiple clock frequencies, which often require distinct VID settings. When transitioning from one clock frequency to the other, the CPU first goes into a low-power state, then the output voltage and clock frequency are changed. The change must be accomplished in a specified transition time or the system can halt. At the beginning of an output voltage transition, the MAX1718T blanks the VGATE output, preventing it from going low. VGATE remains blanked during the transition and is reenabled when the slew-rate controller has set the internal DAC to the final value and one additional SMBus is a trademark of Intel Corp. ______________________________________________________________________________________ 21 MAX1718T Notebook CPU Step-Down Controller 3.15V TO 5.5V *OPTIONAL 4.7nF 1MΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ D4 100kΩ D3 CPU MAX1718T D2 100kΩ D1 D0 ZMODE CPU VID = 01100 → 1.15V (ZMODE LOW) ZMODE HIGH VID = 01010 → 1.25V ZMODE = HIGH = 1.25V ZMODE = LOW = 1.15V *TO REDUCE QUIESCENT CURRENT, 1kΩ PULLUP RESISTORS CAN BE REPLACED BY 1MΩ RESISTORS WITH 4.7nF CAPACITORS IN PARALLEL. Figure 13. Using the Internal Mux with CPU Driving the Logic-Mode VID Code slew-rate clock period has passed. The slew-rate clock frequency (set by resistor R TIME ) must be set fast enough to ensure that the longest required transition is completed within the allowed interval. The output voltage transition is performed in 25mV steps, preceded by a 4µs delay and followed by one additional clock period. The total time for a transition depends on R TIME , the voltage difference, and the accuracy of the MAX1718T’s slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX1718T automatically controls the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ILIM. The transition time is given by: ⎡ 1 ⎛ VOLD - VNEW ⎞ ⎤ ≤ 4μs + ⎢ ⎜ ⎟⎥ ⎣ fSLEW ⎝ 25mV ⎠ ⎦ 22 where fSLEW = 150kHz 120kΩ / RTIME, VOLD is the original DAC setting, and VNEW is the new DAC setting. See Time Frequency Accuracy in the Electrical Characteristics table for fSLEW accuracy. The practical range of RTIME is 47kΩ to 470kΩ, corresponding to 2.6µs to 26µs per 25mV step. Although the DAC takes discrete 25mV steps, the output filter makes the transitions relatively smooth. The average inductor current required to make an output voltage transition is: IL ≅ COUT 25mV fSLEW Output Overvoltage Protection The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The output voltage is continuously monitored for overvoltage. If the output is more than 2V, OVP is triggered and the circuit shuts down. The DL low-side gate-driver output is then latched high until SKP/SDN is toggled or VCC power is cycled below 1V. This action turns on the synchronous-rectifier MOSFET with 100% duty and, in turn, rapidly discharges the output filter capacitor and ______________________________________________________________________________________ Notebook CPU Step-Down Controller MAX1718T 3.3V R R R R R = 100kΩ R VID4 R VID3 R CPU VID2 MAX1718T R VID1 R VID0 ZMODE 3.3V 3.3kΩ MAX1609 1nF ADD0 ADDRESS ADD1 0 1 1 0 1 1 1 DATA SMBUS CLOCK 0 1 1 SMBSUS GMUXSEL Figure 14. Using the ZMODE Multiplexer forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. DL is also kept high continuously when VCC UVLO is active, as well as in shutdown mode (Table 6). Overvoltage protection can be defeated with a logic high on OVP or through the NO FAULT test mode (see the NO FAULT Test Mode section). Output Undervoltage Shutdown The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX1718T output voltage is under 70% of the nominal value, the PWM is latched off and does not restart until VCC power is cycled or SKP/SDN is toggled. To allow startup, UVP is ignored during the undervoltage fault-blanking time (the first 256 cycles of the slew rate after startup). UVP can be defeated through the NO FAULT test mode (see the NO FAULT Test Mode section). NO FAULT Test Mode The over/undervoltage protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a test mode is provided to disable the OVP, UVP, and thermal shutdown features, and clear the fault latch if it has been ______________________________________________________________________________________ 23 MAX1718T Notebook CPU Step-Down Controller Table 6. Operating Mode Truth Table SKP/SDN DL MODE GND High Shutdown 12V to 15V Switching No fault Test mode with faults disabled and fault latches cleared, including thermal shutdown. Otherwise, normal operation, with automatic PWM/PFM switchover for pulse skipping at light loads. Open Switching Run (PWM, low noise) Low-noise operation with no automatic switchover. Fixed-frequency PWM action is forced regardless of load. Inductor current reverses at light-load levels. VCC Switching Run (PFM/PWM) Operation with automatic PWM/PFM switchover for pulse skipping at light loads. VCC or open High Fault set. The PWM operates as if SKP/SDN were high (SKIP mode). The NO FAULT test mode is entered by forcing 12V to 15V on SKP/SDN. Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case high-AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. 2) Maximum Load Current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) 80%. 3) Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are pro24 COMMENT Low-power shutdown state. DL is forced to VDD, enforcing OVP. ICC + IDD = 2µA (typ). Fault latch has been set by OVP, UVP, or thermal shutdown. Device remains in FAULT mode until VCC power is cycled or SKP/SDN is forced low. portional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. 4) Inductor Operating Point. This choice provides tradeoffs between size and efficiency. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The MAX1718T’s pulse-skipping algorithm initiates skip mode at the critical conduction point. So, the inductor operating point also determines the loadcurrent value at which PFM/PWM switchover occurs. The optimum point is usually found between 20% and 50% ripple current. 5) The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: ______________________________________________________________________________________ Notebook CPU Step-Down Controller VSAG = ⎡ ⎛ V − VOUT ⎞ ⎤ 2 × COUT × VOUT ⎢K ⎜ IN − t OFF(MIN) ⎥ ⎟ VIN ⎠ ⎢⎣ ⎝ ⎥⎦ where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics tables) and K is from Table 2. Inductor Selection The switching frequency and operating point (% ripple or LIR) determine the inductor value as follows: L = ( VOUT VIN − VOUT ) VIN × fSW × LIR × ILOAD(MAX) Example: ILOAD(MAX) = 19A, VIN = 7V, VOUT = 1.25V, fSW = 300kHz, 30% ripple current or LIR = 0.30: VSOAR ≈ L × I PEAK 2 2 × C × VOUT Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + (LIR / 2) ILOAD(MAX) Setting the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current; therefore: ILIMIT(LOW) > ILOAD(MAX) - (LIR / 2) ILOAD(MAX) where I LIMIT(LOW) equals the minimum current-limit threshold voltage divided by the RDS(ON) of Q2. For the MAX1718T Figure 1 circuit, the minimum current-limit threshold with VILIM = 105mV is about 95mV. Use the worst-case maximum value for RDS(ON) from the MOSFET Q2 data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each °C of temperature rise. Examining the Figure 1 example with a Q2 maximum RDS(ON) = 3.8mΩ at TJ = +25°C and 5.7mΩ at TJ = +125°C reveals the following: ILIMIT(LOW) = 95mV / 5.7mΩ = 16.7A and the required valley current limit is: ILIMIT(LOW) > 19A - (0.30 / 2) 19A = 16.2A Since 16.7A is greater than the required 16.2A, the circuit can deliver the full-rated 19A. When delivering 19A of output current, the worst-case power dissipation of Q2 is 1.95W. With a thermal resistance of +60°C/W and each MOSFET dissipating 0.98W, the temperature rise of the MOSFETs is +60°C/W 0.98W = +58°C, and the maximum ambient temperature is +125°C - +58°C = +67°C. To operate at a higher ambient temperature, choose lower RDS(ON) MOSFETs or reduce the thermal resistance. Raising the current-limit threshold allows for operation with a higher MOSFET junction temperature. Connect ILIM to VCC for a default 100mV current-limit threshold. For an adjustable threshold, connect a resistordivider from REF to GND, with ILIM connected to the center tap. The external adjustment range of 0.5V to 3.0V corresponds to a current-limit threshold of 50mV to 300mV. When adjusting the current limit, use 1% tolerance resistors and a 10µA divider current to prevent a significant increase of errors in the current-limit tolerance. Output Capacitor Selection The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and loadtransient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the OVP circuit. In CPU VCORE converters and other applications where the output is subject to violent load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR ≤ VSTEP / ILOAD(MAX) The actual microfarad capacitance value required often relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, and other electrolytics). When using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent VSAG ______________________________________________________________________________________ 25 MAX1718T ⎛ V ⎞ (I LOAD1 − I LOAD2 ) × L ⎜ K OUT + t OFF(MIN) ⎟ VIN ⎝ ⎠ 2 MAX1718T Notebook CPU Step-Down Controller and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG equation in the Design Procedure section). The amount of overshoot due to stored inductor energy can be calculated as: L × I PEAK 2 VSOAR ≈ 2 × C × VOUT where IPEAK is the peak inductor current. Output Capacitor Stability Considerations Stability is determined by the value of the ESR zero relative to the switching frequency. The voltage-positioned circuit in this data sheet has the ESR zero frequency lowered due to the external resistor in series with the output capacitor ESR, guaranteeing stability. For a voltage-positioned circuit, the minimum ESR requirement of the output capacitor is reduced by the voltage-positioning resistor value. The boundary condition of instability is given by the following equation: (RESR + RDROOP) COUT ≥ 1 / (2 fSW) where RDROOP is the effective value of the voltage-positioning resistor (Figure 1, R8). For good phase margin, increase the equivalent RC time constant by a factor of two. The standard application circuit (Figure 1) operating at 300kHz with COUT = 1320µF, RESR = 2.5mΩ, and RDROOP = 5mΩ easily meets this requirement. In some applications, the COUT and RDROOP values are sufficient to guarantee stability even if RESR = 0. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation: I RMS = I LOAD VOUT (VIN - VOUT ) VIN For most applications, nontantalum chemistries (ceramic or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a switch or a connector in series with the battery. If the 26 MAX1718T is operated as the second stage of a twostage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity. Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability (>12A) when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of Q1. Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of Q1. If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET (Q2) that has the lowest possible RDS(ON), comes in a moderate-sized package (i.e., two or more 8-pin SOs, DPAKs, or D2PAKs), and is reasonably priced. Ensure that the MAX1718T DL gate driver can drive Q2; in other words, check that the dv/dt caused by Q1 turning on does not pull up the Q2 gate due to drain-to-gate capacitance, causing crossconduction problems. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the buck topology. MOSFET Power Dissipation The high-side MOSFET power dissipation due to resistance is: V PD (Q1 Re sistive) = OUT × I LOAD2 × RDS(ON) VIN Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages ______________________________________________________________________________________ Notebook CPU Step-Down Controller Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation and temperature measurements: PD(Q1 Switching) = CRSS × VIN(MAX)2 × fSW × I LOAD IGATE where CRSS is the reverse transfer capacitance of Q1 and IGATE is the peak gate-drive source/sink current (2A typ). For the low-side MOSFET (Q2), the worst-case power dissipation always occurs at maximum battery voltage: ⎛ VOUT ⎞ 2 PD (Q2) = ⎜1 − ⎟ I LOAD × RDS(ON) V IN(MAX) ⎠ ⎝ For both Q1 and Q2, note the MOSFET’s maximum junction temperature and the thermal resistance that is realistically achieved with the device packaging and your thermal environment to avoid overheating. The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can “overdesign” the circuit to tolerate: Applications Information Voltage Positioning Powering new mobile processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher allows a larger step down when the output current suddenly increases, and regulating at the lower output voltage under load allows a larger step up when the output current suddenly decreases. Allowing a larger step size means that the output capacitance can be reduced and the capacitor’s ESR can be increased. Adding a series output resistor positions the full-load output voltage below the actual DAC programmed voltage. Connect FB directly to the inductor side of the voltagepositioning resistor (R8, 4mΩ). The other side of the voltage-positioning resistor should be connected directly to the output filter capacitor with a short, wide PCB trace. With a 20A full-load current, R8 causes an 80mV drop. This 80mV is a -6.4% droop. An additional benefit of voltage positioning is reduced power consumption at high load currents. Because the output voltage is lower under load, the CPU draws less current. The result is lower power dissipation in the CPU, although some extra power is dissipated in R8. For a nominal 1.25V, 20A output, reducing the output voltage 6.4% gives an output voltage of 1.17V and an output current of 18.7A. Given these values, CPU power consumption is reduced from 25W to 21.9W. The additional power consumption of R8 is: 4mΩ 18.7A2 = 1.4W And the overall power savings is as follows: ILOAD = ILIMIT(HIGH) + (LIR / 2) ILOAD(MAX) 25 - (21.9 + 1.4) = 1.7W where I LIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. This means that the MOSFETs must be very well heatsinked. If short-circuit protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses. Choose a Schottky diode (D1) having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency is not critical. In effect, 3W of CPU dissipation is saved, and the power supply dissipates some of the power savings, but both the net savings and the transfer of dissipation away from the hot CPU are beneficial. Reduced-Power-Dissipation Voltage Positioning A key benefit of voltage positioning is reduced power dissipation, especially at heavy loads. In the standard application circuit (Figure 1), voltage positioning is accomplished using a droop resistor (R8), which can dissipate over 1W. Although the power savings in the processor is much greater than the dissipation in the resistor, 1W of dissipation is still far from ideal. ______________________________________________________________________________________ 27 MAX1718T becomes extraordinarily hot when subjected to VIN(MAX), reconsider your choice of MOSFET. MAX1718T Notebook CPU Step-Down Controller The resistor is a necessary component because accurate voltage positioning depends on an accurate current-sense element. But it is not necessary to drop the entire positioning voltage across this resistor. The circuit of Figure 15 uses an external op amp to add gain to R8’s voltage signal, allowing the resistor value and power dissipation to be divided by the gain factor. The recommended range for the gain is up to about 4, with preferred practical values around 1.5–3. There are several difficulties with high gains. If high gain is used, the sense-resistor value is very small (<1mΩ). The sense signal is also small, potentially causing noise and stability problems. Also, output voltage and positioning accuracy are essential. A smaller sense signal reduces accuracy, as does any op-amp input voltage offset, which is increased by the gain factor. The op-amp output directly drives FB. To ensure stability, the output voltage ripple and the ripple signal across R8 must be delivered with good fidelity. To preserve higher harmonics in the ripple signal, the circuit bandwidth should be approximately 10 times the switching frequency. Besides lowering power dissipation, the gain stage provides another benefit; it eases the task of providing the required positioning slope, using available discrete values for R8. A lower value resistor can be used and the gain adjusted to deliver the desired slope. Sometimes the desired slope is not well known before the final PCB is evaluated. A good practice is to adjust the final gain to deliver the correct voltage slope at the processor pins, adjusting for the actual copper losses in the supply and ground paths. This does not remove the requirement to minimize copper losses because they vary with temperature and PCB production lot. It does, however, provide an easy, practical way to account for their typical expected voltage drops. Replacing the droop resistor with a lower value resistor and a gain stage does not affect the MAX1718T stability criteria. The IC cannot distinguish one from the other, as long as the required signal integrity is maintained. R8’s effective value can be used to guarantee stability with extremely low-ESR (ceramic) output capacitors (see the Output Capacitor Stability Considerations section). The effective value is the resistor value that would result in the same signal delivered to the MAX1718T’s FB pin, or R8 times the op-amp circuit’s gain. Although the op amp should be placed near R8 to minimize input noise pickup, power it from the MAX1718T’s quiet VCC supply and analog ground to prevent other noise problems. 28 DH R8 VOUT 1.25V, 19A VCC DL 510Ω MAX1718T FB MAX4322 A=2 R5 1kΩ R6 1kΩ Figure 15. Lowering Voltage-Positioning Power Dissipation High-Accuracy Current Limit The MAX1718T’s integrated current limit uses the synchronous rectifier’s RDS(ON) for its current-sense element. This dependence on a poorly specified resistance with high temperature variation means that the integrated current limit is useful mainly in high-overload and short-circuit conditions. A moderate overload may be tolerated indefinitely. This arrangement is tolerable because there are other ways to detect overload conditions and take appropriate action. For example, if the CPU draws excessive current (but not enough to activate the current limit) the CPU heats up, and eventually the system takes notice and shuts down. While this approach is usually acceptable, it is far from optimal. An inaccurate current limit causes component specification difficulties. What values should be used for inductor saturation ratings, MOSFET peak current requirements, and power dissipation requirements? An accurate current limit makes these issues more manageable. The circuit of Figure 16 uses an external op amp, together with the voltage-positioning resistor (R8) to implement an accurate inductor current limit. A voltage-divider from the positive side of R8 creates a threshold several mVs below the output. When the voltage drop across R8 exceeds the threshold, current limiting occurs. The op amp causes current limiting by lowering the voltage on the ILIM pin. This lowers the current-limit threshold of the IC’s internal current-limit circuit, which uses the MOSFET RDS(ON) as usual. The op-amp output swing has the ability to adjust the IC’s internal valley current limit from a value much higher than ever needed (given the MOSFET’s RRD(ON)) to a ______________________________________________________________________________________ Notebook CPU Step-Down Controller The bandwidth of the ILIM pin is not high, so the speed of the op amp is not critical. Any op amp or comparator could be acceptable, as long as its input offset does not degrade current-limit accuracy excessively, has input common-mode range to ground, and has Rail-toRail® output swing. Because the bandwidth is low, the circuit responds to the average inductor current rather than the peak or valley current, eliminating the current limit’s dependence on inductor ripple current. Similar to a foldback current limit, this circuit must be carefully designed to guarantee startup. The op amp must be incapable of setting the current limit to zero or else the power supply may be unable to start. The three-way divider from REF to ground to the op-amp output allows the op amp to vary the MAX1718T’s internal current-limit threshold from 21mV (severely limiting current) to 182mV (more than guaranteeing the maximum required output current). These divider resistors should be chosen with the required current and the synchronous rectifier’s RRD(ON) in mind to ensure that the op-amp adjustment range is high enough to guarantee the required output current. The voltage at the ILIM pin is given by: VILIM = [(R12 × R13 × VREF ) + (R13 × R14 × VCOMP )] [(R12 × R14) + (R12 × R13) + (R13 × R14)] where VCOMP is the voltage at the output of the comparator. The minimum VILIM is calculated when VCOMP is at the VOL of the comparator. The maximum VILIM is calculated when VCOMP = VOH at the minimum VCC. The valley current-limit threshold is set at 10% of the voltage VILIM. C13 should be picked to give approximately 10µs time constant at the ILIM input. The actual threshold at which the op amp begins to limit current is determined by R8 and the R10/R11 divider values and is very easy to set. Ideally, IOUT(MAX) R8 = VFB R10 / (R10 + R11). In practice, some margin must be added for resistor accuracy, opamp input offset, and general safety. With the op amp shown and ±1% resistors, 10% margin is adequate. An additional benefit of this circuit is that the currentlimit value is proportional to the output voltage setting (VFB). When the output voltage setting is lowered, the current limit automatically adjusts to a more appropriate level, providing additional protection without compromising performance since the reduction of the required load current is greater than that of the output voltage setting. In some cases, the current required to slew the R8 4mΩ DH VOUT 1.25V, 19A DL MAX1718T FB VCC R10 1.5kΩ REF R14 100kΩ R12 30kΩ ILIM 1nF MAX4322 R13 20kΩ R11 20kΩ Figure 16. Improving Current-Limit Accuracy output capacitor may be large enough to require the current limit to be increased beyond what is necessary to support the load. This circuit is completely compatible with the circuit of Figure 15. If the two circuits are used together, the MAX4326 dual op amp in a µMAX package can replace the two single devices, saving space and cost. If both are used, the reduced R8 value makes the op-amp input offset more significant. Additional margin might be needed, depending on the magnitude of R8’s reduction. Although the op amp should be placed near R8 to minimize input noise pickup, power it from the MAX1718T’s quiet VCC supply and analog ground to prevent other noise problems. Using Skip Mode During Suspend (SKP/SDN = VCC) Typically, for the MAX1718T’s intended application, the minimum output currents are too high to benefit from pulse-skipping operation in all active CPU modes. Furthermore, skip mode can be a hindrance to properly executing downward output voltage transitions (see the Forced-PWM Mode section). However, processor suspend currents can be low enough that skip mode operation provides a real benefit. In the circuit of Figure 17, SKP/SDN remains biased at 2V in every state except suspend and shutdown. In addition, upon entering suspend (SUS going high), the pin remains at 2V for about 200µs before it eventually Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ______________________________________________________________________________________ 29 MAX1718T value much lower than required to support a normal load. MAX1718T Notebook CPU Step-Down Controller goes high. This causes the MAX1718T to remain in PWM mode long enough to correctly complete the negative output voltage transition to the suspend state voltage. When SKP/SDN goes high, the MAX1718T enters its low-quiescent-current skip mode. Dropout Performance The output voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot (375ns max at 1000kHz). For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 2). Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). The ratio h = ΔIUP/ΔIDOWN is an indicator of ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but this may be adjusted up or down to allow tradeoffs between V SAG , output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VIN(MIN) = (VOUT + VDROP1) ⎛ TOFF(MIN ) x h ⎞ 1- ⎜ ⎟ K ⎝ ⎠ + VDROP2 - VDROP1 where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths, respectively (see the On-Time One-Shot (TON) section), TOFF(MIN) is from the Electrical Characteristics tables, and K is taken from Table 2. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipat- 30 ed, calculate VSAG to be sure of adequate transient response. Dropout Design Example: VOUT = 1.6V fsw = 550kHz K = 1.8µs, worst-case K = 1.58µs TOFF(MIN) = 500ns VDROP1 = VDROP2 = 100mV h = 1.5 VIN(MIN) = (1.6V + 0.1V) / (1-0.5µs 1.5/1.58µs) + 0.1V - 0.1V = 3.2V Calculating again with h = 1 gives the absolute limit of dropout: VIN(MIN) = (1.6V + 0.1V) / (1-1.0 0.5µs/1.58µs) - 0.1V + 0.1V = 2.5V Therefore, VIN must be greater than 2.5V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.2V. Adjusting VOUT with a Resistor-Divider The output voltage can be adjusted with a resistordivider rather than the DAC if desired (Figure 18). The drawback is that the on-time does not automatically receive correct compensation for changing output voltage levels. This can result in variable switching frequency as the resistor ratio is changed, and/or excessive switching frequency. The equation for adjusting the output voltage is: ⎛ R ⎞ VOUT = VFB ⎜1 + 1 ⎟ R2 ⎠ ⎝ where V FB is the currently selected DAC value. In resistor-adjusted circuits, the DAC code should be set as close as possible to the actual output voltage in order to minimize the shift in switching frequency. One-Stage (Battery Input) vs. Two-Stage (5V Input) Applications The MAX1718T can be used with a direct battery connection (one stage) or can obtain power from a regulated 5V supply (two stage). Each approach has advantages, and careful consideration should go into the selection of the final design. The one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5V supply. The transient response of the single stage is better due to the ability to ramp up the inductor current faster. The total efficiency of a single stage is better than the two-stage approach. ______________________________________________________________________________________ Notebook CPU Step-Down Controller MAX1718T VCC VBATT DH 120kΩ TO SKP/SDN VCC VOUT 80kΩ DL TO SUS MAX1718T 30kΩ R1 0.01μF FB SHUTDOWN 3.3V SUS ~200μs R2 ~200μs 0V 5V SKP/SDN 2.0V Figure 17. Using Skip Mode During Suspend (SKP/ SDN = VCC) The two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipation. The power supply can be placed closer to the CPU for better regulation and lower I2R losses from PCB traces. Although the two-stage design has worse transient response than the single stage, this can be offset by the use of a voltage-positioned converter. Ceramic Output Capacitor Applications Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. They are also expensive and brittle, and their ultra-low ESR characteristic can result in excessively high ESR zero frequencies (affecting stability in nonvoltage-positioned circuits). In addition, their relatively low capacitance value can cause output overshoot when going abruptly from full-load to no-load conditions, unless the inductor value can be made small (high-switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the inductor. In some cases, there may be no room for electrolytics, necessitating a ceramic-only DC-to-DC design. The MAX1718T can take full advantage of the small size and low ESR of ceramic output capacitors in a voltage-positioned circuit. Adding the positioning resistor increases the ripple at FB, lowering the effective ESR zero frequency of the ceramic output capacitor. Output overshoot (VSOAR) determines the minimum output capacitance requirement (see the Output Capacitor Selection section). Often the switching frequency is increased to 550kHz or 1000kHz, and the inductor value is reduced to minimize the energy transferred from VOUT = VFB ✕ 1 + R1 R2 ( ) Figure 18. Adjusting VOUT with a Resistor-Divider inductor to capacitor during load-step recovery. The efficiency penalty for operating at 550kHz is about 2% to 3% and about 5% at 1000kHz when compared to the 300kHz voltage-positioned circuit, primarily due to the high-side MOSFET switching losses. PCB Layout Guidelines Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 19). If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PCB layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. 2) All analog grounding is done to a separate solid copper plane, which connects to the MAX1718T at the GND pin. This includes the V CC , REF, and CC capacitors, the TIME resistor, as well as any other resistor-dividers. 3) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. ______________________________________________________________________________________ 31 MAX1718T Notebook CPU Step-Down Controller 4) LX and GND connections to Q2 for current limiting must be made using Kelvin-sense connections to guarantee the current-limit accuracy. With 8-pin SO MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while connecting GND and LX inside (underneath) the 8-pin SO package. 5) When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor. 6) Ensure the FB connection to the output is short and direct. In voltage-positioned circuits, the FB connection is at the junction of the inductor and the positioning resistor. 7) Route high-speed switching nodes away from sensitive analog areas (CC, REF, ILIM). Make all pin-strap control input connections (SKP/SDN, ILIM, etc.) to analog ground or VCC rather than power ground or VDD. Layout Procedure 1) Place the power components first, with ground terminals adjacent (Q2 source, CIN-, COUT-, D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to MOSFET Q2, preferably on the back side opposite Q2 in order to keep LX-GND current-sense lines and the DL drive line short and wide. The DL gate trace must be short and wide, measuring 10 to 20 squares (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-to-DC controller ground connections as shown in Figure 19. This diagram can be viewed as having three separate ground planes: output ground, where all the high-power components go; the GND plane, where the GND pin and VDD bypass capacitors go; and an analog ground plane where sensitive analog components go. The analog ground plane and GND plane must meet only at a single point directly beneath the IC. These two planes are then connected to the high-power output ground with a short connection from GND to the source of the lowside MOSFET Q2 (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close to the CPU as is practical. Pin Configuration TOP VIEW V+ 1 28 DH SKP/SDN 2 27 LX TIME 3 26 BST FB 4 25 D0 NEG 5 CC 6 24 D1 MAX1718T 23 D2 S0 7 22 D3 S1 8 21 D4 VCC 9 20 OVP TON 10 19 ZMODE REF 11 18 SUS ILIM 12 17 VDD POS 13 16 DL VGATE 14 15 GND QSOP 32 ______________________________________________________________________________________ Notebook CPU Step-Down Controller MAX1718T VBATT GND IN ALL ANALOG GROUNDS CONNECT TO LOCAL PLANE ONLY VIA TO GND NEAR Q2 SOURCE MAX1718T VCC CIN GND OUT CC Q1 REF VDD D1 COUT Q2 VOUT GND VIA TO SOURCE OF Q2 R6 CONNECT LOCAL ANALOG GROUND PLANE DIRECTLY TO GND FROM THE SIDE OPPOSITE THE VDD CAPACITOR GND TO AVOID VDD GROUND CURRENTS FROM FLOWING IN THE ANALOG GROUND PLANE. VIA TO FB AND FBS L1 VIA TO LX NOTE: “STAR” GROUND IS USED. D1 IS DIRECTLY ACROSS Q2. INDUCTOR DISCHARGE PATH HAS LOW-DC RESISTANCE Figure 19. Power-Stage PCB Layout Example Chip Information TRANSISTOR COUNT: 7190 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 28 QSOP E28-1 21-0055 Note: The MAX1718T does not have a heat slug. ______________________________________________________________________________________ 33 MAX1718T Notebook CPU Step-Down Controller Revision History REVISION REVISION NUMBER DATE DESCRIPTION PAGES CHANGED 0 11/02 Initial release — 1 10/08 Removal of patent pending on page 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 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