SC2544
High Performance Wide Input Range
Dual Synchronous Buck Controller
POWER MANAGEMENT
Description
Features
The SC2544 is a high performance dual PWM controller.
It is designed to convert a wide ranged input voltage down
to two independent output rails. The PWM operations of
the two channels are 180 degree out of phase which
can greatly reduce the size and the cost of the input
capacitors. Synchronous Buck PWM topology and voltage mode control allow high efficiency operation, fast
transient responses, and flexible component selection
for easy designs. A 10V internal linear regulator provides the bias for the controller, and this voltage is optimized for gate drivers to deliver high efficiency. The power
sequencing is fully supported including independent start
up, and power good output. In the shut down mode the
controller only draws 100nA from the supply. The controller also offers full protection features for the conditions of under voltage, over voltage, and the over current.
There is no need for a current sensing resistor because
the MOSFET on resistance is used for the sensing
element. The switching frequency is adjustable from 100
kHz to 300 kHz. Two packages TSSOP-24 and MLPQ-24
are offered.
Independent dual-outputs
Wide input voltage range: 4.5V~28V
Adjustable output voltage down to 0.75V
Sequential and ratiometric start-up
Power good output
Synchronous Buck topology with voltage mode
control
Out of phase operation to reduce cost of input
capacitor
10V internal regulator for gate driver to deliver high
efficiency
Programmable switching frequency:
100kHz~300kHz
Full protection: UVLO, OVP and programmable
OCP
No need for current sense resistor
Low shutdown current (100nA typical)
24 lead TSSOP and MLPQ packages
Fully WEEE and RoHS Compliant
Applications
Typical Application Circuit
Systems with 4.5V~28V input
LCDTV and PDPTV
Network and telecom systems
Portable devices
SC2544
VIN+
VO1
1
VCC
2
3
ENABLE
4
FB1
5
6
VIN+
7
8
VO1
9
10
11
FB1
12
VIN
AGND
VCC
ROSC
PWRGD
EN
FB2
FB1
ERROUT1
ERROUT2
SS2
SS1
ILIM1
ILIM2
BST1
BST2
DRVH2
DRVH1
PHASE2
PHASE1
DRVL1
DRVL2
PGND
PVCC
24
23
22
PWGRD
21
FB2
20
19
VIN+
18
17
16
VO2
15
14
13
VCC
FB2
Pinout shown as TSSOP-24.
Revision: August 10, 2005
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SC2544
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction.
Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
U nits
BST1, BST2 to PGND
V b st
38
V
VIN to PGND
Vin
28
V
ILIM1, ILIM2 and EN to PGND
VIN
V
VC C and PVC C to PGND
14
V
+/- 0.3
V
-0.3 to 14
V
-0.3 to VC C
V
-3
V
-0.3 to VC C
V
PGND to AGND
BST1 to PH1, BST2 to PH2, D RVH1 to PH1, D RVH2 to PH2
D RVL1, D RVL2 to PGND
PHASE, D RVL to AGND pulse (100nS), peak voltage
All Other Pi ns to AGND
TSTG
-60 to +150
o
C
TJ
-40 to +150
o
C
TLEAD
260
o
C
Thermal Resi stance Juncti on to C ase
TSSOP-24
MLP-24
θJC
23
2
o
C /W
Thermal Resi stance Juncti on to Ambi ent
TSSOP-24
MLP-24
θJA
78
25
o
C /W
Storage Temperature Range
Juncti on Temperature
Lead Temperature (Solderi ng) 10 Sec for TSSOP-24
Lead Temperature (IR Reflow) for MLPQ-24
Note: This device is ESD sensitive. Use of standard ESD handling precautions is required.
Electrical Characteristics
o
Unless specified: TA = 25 C, VIN=16V, Fs=200KHz .
Parameter
Test C onditions
Min
Typ
Max
U nit
4.5
V
U ndervoltage Lockout
Start Threshold
Vcc ri si ng
UVLO Hysteresi s
Vcc falli ng
200
SS1/SS2/EN =Hi gh, FS=200kHz
6.0
VIN > 12V
10
V
I_load=0~20mA
2
%
Vi n=12~24V
2
%
200KHz, 1nF on HG, 1nF on LG
14
mA
EN=low
0.1
Li ne Regulati on
5V<Vi n <28V
0.5
%
Load Regulati on
0A<load current <10A
0.5
%
mV
Pow er Supply
Operati ng C urrent (I IN-IPVCC)
Vcc Regulated
Vcc Load Regulati on Level
Vcc Li ne Regulati on
PVcc Operati ng C urrent
D i sable Qui escent C urrent
10
mA
10
uA
Main Sw itcher output
Output Voltage Accuracy
2005 Semtech Corp.
Wi thout feedback attenuati on ,
TA = -40 oC to +85 oC
2
0.735
0.750
0.765
V
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SC2544
POWER MANAGEMENT
Electrical Characteristics
Unless specified: T = 25 C, V =16V, Fs=200KHz
(Cont.)
o
A
IIN
Parameter
Test Conditions
Min
Typ
Max
Unit
2
V
ENABLE
EN Ramp Up Threshold Voltage
EN Ramp Down Threshold Voltage
0.6
V
Soft Start
Soft Start Charge Current
84
uA
Soft Start Discharge Current
15
uA
0.65
V
Threshold Voltage for DRVL
Out of Tri-State
Pull below this level, turning on DRVL
(Turn on low side MOSFET)
Error Amplifier
TA = -40oC to +85oC
Voltage Feedback Reference
0.735
0.750
Input Bias Current
0.765
V
2
uA
70
dB
Unity Gain Bandwidth (1)
3
MHz
Output Source/Sink Current
1
mA
10
V/uS
75
nS
Open Loop Gain
Slew Rate
(1)
100pF capacitive loading
(1)
PWM Comparator to Output Delay
(1)
Oscillator
Frequency Range per phase
Oscillator Frequency per phase
100
Rosc=73K OHM
175
210
300
kHz
245
kHz
Oscillator Ramp Peak Voltage
2.3
V
Oscillator Ramp Valley Voltage
1
V
Current Limit
ILIM Source Current
9
ILIM Offset Voltage
10
11
uA
2
mV
Duty Cycle
PWM 1 & 2 Maximum Duty Cycle
Rosc = 73K OHM
90
%
PWM 1 & 2 Minimum Duty Cycle
Rosc = 73K OHM
0
%
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SC2544
POWER MANAGEMENT
Pin Descriptions for SC2544TSTRT (TSSOP)
Pin #
Pin Name
1
VIN
2
VC C
3
EN
When EN pin is low all outputs are disabled. Typical shutdown current is l00nA.
4
FB 1
Negative input of the error amplifier for output1.
5
ERROUT1
6
SS1
An external capacitor connected from this pin to AGND sets the soft-start time.
Disable output1 by pulling this pin below 1V.
7
ILIM1
An external resistor connected from this pin to PHASE1 sets the over current shutdown trip
point.
8
BST1
Boost capacitor connection for output1 high side gate drive.
Connect an external capacitor as shown in the typical application circuit.
9
DRVH1
10
PHASE1
11
DRVL1
Low side gate drive for output 1.
12
PGND
Power ground of low-side drivers.
13
PVC C
Supply voltage for low-side gate drivers.
14
DRVL2
Low-side gate drive for output 2.
15
PHASE2
16
DRVH2
17
BST2
Boost capacitor connection for OUTPUT2 high side gate drive.
Connect an external capacitor as shown in the typical application circuit.
18
ILIM 2
An external resistor connected from this pin to PHASE2 sets the over current shutdown trip
point.
19
SS2
20
ERROUT2
21
FB 2
22
PWRGD
23
ROSC
A resistor from this pin to AGND sets oscillator frequency.
24
AGND
Analog signal ground. Star connected to the system ground plane.
2005 Semtech Corp.
Pin Function
Input supply voltage. The range is from 4.5V to 28V.
10V regulator output. Supply voltage for the gate drivers. Connect to VIN pin when Vin<10V.
Error amplifier output for buck converter1.
Gate drive for the high side MOSFET of output1. 180 degrees out of phase with DRVH2.
Phase node for output 1.
Phase node for output 2.
Gate drive for the high side MOSFET of OUTPUT2. 180 degrees out of phase with DRVH1.
An external capacitor connected from this pin to AGND sets the soft-start time.
Disable output1 by pulling this pin below 1V.
Error amplifier output for buck converter2.
Negative input of the error amplifier of output2.
Open collector output. It is internally pulled low when either output is below the power good
threshold level.
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SC2544
POWER MANAGEMENT
Pin Descriptions for SC2544MLTRT (MLPQ)
Pin #
Pin Name
1
FB 1
2
ERROUT1
3
SS1
An external capacitor connected from this pin to AGND sets the soft-start time.
Disable output1 by pulling this pin below 1V.
4
ILIM1
An external resistor connected from this pin to PHASE1 sets the over current shutdown trip
point.
5
BST1
Boost capacitor connection for output1 high side gate drive.
Connect an external capacitor as shown in the typical application circuit.
6
DRVH1
7
PHASE1
8
DRVL1
Low side gate drive for output 1.
9
PGND
Power ground of low-side drivers.
10
PVC C
Supply voltage for low-side gate drivers.
11
DRVL2
Low-side gate drive for output 2.
12
PHASE2
13
DRVH2
14
BST2
Boost capacitor connection for output2 high side gate drive.
Connect an external capacitor as shown in the typical application circuit.
15
ILIM2
An external resistor connected from this pin to PHASE2 sets the over current shutdown trip
point.
16
SS2
An external capacitor connected from this pin to AGND sets the soft-start time.
Disable output1 by pulling this pin below 1V.
17
ERROUT2
18
FB 2
19
PWRGD
20
ROSC
A resistor from this pin to AGND sets oscillator frequency.
21
AGND
Analog signal ground. Star connected to the system ground plane.
22
VIN
23
VC C
24
EN
2005 Semtech Corp.
Pin Function
Negative input of the error amplifier for output1.
Error amplifier output for buck converter1.
Gate drive for the high side MOSFET of output1. 180 degrees out of phase with DRVH2.
Phase node for output 1.
Phase node for output 2.
Gate drive for the high side MOSFET of output2. 180 degrees out of phase with DRVH1.
Error amplifier output for buck converter2.
Negative input of the error amplifier of output2.
Open collector output. It is internally pulled low when either output is below the power good
threshold level.
Input supply voltage. The range is from 4.5V to 28V.
10V regulator output. Supply voltage for the gate drivers. Connect to VIN pin when Vin<10V.
When EN pin is low all outputs are disabled. Typical shutdown current is 100nA.
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SC2544
POWER MANAGEMENT
Block Diagram (One PWM channel
shown)
PVCC
BST1
Protect 1
DRVH1
PHASE1
Ramp1
ROSC
PHASE1
PVCC
+
Oscillator
Ramp
generator
PVCC
PWM
S
-
DRVL1
Q
CLK1
R
Protect 1
ERROUT1
FB1
FB1
-
+
SS1
E/A
0.75V
+
0.75V
OUT
OUT
OUT
VCC
R
+
-
3R
S
R
/Q
Protect 1
10u A
UVLO
OCP
OUT
VCC
+
VCC
+
OVP
VIN
EN
ON/OFF
VCC
0.89V
0.75V
Band
Gap 1
10V
LDO
Band
Gap 2
UVLO
PWRGD
0.75V
0.675V
FB1
FB2
AGND
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FB1
OUT
-
ENABLE
ILIM1
-
7
+
-
OUT
OVP
OCP
-
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SC2544
POWER MANAGEMENT
Applications Information
Start-up
Overview
The SC2544 is a constant frequency 2-phase voltage
mode step-down PWM switching controller driving all Nchannel MOSFETs. The two channels of the controller
operate at 180 degree out of phase from each other.
Since input currents are interleaved in a two-phase
converter, input ripple current is lower and smaller input
capacitance can be used for filtering. Also, with lower
inductor current and smaller inductor ripple current per
phase, overall I2 R losses are reduced.
During start-up, the reference voltage of the error
amplifier equals 30% of the voltage on Css (soft-start
capacitor) which is connected between the SS pin and
ground. When the controller is enabled (by pulling EN
pin high), one internal 84uA current source, ISS, (soft
start current) will charge the soft-start capacitor
gradually. The PWM output starts pulsing when the
soft start voltage reaches 1V.
This soft start scheme will ensure the duty cycle to
increase slowly, therefore limiting the charging current
into the output capacitor and also ensuring the
inductor does not saturate. The soft start capacitor
will eventually be charged up to 2.5V.
The soft-start sequence is initiated when EN pin is high
and Vcc >4.5V or during recovery from a fault condition
( OCP, OVP, or UVLO).
F req
uency Se
tting
requency
Setting
The frequency of the SC2544 is user- programmable.
The oscillator of SC2544 can be programmed with an
external resistor from the Rosc pin to the ground. The
step-down controller is capable of operating up to
300KHz. The relationship between oscillation frequency
versus oscillation resistor is shown in Figure 1.
The period of start up can be programed by the soft
start capacitor:
The advantages of using constant frequency operation
are simple passive component selection and ease of
feedback compensation. Before setting the operating
frequency, the following trade-offs should be considered.
1) Passive component size
2) Circuitry efficiency
3) EMI condition
4) Minimum switch on time
5) Maximum duty ratio
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFETs/Diodes switching losses
are proportional to the operating frequency. Other issues
such as heat dissipation, packaging and cost issues are
also to be considered. The frequency bands for signal
transmission should be avoided because of EM
interference.
Tss =
By connecting different capacitors at SS1 and SS2
pins, VO1 and VO2 will start at different time, achieving
sequential start-up for the outputs. Connecting SS1
and SS2 together would make the 2 outputs start and
reach steady state values at the same time, achieving
ratiometric start-up.
Shutdown
When the EN pin is pulled low, an internal 15uA current
source discharges the soft-start capacitor and DRVH/
DRVL signals stop pulsing. The output voltage ramps
down at a rate determined by the load condition.
The SC2544 can also be shutdown by pulling down
directly on the SS pin. The designer needs to consider
the slope of the SS pin voltage and choose a suitable
pull down resistor to prevent the output from
undershooting.
350
300
Fsw(KHz)
Css × 2.5V
84 μA
250
Shutdown can also be triggered when an OCP condition
occurs. When an OCP condition is detected, DRVH and
DRVL will stop pulsing and enter a “tri-state shutdown”
with the output voltage ramping down at a rate determined by the load condition. The internal 15uA current
source will begin discharging the soft-start capacitor
and when the soft-start voltage reaches 0.65V, DRVL
will go high.
200
150
100
50
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
Rosc(KOHM)
Figure 1. Switching frequency versus Rosc.
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
Over Current Protection (OCP)
The inductor current is sensed by using the low side
MOSFET Rds(on) . After low side MOSFET is turned
on, the OCP comparator starts monitoring the
voltage drop across the MOSFET. The OCP trip
level is programmed by the resistor from the ILIM
pin to the phase node. There is an internal current
source that flows out of the ILIM pin which will
generate a voltage drop on the setting resistor.
When the sum of the setting resistor voltage and
the MOSFET drain to source voltage is less then
zero, the OCP condition will be flagged. This
functionality is depicted in Figure 2.
The following formula is used to set the OCP level
TG
IL
100n S
B lan kin g
Figure 3. OCP comparator timing chart.
U nder V
oltage Lock Out (UVL
O)
Voltage
(UVLO)
10 µ A × RILIM = I L _ PEAK × RDS ( ON )
The UVLO circuitry monitors Vcc and the soft start
begins once Vcc ramps up above 4.5V. There is a
built in 200mV hysteresis for the UVLO ramp down
threshold. The gate driver output will be in “tristate” (both high side and low side MOSFET off)
once Vcc ramps down bellow 4.2V (typical), and the
soft start cap will be discharged by internal 15uA
current sink.
When OCP is tripped, both high side and low side
MOSFETs will be turned off and this condition is
latched. At the same time, the soft start cap will
be discharged by the internal current source of
15uA. When the Vss drops bellow 0.65V, the DRVL
pin will go high again.
Ov
er V
oltage Pr
o t ection (O
VP)
Over
Voltage
Pro
(OVP)
To avoid switching noise during the phase node
commutation, a 100nS blanking time is built in
after the low side MOSFET is turned on, as shown in
Fig. 3.
The OVP circuitry monitors the feedback voltages,
If either feedback voltage exceeds 0.89V, the OVP
condition is registered. Under this condition, the
DRVH pins will be pulled low, and the DRVL pins will
be pulled high. This will create a “crow bar” condition for the input power rail in case the high side
MOSFET is failed short. The crow bar operation
may trip the input supply to prevent the load from
seeing more voltage.
VCC
10uA
+
OCP
DRVH
ILIM
O C P A ctive
OUTPUT
P o w er Good Output
Out
-
DRVL
The power good is an open collector output. The
PWRGD pin is pulled low at start up if any of the
two feedback voltages below 90% of its regulation
level. The ramp down threshold of the signal is 80%
of the regulation target. External pull up is required for the PWRGD pin, and the pull up resistor
should be chosen such that the pin does not sink
more than 2mA when PWRGD is low.
Figure 2. Block diagram of over current
protection.
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
IL,rms = Io 1 +
General Design Pr
ocedure ffor
or a St
ep-do
wn P
o w er
Procedure
Step-do
ep-down
Po
Converter
The followings are to be considered when choosing
inductors.
a) Inductor core material: For higher efficiency
applications above 300 KHz, ferrite, Kool-Mu and
polypermalloy materials should be used. Low-cost
powdered iron cores can be used for cost sensitiveapplications below 300 KHz but with attendant higher
core losses.
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The
designer can choose the adjacent (larger) standard
inductance value. The inductance varies with
temperature and DC current. It is a good engineering
practice to re-evaluate the resultant current ripple
at the rated DC output current.
c) Current rating: The saturation current of the
inductor should be at least 1.5 times of the peak
inductor current under all conditions.
Selection criterias and design procedures for the following parameters are described:
1) Output inductor (L) type and value
2) Output capacitor (C o) type and value
3) Input capacitor (C in) type and value
4) Power MOSFETs
5) Current sensing and limiting circuit
6) Voltage sensing circuit
7) Loop compensation network
The following step-down converter specifications are
needed:
Input voltage range: V in,min and V in,max
Input voltage ripple (peak-to-peak): DV in
Output voltage: V o
Output voltage accuracy: e
Output voltage ripple (peak-to-peak): DV o
Nominal output (load) current: I o
Maximum output current limit: I o,max
Output (load) current transient slew rate: dIo (A/ s)
Circuit efficiency: η
Output Capacit
or (C o) and V out Ripple
Capacitor
Inductor (L) and Ripple Current
The output capacitor provides output current filtering
in steady state and serves as a reservoir during load
transient. The output capacitor can be modeled as
an ideal capacitor in series with its parasitic ESR and
ESL as shown in Figure 4.
Both step-down controllers in the SC2544 operate in
synchronous continuous-conduction mode (CCM)
regardless of the output load level. The output
inductor selection/design is based on the output DC
and transient requirements. Both output current and
voltage ripples are reduced with larger inductance
but it takes longer to change the inductor current
during load transients. Conversely smaller inductance
results in lower DC copper losses but the AC core
losses (flux swing) and the winding AC resistance losses
are higher. A compromise is to choose the inductance
such that peak-to-peak inductor ripple-current is 20%
to 30% of the rated output load current.
Assuming that the inductor current ripple (peak-topeak) value is δ *Io, the inductance value will then
be
L=
δ2
.
12
Co
Lesl
Resr
Figure 4. An equivalent circuit of output.
If the current through the branch is ib(t), the voltage
across the terminals will then be
Vo (1 − D)
.
δIo fs
t
vo (t) = Vo +
The peak current in the inductor becomes
di (t)
1
ib (t)dt + Lesl b + Resrib (t).
Co 0
dt
∫
This basic equation illustrates the effects of ESR,
ESL, and Co on the output voltage.
(1+ δ /2)*Io
and the RMS current is
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
The voltage rating of aluminum capacitors should be
at least 1.5Vo. The RMS current ripple rating should
also be greater than
The first term is the DC voltage across C o at time
t=0. The second term is the voltage variation caused
by the charge balance between the load and the
converter output. The third term is voltage ripple
due to ESL and the fourth term is the voltage ripple
due to ESR. The total output voltage ripple is then a
vector sum of the last three terms.
G,R
Usually it is necessary to have several capacitors of
the same type in parallel to satisfy the ESR
requirement. The voltage ripple caused by the
capacitor charge/discharge should be an order of
magnitude smaller than the voltage ripple caused by
the ESR. To guarantee this, the capacitance should
satisfy
Since the inductor current is a triangular waveform
with peak-to-peak value G *I o , the ripple-voltage
caused by inductor current ripples is
'Y& |
&R !
G,R
&RIV
/ HVO I V
G ,R
'
and the ESR ripple-voltage is
'Y(65
Remark 1: High frequency ceramic capacitors
may not carry most of the ripple current. It also
depends on the capacitor value. Only when the
capacitor value is set properly, the effect of ceramic
capacitor low ESR starts to be significant. For
example, if a 10 P F, 4m : ceramic capacitor is
connected in parallel with 2x1500 P F, 90m :
electrolytic capacitors, the ripple current in the
ceramic capacitor is only about 42% of the current in
the electrolytic capacitors at the ripple frequency. If
a 100 P F, 2m : ceramic capacitor is used, the ripple
current in the ceramic capacitor will be about 4.2
times of that in the electrolytic capacitors. When
two 100 P F, 2m : ceramic capacitors are used, the
current ratio increases to 8.3. In this case most of
the ripple current flows in the ceramic decoupling
capacitor. The ESR of the ceramic capacitors will then
determine the output ripple-voltage.
5HVUG,R Aluminum capacitors (e.g. electrolytic) have high
capacitances and low ESLs. The ESR has the dominant
effect on the output ripple voltage. It is therefore
very important to minimize the ESR. Other types to
choose are solid OS-CON, POSCAP, and tantalum.
When determining the ESR value, both the steady
state ripple-voltage and the dynamic load transient
need to be considered. To meet the steady state
output ripple-voltage spec, the ESR should satisfy
5H VU¢
'92
G ,2
To limit the dynamic output voltage overshoot/
undershoot within a (say 3%) of the steady state
output voltage from no load to full load, the ESR
value should satisfy
5H VU ¢
Remark 2: The total equivalent capacitance of the
filter bank is not simply the sum of all the paralleled
capacitors. The total equivalent ESR is not simply the
parallel combination of all the individual ESRs either.
Instead they should be calculated using the following
formula.
92
,2
Then, the required ESR value of the output capacitors
should be
Resr = min{Resr1,Resr2 }.
ã 2005 Semtech Corp.
SIV5 HVU
In many applications, several low ESR ceramic
capacitors are added in parallel with the aluminum
capacitors in order to further reduce ESR and improve
high frequency decoupling. Because the values of
capacitance and ESR are usually different in ceramic
and aluminum capacitors, the following remarks are
made to clarify some practical issues.
the ripple-voltage due to ESL is
' Y (6/
HT Z &HT&Z
11
5D 5E Z &D &E &D &E 5D &D 5E &E Z &D &E &D &E www.semtech.com
SC2544
POWER MANAGEMENT
Applications Information (Cont.)
&5HTHTZZ In Figure 6 the DC input voltage source has an internal
impedance Rin and the input capacitor Cin has an ESR
of R esr . MOSFET and input capacitor current
waveforms, ESR voltage ripple and input voltage ripple
are shown in Figure 7.
5D5E 5D 5E Z &D &E 5E &E 5D &D 5D 5E Z &D &E &D &E where R 1a and C 1a are the ESR and capacitance of
electrolytic capacitors, and R 1b and C1b are the ESR
and capacitance of the ceramic capacitors, respectively
(Figure 5).
L4
&D
&E
&HT
5D
5E
5HT
L&LQ
9HVU
Figure 5. Equivalent RC branch.
9&LQ
Req and Ceq are both functions of frequency. For
rigorous design, the equivalent ESR should be
evaluated at the ripple frequency for voltage ripple
calculation when both ceramic and electrolytic
capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1,
then R eq and Ceq will be frequency-independent and
Figure 7. Typical waveforms at converter input.
It can be seen that the current in the input capacitor
pulses with high di/dt. Capacitors with low ESL should
be used. It is also important to place the input capacitor
close to the MOSFETs on the PC board to reduce trace
inductances around the pulse current loop.
Req = 1/2 R1 and Ceq = 2C1.
Input Capacitor (Cin)
The RMS value of the capacitor current is
approximately
The input supply to the converter usually comes from
a pre-regulator. Since the input supply is not ideal,
input capacitors are needed to filter the current pulses
at the switching frequency. A simple buck converter
is shown in Figure 6.
,&LQ
5HVU
PCin = ICin2Resr.
/
For reliable operation, the maximum power dissipation
in the capacitors should not result in more than 10oC
of temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of
the capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high
enough to handle the ripple current. It is common
pratice that multiple capacitors are placed in parallel
to increase the ripple current handling capability.
'
9'&
&LQ
&R
5R
Figure 6. A simple model for the converter input.
ã 2005 Semtech Corp.
G
'
'
' @
K
K
The power dissipated in the input capacitors is then
4
5LQ
,R '> 12
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
Choosing P
ower MOSFET
Po
MOSFETss
Main considerations in selecting the MOSFET’s are
power dissipation, MOSFETs cost, and packaging.
Switching losses and conduction losses of the MOSFET’s
are directly related to the total gate charge (C g) and
channel on-resistance (R ds(on)). In order to judge the
performance of MOSFET’s, the product of the total
gate charge and on-resistance is used as a figure of
merit (FOM). Transistors with the same FOM follow
the same curve in Figure 8.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input
voltage ripple due to the ESR is
δ
∆v ESR = R esr (1 + )Io .
2
The peak-to-peak input voltage ripple due to the
capacitor is
∆v C ≈
DIo
,
Cin fs
From these two expressions, CIN can be found to meet
the input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce
ripple. The two step-down channels of the SC2544
operate at 180 degrees from each other. If both stepdown channels in the SC2544 are connected to the
same input rail, the input RMS currents will be reduced.
Ripple cancellation effect of interleaving allows the
use of smaller input capacitors.
Gate Charge (nC)
50
When two channels with a common input are
interleaved, the total DC input current is simply the
sum of the individual DC input currents. The combined
input current waveform depends on duty ratio and
the output current waveform. Assuming that the
output current ripple is small, the following formula
can be used to estimate the RMS value of the ripple
current in the input capacitor.
2
If D1>0.5 and (D1-0.5) < D2<0.5, then
2
ICin ≈ 0.5Io1 + (D1 − 0.5)(Io1 + Io 2 )2 + (D 2 − D1 + 0.5)Io 2 .
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
1
0
0
5
1
Rds
On-resistance (mOhm)
10
15
20
20
The closer the curve is to the origin, the lower is the
FOM. This means lower switching loss or lower
conduction loss or both. It may be difficult to find
MOSFET’s with both low C g and low R ds(on. Usually a
trade-off between R ds(on and Cg has to be made.
MOSFET power dissipation consists of
a) conduction loss due to the channel resistance Rds(on);
b) switching loss due to the switch rise time t r and
fall time t f; and
c) the gate loss due to the gate resistance RG.
2
ICin ≈ 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 − D 2 − 0.5)Io 2 .
If D1>0.5 and D2 > 0.5, then
2
20
MOSFET selection also depends on applications. In
many applications, either switching loss or conduction
loss dominates for a particular MOSFET. For
synchronous buck converters with high input to output
voltage ratios, the top MOSFET is hard switched but
conducts with very low duty cycle. The bottom switch
conducts at high duty cycle but switches at near zero
voltage. For such applications, MOSFET’s with low Cg
are used for the top switch and MOSFET’s with low
R ds(on) are used for the bottom switch.
ICin ≈ D1Io1 + D 2Io2 .
2
Cg( 500 , Rds )
Figure 8. Figure of Merit curves.
If D1<0.5 and D2<0.5, then
2
Cg( 200 , Rds )
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
2
40
Cg( 100 , Rds )
2
ICin ≈ (D1 + D 2 − 1)(Io1 + Io 2 )2 + (1 − D 2 )Io1 + (1 − D1 )Io2 .
2005 Semtech Corp.
13
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
In Figure 9, Qgs1 is the gate charge needed to bring
the gate-to-source voltage Vgs to the threshold voltage
V gs_th.
Q gs2 is the additional gate charge required for the
switch current to reach its full-scale value Ids, and Qgd
.
is the charge needed to charge gate-to-drain (Miller)
capacitance when Vds is falling.
Top Switc
h
Switch
The RMS value of the top switch current is calculated
as
δ2
IQ1,rms = Io D(1+ 12
).
The conduction losses are then
P tc = I Q1,rms 2 R ds(on).
Switching losses occur during the time interval [t 1,
t3]. Defining tr = t3-t 1 and tr can be approximated as
R ds(on) varies with temperature and gate-source
voltage. Curves showing Rds(on) variations can be found
in manufacturers’ data sheet. From the Si4860
datasheet, Rds(on) is less than 8m Ω when Vgs is greater
than 10V. However R ds(on) increases by 50% as the
junction temperature increases from 25oC to 110 oC.
tr =
Vcc − Vgsp
.
where Rgt is the total resistance from the driver supply
rail to the gate of the MOSFET. It includes the gate
driver internal impedance Rgi, external resistance Rge
and the gate resistance Rg within the MOSFET :
The switching losses can be estimated using the simple
formula
R gt = Rgi+R ge+R g.
Vgsp is the Miller plateau voltage shown in Figure 9.
Similarly an approximate expression for tf is
Pts = 21 ( t r + t f )(1 + 2δ )Io Vin fs .
where tr is the rise time and tf is the fall time of the
switching process. Different manufactures have
different definitions and test conditions for t and
r
t . To clarify these, we sketch the typical MOSFET
f
switching characteristics under clamped inductive
mode in Figure 9.
tf =
(Q gs 2 + Q gd )R gt
Vgsp
.
Only a portion of the total losses P g = Q g V cc f s is
dissipated in the MOSFET package. Here Q g is the
total gate charge specified in the datasheet. The
power dissipated within the MOSFET package is
V ds
V o lts
(Q gs 2 + Q gd )R gt
Ids
M iller plateau
Ptg =
V gs
Rg
R gt
Q g Vcc fs .
The total power loss of the top switch is then
V gs th
Pt = Ptc+Pts+Ptg.
Q gs1 Q gs2
t0
t1
t2
Q gd
t3
If the input supply of the power converter varies
over a wide range, then it will be necessary to
weigh the relative importance of conduction and
switching losses. This is because conduction losses
are inversely proportional to the input voltage.
Switching loss however increases with the input
voltage. The total power loss of MOSFET should be
calculated and compared for high-line and low-line
cases. The worst case is then used for thermal
design.
G ate charge
Figure 9. MOSFET switching characteristics
2005 Semtech Corp.
14
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
Bottom Switch
The RMS current in bottom switch is given by
Main Control Loop Design
The goal of compensation is to shape the frequency
response charatericstics of the buck converter to
achieve a better DC accuracy and a faster transient
response for the output voltage, while maintaining
the loop stability.
2
δ
IQ2,rms = Io (1− D)(1+ 12
).
The conduction losses are then
The block diagram in Figure 10 represents the control
loop of a buck converter designed with the SC2544. The
control loop consists of a compensator, a PWM modulator, and an LC filter.
P bc=I Q2,rms2 R ds(on) .
where R ds(on) is the channel resistance of bottom
MOSFET. If the input voltage to output voltage ratio
is high (e.g. V in =12V, V o=1.5V), the duty ratio D will
be small. Since the bottom switch conducts with duty
ratio (1-D), the corresponding conduction losses can
be quite high.
The LC filter and PWM modulator represent the small
signal model of the buck converter operating at fixed
switching frequency. The transfer function of the
model is given by:
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the
bottom MOSFET. The bottom MOSFET switches on with
only a diode voltage between its drain and source
terminals. The switching loss is negligible due to near zerovoltage switching.
VO VIN
1 + sRESRC
=
⋅
VC Vm 1 + sL / R + s 2 LC
REF
REF
Rg
R gt
EA
L
Vo
MODULATOR
-
Co
The gate losses are estimated as
P bg =
PWM
+
Zf
Q g V cc f s .
ERROUT
Resr
Zs
The total bottom switch losses are then
Pb=Pbc+Pbg.
Fig. 10. Block diagram of the control loop.
Once the power losses for the top and bottom
MOSFET’s are known, thermal and package design
at component and system level should be done to
verify that the maximum die junction temperature
(T j,max , usually 125 o C) is not exceeded under the
worst-case condition. The equivalent thermal
impedance from junction to ambient ( θ ja ) should
satisfy
θ ja ≤
Tj,max − Ta,max
Ploss
where VIN is the input voltage, Vm is the amplitude of
the internal ramp, and R is the equivalent load.
The model is a second order system with a finite DC
gain, a complex pole pair at Fo, and an ESR zero at
Fz, as shown in Figure 11. The locations of the poles
and zero are determined by:
.
θ ja depends on the die to substrate bonding,
packaging material, the thermal contact surface,
thermal compound property, the available effective
heat sink area, and the air flow condition (natual or
forced convection). Actual temperature measurement
of the prototype should be carried out to verify the
thermal design.
2005 Semtech Corp.
15
FO =
1
2π LCO
FZ =
1
2π Re srCO
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
The compensator in Figure 10 includes an error amplifier and impedance networks Zf and Zs. It is implemented by the circuit in Figure 12. The compensator
provides an integrator, double poles, and double zeros. As shown in Figure 11, the integrator is used to
boost the gain at low frequency. Two zeros are introduced to compensate excessive phase lag at the
loop gain crossover due to the integrator (-90deg)
and the complex pole pair (-180deg). Two high frequency poles are designed to compensate the ESR
zero and to attenuate high frequency noise.
Fp1
G A IN (d B )
F z1
LO
Rbot =
OP
GA
IN
Fo
CO
Fz
NV
Fc
ER
TE
R G
A IN
F R E Q U E N C Y (H z)
Fig. 11. Bode plots for control loop design.
A MathCAD program is available upon request for the
calculation of the compensation parameters.
C2
C1
R2
C3
Rtop
Vc
0.75V
∗ Rtop
Vo − 0.75V
where 0.75V is the internal reference voltage of the
SC2544.
The other components of the compensator can be
calculated using following design procedure:
(1). Plot the converter gain, including LC filter and
PWM modulator.
(2). Select the open loop crossover frequency Fc located at 10% to 20% of the switching frequency. At
Fc, find the required DC gain.
(3). Use the first compensator pole Fp1 to cancel the
ESR zero Fz.
(4). Have the second compensator pole Fp2 at half
the switching frequency to attenuate the switching
ripple and high frequency noise.
(5). Place the first compensator zero Fz1 at or below
50% of the power stage resonant frequency Fo.
(6). Place the second compensator zero Fz2 at or
below the power stage resonant frequency Fo.
Fp2
C O M P E N S A T O R G A IN
F z2
A resistive divider is used to program the output voltage. The top resistor R top of the divider in Fig. 12
can be chosen from 20k Ω to 30k Ω . Then the bottom resistor Rbot is found from:
R3
Vo
Out
E/A
+
Rbot
0.75V
Fig. 12. Compensation network.
2005 Semtech Corp.
16
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters. A power ground plane is required to reduce
ground bounces. The followings are suggested for
proper layout.
Control Section
6) The frequency-setting resistor Rosc should be placed
close to Pin 23. Trace length from this resistor to the
analog ground should be minimized.
7) Place the bias decoupling capacitor right across
the VCC and analog ground AGND.
P o w er Stage
1) Separate the power ground from the signal ground. In
SC2544 design, use an isolated local ground plane for
the controller and tie it to power grand.
2) Minimize the size of the high pulse current loop.
Keep the top MOSFET, the bottom MOSFET and the
input capacitors within a small area with short and
wide traces. In addition to the aluminum energy
storage capacitors, add multi-layer ceramic (MLC)
capacitors from the input to the power ground to
improve high frequency bypass.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFETs
to reduce stray inductances. Add a small RC snubber
if necessary to reduce the high frequency ringing at
the phase node. Sometimes slowing down the gate
drive signal also helps in reducing the high frequency
ringing at the phase node if the EMI is a concern for
the system.
4) Shorten the gate drive trace. Integrity of the
gate drive (voltage level, leading and falling edges)
is important for circuit operation and efficiency. Short
and wide gate drive traces reduce trace inductances.
Bond wire inductance is about 2~3nH. If the length of
the PCB trace from the gate driver to the MOSFET
gate is 1 inch, the trace inductance will be about
25nH. If the gate drive current is 2A with 10ns rise
and falling times, the voltage drops across the bond
wire and the PCB trace will be
0.6V and 5V
respectively. This may slow down the switching
transient of the MOSFET’s. These inductances may
also ring with the gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and PVCC) close to the IC and power
ground.
2005 Semtech Corp.
17
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SC2544
POWER MANAGEMENT
Typical Application Circuit
SC2544MLTRT
VO2
U1
VIN+
C1
1uF/25V
1
C2
1uF/16V
VCC 2
3
EN
4
FB1
C3
SS1
1n
4.7n R4
C9
18k
R6
5
C10 220nF
4.7K
C32
7
N.P. C17 1uF/16V
R8
R10
6
0
2.2
8
9
10
11
VIN+
12
SC2544
VIN
AGND
VCC
ROSC
EN
PWRGD
FB1
FB2
ERROUT1 ERROUT2
SS1
SS2
ILIM1
ILIM2
BST1
BST2
DRVH1
DRVH2
PHASE1
PHASE2
DRVL1
DRVL2
PGND
PVCC
R2
10K
24
R3
23
73.2K
22
PWGRD
21
FB2
SS2
20
19
470nF C11
R5
R7
4.7K
1uF/16V
C33
N.P.
18
17
C4 1n
C18
16 R9
C12 4.7n
18k
0
R11
15
2.2
14
VIN+
VCC
13
C31
R12
L1
7.6uH
28K
Q3
R15 499
FB1
C20
C21
C22
C23
IR F 7 8 1 1 A
VO1
0R
C34
N.P.
C19 3.9nF
N.P.
3 3 0 u F /6 .3 V
N.P.
3 3 0 u F /6 .3 V
4.9K
C16
C15
0.1uF/25V 10uF/25V 10uF/25V
L2
N.P.
VO2
7.6uH
Q4
R13 499
R14 28K
C35
N.P.
C29
C24
C25
C26
C27
C28 3.3nF
FB2
N.P.
C30
R17
C14
R25
N.P.
R25
N.P.
N.P.
N.P.
N.P.
3 3 0 u F /6 .3 V
Q2
C13
Q1
330uF /6.3V
10uF/25V 10uF/25V 0.1uF/25V
R24
IR 7 8 1 1 A
C8
1 u F /1 6 V
N.P.
C7
IR F 7 8 1 1 A
C6
IR F 7811A
C5
R18 8.25K
Vin: 4.5V ~ 28V
Vout: 3.3V/6A and 5V/6A
© 2005 Semtech Corp.
18
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SC2544
POWER MANAGEMENT
Evaluation Board - Bill of Material
SC2544MLTRT
R ef
Qty
Reference
Part Number/Value
Manufacturer
1
1
C1
1uF, 25V, X5R,Ceramic, 0805
Any
2
3
C2,C18,C31
1uF, 16V, X5R, Ceramic , 0805
Any
3
4
C3,C4,C34,C35
1nF, Ceramic 0805
Any
4
14
L1, L2, C 5, C 16, C 20,
C 21, C 24, C 24, C 29,
C30, C32, C33,R25
N.P.
5
4
C 6, C 7, C 14, C 15
10uF, 25V, X5R , Ceramic 1206
Panasonic, ECJ3YB1E106M
6
2
C 8, C 13
0.1uF, 25V, 0603
Any
7
2
C 12, C 9
4.7nF, Ceramic, 0603
Any
8
1
C 10,
220nF, Ceramic, 0603
Any
9
1
C11
470nF, Ceramic, 0603
Any
10
1
C 17
1nF, Ceramic, 0603
Any
11
2
C28,C19
3.3nF, Ceramic, 0603
Any
12
2
C 22, C 23, C 26, C 27
33uF, 6.3V, 18mohm, PosCap
Sanyo, 6TPE330MIL
13
2
L1, L2
7.6uH, 6.8A, 16mohm
Sumida, CDRH127
14
4
Q1, Q2, A3, Q4
IRF7811A
IR
15
1
R2
10K , 0603
Any
16
1
R3
73.2K, 0603
Any
17
2
R5, R4
18K , 0603
Any
18
1
R6
6.8K, 0603
Any
19
1
R7
4.7K, 0603
Any
20
1
R10
4.7, 0603
Any
21
1
R25, R11
4.7, 0603
Any
22
2
R14, R12
2.2, 0603
Any
23
2
R15,R13
499, 0603
Any
24
2
R18, R17
4.9K, 0603
Any
25
1
R24
0, 0603
Any
26
1
U1
S C 2544
Semtech
© 2005 Semtech Corp.
19
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SC2544
POWER MANAGEMENT
Typical Characteristics
CH1:
CH2:
CH3:
CH4:
CH1:Vi
CH2:Ven
CH3:VSS
CH4:Vo
TG1
BG1
TG2
BG2
Shut down by pulling down EN pin
voltage.
Gate waveform
CH1: EN
CH2: VO1
CH3:Vo
CH4:Io
CH3: VO2
Ratiometric start up(connect
SS1,SS2 together).
Transient response(0-5A).
CH1: EN
CH2: VO1
CH1:TG
CH2:BG
CH3:TG
CH4:BG
CH3: VO2
Over current protection (5A/10mV)
Sequential start up (Seperate
SS1,SS2).
© 2005 Semtech Corp.
20
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SC2544
POWER MANAGEMENT
Typical Characteristics (Cont.)
Vin=8V
Vin=16V
190
100%
188
Fs (khz)
Efficient
80%
60%
40%
186
184
182
180
20%
178
-40
0%
0
1
2
3
4
5
6
Io(A)
7
8
9
20
50
110
Freq. vs. Temp. ( Rosc=75kohm,
Vin=16V).
10.5
10.3
350
300
Vcc (V)
250
200
150
100
50
10.1
9.9
9.7
9.5
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
10 12 14 16 18 20 22 24 26 28 30
Vin (V)
Rosc(KOHM)
Operating frequency vs. Rosc.
Vcc vs. Vin ( Ta=25 Degree C).
9
10.13
8
10.11
7
Vcc (V)
Io(A)
80
Temperature (Degree C)
Efficiency Curve for
Vout=3.3V.
Fsw(KHz)
-10
10
6
10.09
10.07
5
10.05
4
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5
10.03
-40
0
20
40
60
80
100
120
Tj (Degree C)
RILIM(KOHM)
RILIM vs. OCP (Vi=12V).
2005 Semtech Corp.
-20
Vcc vs. Temp.
21
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SC2544
POWER MANAGEMENT
Typical Characteristics (Cont.)
7.0
Icc (mA)
6.5
6.0
5.5
5.0
8
10
12
14
16
18
20
22
24
26
28
Vin(V)
DRVL min Ton(nS)
Icc vs. Vin (25 DegreeC).
500
480
460
440
420
400
-40
-20
0
20
40
60
80
100 120
Tj (Degree C)
DL min Ton vs. Tj (Vin=16V).
Dead time (nS)
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
Tj (Degree C)
Dead time vs. Tj (Vin=16V, DH falling to DL
rising).
2005 Semtech Corp.
22
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SC2544
POWER MANAGEMENT
Outline Drawing - TSSOP-24
A
DIM
D
e
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
N
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 2 3
e/2
B
.047
.002
.006
.042
.031
.007
.012
.003
.007
.303 .307 .311
.169 .173 .177
.252 BSC
.026 BSC
.018 .024 .030
(.039)
24
0
8
.004
.004
.008
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
7.70 7.80 7.90
4.30 4.40 4.50
6.40 BSC
0.65 BSC
0.45 0.60 0.75
(1.0)
24
0
8
0.10
0.10
0.20
D
aaa C
SEATING
PLANE
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
A2 A
C
H
A1
bxN
bbb
c
GAGE
PLANE
C A-B D
0.25
L
(L1)
SEE DETAIL
SIDE VIEW
DETAIL
A
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AD.
Land Pattern - TSSOP-24
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1.
© 2005 Semtech Corp.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
23
www.semtech.com
SC2544
POWER MANAGEMENT
Outline Drawing - MLPQ-24 (4 x 4mm)
A
D
B
DIM
PIN 1
INDICATOR
(LASER MARK)
Top View
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
E
A2
A
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.031 .035 .040 0.80 0.90 1.00
.000 .001 .002 0.00 0.02 0.05
- (0.20) - (.008) .007 .010 .012 0.18 0.25 0.30
.151 .157 .163 3.85 4.00 4.15
.100 .106 .110 2.55 2.70 2.80
.151 .157 .163 3.85 4.00 4.15
.100 .106 .110 2.55 2.70 2.80
0.50 BSC
.020 BSC
.011 .016 .020 0.30 0.40 0.50
24
24
.004
0.10
.004
0.10
SEATING
PLANE
aaa C
A1
C
D1
LxN
E/2
Bottom View
E1
2
1
N
bxN
bbb
e
C A B
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPQ-24 (4 x 4mm)
K
(C)
G
H
DIM
C
G
H
K
P
X
Y
Z
Z
DIMENSIONS
INCHES
MILLIMETERS
(.155)
(3.95)
3.10
.122
.106
2.70
.106
2.70
.021
0.50
.010
0.25
.033
0.85
.189
4.80
X
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
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Semtech Corporation, which has its headquarters in the U.S.A.
2005 Semtech Corp.
Semtech Sw itz erland GmbH
Japan Branch
24
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