TM SPANSION MCP Data Sheet September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-50222-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 64M (×16) FLASH MEMORY & 8M (×16) SRAM MB84SD23280FA/MB84SD23280FE-70 ■ FEATURES • Power supply voltage of 1.65 V to 1.95 V • High performance 70 ns maximum access time (Flash) 70 ns maximum access time (SRAM) • Operating Temperature –30 °C to +85 °C • Package 73-ball FBGA (Continued) ■ PRODUCT LINEUP Flash Memory Supply Voltage (V) VCCf* = 1.8 V +0.15V –0.15 V SRAM VCCs* = 1.8 V Max Address Access Time (ns) 70 70 Max CE Access Time (ns) 70 70 Max OE Access Time (ns) 20 35 *: Both VCCf and VCCs must be in recommended operation range when either part is being accessed. ■ PACKAGE 73-ball plastic FBGA (BGA-73P-M03) +0.15V –0.15 V MB84SD23280FA/MB84SD23280FE-70 (Continued) • FLASH MEMORY • 0.17 µm process technology • Simultaneous Read/Write operation (Dual Bank) • FlexBankTM *1 Bank A: 16M bit (16KB × 4 and 64KB × 31) Bank B: 16M bit (64KB × 32) Bank C: 16M bit (64KB × 32) Bank D: 16M bit (16KB × 4 and 64KB × 31) • Minimum 100,000 program/erase cycles • Sector Erase Architecture Four 8K words, a hundred twenty-eight 32K words sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. • WP Input Pin At VIL, allows protection of all sectors, regardless of sector protection/unprotection status At VIH, allows removal of sector protection • Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode • Low VCC write inhibit • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device resumes the erase operation • Sector Protection Software command sector locking • Please Refer to “MBM29BS64LF” Datasheet in Detailed Function •SRAM • Power Dissipation Operating : 50 mA Max Standby :15 µA Max • Power Down Features using CE1s and CE2s • Data Retention Supply Voltage: 1.0 V to 1.95 V • CE1s and CE2s Chip Select • Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8) *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MB84SD23280FA/MB84SD23280FE-70 ■ PIN ASSIGNMENT FBGA (TOP VIEW) Marking Side A10 B10 F10 G10 L10 M10 N.C. N.C. N.C. N.C. N.C. N.C. D9 E9 F9 G9 H9 J9 A15 A21 N.C. A16 N.C. VSS C8 D8 E8 F8 G8 H8 J8 K8 A11 A12 A13 A14 N.C. DQ15 DQ7 DQ14 C7 D7 E7 F7 G7 H7 J7 K7 A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5 B6 C6 D6 E6 H6 J6 K6 L6 N.C. WE CE2s A20 DQ4 VCCs N.C. N.C. B5 C5 D5 E5 H5 J5 K5 L5 N.C. WP RESET RDY DQ3 VCCf DQ11 N.C. C4 D4 E4 F4 G4 H4 J4 K4 LB UB A18 A17 DQ1 DQ9 DQ10 DQ2 C3 D3 E3 F3 G3 H3 J3 K3 A7 A6 A5 A4 VSS OE DQ0 DQ8 D2 E2 F2 G2 H2 J2 A3 A2 A1 A0 CEf CE1s A1 B1 C1 F1 G1 L1 M1 N.C. N.C. N.C. N.C. N.C. N.C. N.C. (BGA-73P-M03) 3 MB84SD23280FA/MB84SD23280FE-70 ■ PIN DESCRIPTION Pin Configuration Pin Name A18 to A0 Function Input/Output Address Inputs (Common) I A21, A20, A19 Address Inputs (Flash) I DQ15 to DQ0 Data Inputs/Outputs (Common) I/O CEf Chip Enable (Flash) I CE1s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I RDY Ready Outputs (Flash) Open Drain Output O UB Upper Byte Control (SRAM) I LB Lower Byte Control (SRAM) I RESET Hardware Reset Pin (Flash) I WP Write Protect (Flash) I N.C. No Internal Connection VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCs Device Power Supply (SRAM) Power ■ BLOCK DIAGRAM VCCf VSS A21 to A0 RDY A21 to A0 WP 64 M bit Flash Memory RESET CEf DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A18 to A0 LB UB WE OE CE1s CE2s 4 8 M bit SRAM DQ15 to DQ0 MB84SD23280FA/MB84SD23280FE-70 ■ DEVICE BUS OPERATIONS User Bus Operations Operation*1, *3 Full Standby H H Output Disable L Read from Flash*2 L Write to Flash L Read from SRAM Write to SRAM WE LB UB DQ7 to DQ0 DQ15 to DQ8 RESET WP*4 X X X X High-Z High-Z H X H H X X High-Z High-Z X X H H High-Z High-Z H X H H X X High-Z High-Z L H X X DOUT DOUT H X H L X X DIN DIN H H L L DOUT DOUT H L High-Z DOUT H X L H DOUT High-Z L L DIN DIN H L High-Z DIN H X L H DIN High-Z CEf CE1s CE2s OE H H Flash All Sector Write Protection*4 X Flash Hardware Reset X H X X L L H H X X L H X X L H X X L L L H H X X H X X L L X H L X X X X X X H L X X X X High-Z High-Z L X Legend : L = VIL, H = VIH, X = VIL or VIH. See “■DC CHARACTERISTICS” for voltage levels. *1: Other operations except for this indicated table are prohibited. *2: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: At WP=VIL, all sectors are protected. 5 MB84SD23280FA/MB84SD23280FE-70 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Tstg −40 +125 °C TA −30 +85 °C VIN −0.3 VCCf + 0.1 V VOUT −0.3 VCCs + 0.1 V VCCf Supply * VCCf −0.2 +2.5 V VCCs Supply * VCCs −0.5 +2.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins * * : Minimum DC voltage on input or l/O pins are –0.5 V. During voltage transitions, inputs may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and l/O pins are VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Max Unit Ambient Temperature TA −30 +85 °C VCCf Supply Voltages VCCf +1.65 +1.95 V VCCs Supply Voltages VCCs +1.65 +1.95 V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB84SD23280FA/MB84SD23280FE-70 ■ DC CHARACTERISTICS*1, *2 Parameter Symbol Value Test Conditions Min Typ Max Unit Input Leakage Current ILI VIN = VSS to VCCf, VCCs –1.0 — +1.0 µA Output Leakage Current ILO VOUT = VSS to VCCf, VCCs –1.0 — +1.0 µA 12 16 3.3 5 5 MHz Flash VCC Active Read Current *3 ICC1f CEf = VIL, OE = VIH, WEf = VIH Flash VCC Active Write Current *4 ICC2f CEf = VIL, OE = VIH, VPP = VIH — 15 40 mA Flash VCC Active Current (Read-While-Program)*5 ICC3f CEf = VIL, OE = VIH — 25 60 mA Flash VCC Active Current (Read-While-Erase)*5 ICC4f CEf = VIL, OE = VIH — 25 60 mA SRAM VCC Active Current ICC1s VCCs = VCCs Max, tCYCLE =10 MHz CE1s = VIL, CE2s = VIH — — 50 mA SRAM VCC Active Current ICC2s CE1s = 0.2 V, CE2s = VCCs – 0.2 V tCYCLE = 10 MHz — — 50 mA tCYCLE = 1 MHz — — 10 mA Flash VCC Standby Current ISB1f VCCf = VCCf Max, CEf = RESET = Vcc ± 0.2 V, VIN < 0.2 V — 0.2 10 µA Flash VCC Standby Current (Standby, RESET) *6 ISB2f VCCf = VCCf Max, RESET = VIL — 0.2 10 µA SRAM VCC Standby Current ISB1s CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V — — 14 µA SRAM VCC Standby Current ISB2s CE2s < 0.2 V — — 14 µA –0.2 — 0.2 V Flash VCCf–0.2 — VCCf+0.2 SRAM 1.6 — VCCs+0.2 Flash VCCf = VCCf Min, IOL = 1.0 mA — — 0.1 V SRAM VCCs = VCCs Min, IOL = 2.1 mA — — 0.4 V Flash VCCf = VCCf Min, IOH = –0.1 mA VCCf–0.1 — — V SRAM VCCs = VCCs Min, IOH = –0.5 mA VCCs–0.5 — — V — 1.4 V Input Low Level VIL Input High Level VIH Flash Output Low Level SRAM Output Low Level Flash Output High Level SRAM Output High Level Flash Low VCC Lock-Out Voltage VOL VOH 1 MHz — — VLKO — — 1.0 mA V *1 : All voltage are referenced to VSS. *2 : IOUT depends on the output load conditions. *3 : The ICC current listed includes both the DC operating current and the frequency dependent component. *4 : ICC active while Embedded Algorithm (program or erase) is in progress. *5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 60 ns. 7 MB84SD23280FA/MB84SD23280FE-70 ■ AC CHARACTERISTICS • CE Timing Parameter Symbol Value Condition Min Standard CE Recover Time — tCCR — 0 — CE Hold Time — tCHOLD — 3 — • Timing Diagram for alternating SRAM to Flash CEf tCCR tCCR CE1s WE tCHOLD tCCR CE2s 8 Unit JEDEC tCHOLD tCCR MB84SD23280FA/MB84SD23280FE-70 ■ SECTOR LOCK/UNLOCK COMMAND The sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. To unlock a sector, the system must write the sector lock/unlock command sequence. Two cycles are first written: addresses are don’t care and data is 60h. During the third cycle, the sector address (SLA) and unlock command (60h) is written, while specifying with address A6 whether that sector should be locked (A6 = VIL) or unlocked (A6 = VIH). After the third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing F0h (reset command). • Flash Characteristics Please refer to “■ 64M FLASH MEMORY for MCP 1.8 V”. • SRAM Characteristics Please refer to “■ 8M SRAM for MCP 1.8 V”. 9 MB84SD23280FA/MB84SD23280FE-70 ■ 64M FLASH MEMORY for MCP 1.8 V 1. Flexible Sector-erase Architecture on FLASH MEMORY : 16KB : 16KB : 16KB : 16KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB 000000h 002000h 004000h 006000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh BANK B SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 BANK A BANK C BANK D • Sixteen 4K words, and one hundred twenty-six 32K words. • Individual-sector, multiple-sector, or bulk-erase capability. Sector Architecture 10 SA67 : 64KB SA68 : 64KB SA69 : 64KB SA70 : 64KB SA71 : 64KB SA72 : 64KB SA73 : 64KB SA74 : 64KB SA75 : 64KB SA76 : 64KB SA77 : 64KB SA78 : 64KB SA79 : 64KB SA80 : 64KB SA81 : 64KB SA82 : 64KB SA83 : 64KB SA84 : 64KB SA85 : 64KB SA86 : 64KB SA87 : 64KB SA88 : 64KB SA89 : 64KB SA90 : 64KB SA91 : 64KB SA92 : 64KB SA93 : 64KB SA94 : 64KB SA95 : 64KB SA96 : 64KB SA97 : 64KB SA98 : 64KB SA99 : 64KB SA100: 64KB SA101: 64KB SA102: 64KB SA103: 64KB SA104: 64KB SA105: 64KB SA106: 64KB SA107: 64KB SA108: 64KB SA109: 64KB SA110: 64KB SA111: 64KB SA112: 64KB SA113: 64KB SA114: 64KB SA115: 64KB SA116: 64KB SA117: 64KB SA118: 64KB SA119: 64KB SA120: 64KB SA121: 64KB SA122: 64KB SA123: 64KB SA124: 64KB SA125: 64KB SA126: 64KB SA127: 64KB SA128: 64KB SA129: 64KB SA130: 16KB SA131: 16KB SA132: 16KB SA133: 16KB 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3FA000h 3FC000h 3FE000h 3FFFFFh MB84SD23280FA/MB84SD23280FE-70 • FlexBankTM Architecture Bank Quantity Size 4 8K words 31 32K words B 32 32K words C 32 32K words 31 32K words 4 8K words A D • Simultaneous Operation Case 1 2 3 4 5 6 7 Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode * Bank 2 Status Read mode Autoselect mode Program mode Erase mode * Read mode Read mode Read mode * : By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) meant to specify each of the Banks. 11 MB84SD23280FA/MB84SD23280FE-70 • Sector Address Table Bank Bank D Sector Sector Size (×16) Address Range SA0 8 Kwords 000000h to 001FFFh SA1 8 Kwords 002000h to 003FFFh SA2 8 Kwords 004000h to 005FFFh SA3 8 Kwords 006000h to 007FFFh SA4 32 Kwords 008000h to 00FFFFh SA5 32 Kwords 010000h to 017FFFh SA6 32 Kwords 018000h to 01FFFFh SA7 32 Kwords 020000h to 027FFFh SA8 32 Kwords 028000h to 02FFFFh SA9 32 Kwords 030000h to 037FFFh SA10 32 Kwords 038000h to 03FFFFh SA11 32 Kwords 040000h to 047FFFh SA12 32 Kwords 048000h to 04FFFFh SA13 32 Kwords 050000h to 057FFFh SA14 32 Kwords 058000h to 05FFFFh SA15 32 Kwords 060000h to 067FFFh SA16 32 Kwords 068000h to 06FFFFh SA17 32 Kwords 070000h to 077FFFh SA18 32 Kwords 078000h to 07FFFFh SA19 32 Kwords 080000h to 087FFFh SA20 32 Kwords 088000h to 08FFFFh SA21 32 Kwords 090000h to 097FFFh SA22 32 Kwords 098000h to 09FFFFh SA23 32 Kwords 0A0000h to 0A7FFFh SA24 32 Kwords 0A8000h to 0AFFFFh SA25 32 Kwords 0B0000h to 0B7FFFh SA26 32 Kwords 0B8000h to 0BFFFFh SA27 32 Kwords 0C0000h to 0C7FFFh SA28 32 Kwords 0C8000h to 0CFFFFh SA29 32 Kwords 0D0000h to 0D7FFFh SA30 32 Kwords 0D8000h to 0DFFFFh SA31 32 Kwords 0E0000h to 0E7FFFh SA32 32 Kwords 0E8000h to 0EFFFFh SA33 32 Kwords 0F0000h to 0F7FFFh SA34 32 Kwords 0F8000h to 0FFFFFh (Continued) 12 MB84SD23280FA/MB84SD23280FE-70 Bank Bank C Sector Sector Size (×16) Address Range SA35 32 Kwords 100000h to 107FFFh SA36 32 Kwords 108000h to 10FFFFh SA37 32 Kwords 110000h to 117FFFh SA38 32 Kwords 118000h to 11FFFFh SA39 32 Kwords 120000h to 127FFFh SA40 32 Kwords 128000h to 12FFFFh SA41 32 Kwords 130000h to 137FFFh SA42 32 Kwords 138000h to 13FFFFh SA43 32 Kwords 140000h to 147FFFh SA44 32 Kwords 148000h to 14FFFFh SA45 32 Kwords 150000h to 157FFFh SA46 32 Kwords 158000h to 15FFFFh SA47 32 Kwords 160000h to 167FFFh SA48 32 Kwords 168000h to 16FFFFh SA49 32 Kwords 170000h to 177FFFh SA50 32 Kwords 178000h to 17FFFFh SA51 32 Kwords 180000h to 187FFFh SA52 32 Kwords 188000h to 18FFFFh SA53 32 Kwords 190000h to 197FFFh SA54 32 Kwords 198000h to 19FFFFh SA55 32 Kwords 1A0000h to 1A7FFFh SA56 32 Kwords 1A8000h to 1AFFFFh SA57 32 Kwords 1B0000h to 1B7FFFh SA58 32 Kwords 1B8000h to 1BFFFFh SA59 32 Kwords 1C0000h to 1C7FFFh SA60 32 Kwords 1C8000h to 1CFFFFh SA61 32 Kwords 1D0000h to 1D7FFFh SA62 32 Kwords 1D8000h to 1DFFFFh SA63 32 Kwords 1E0000h to 1E7FFFh SA64 32 Kwords 1E8000h to 1EFFFFh SA65 32 Kwords 1F0000h to 1F7FFFh SA66 32 Kwords 1F8000h to 1FFFFFh (Continued) 13 MB84SD23280FA/MB84SD23280FE-70 Bank Bank B Sector Sector Size (×16) Address Range SA67 32 Kwords 200000h to 207FFFh SA68 32 Kwords 208000h to 20FFFFh SA69 32 Kwords 210000h to 217FFFh SA70 32 Kwords 218000h to 21FFFFh SA71 32 Kwords 220000h to 227FFFh SA72 32 Kwords 228000h to 22FFFFh SA73 32 Kwords 230000h to 237FFFh SA74 32 Kwords 238000h to 23FFFFh SA75 32 Kwords 240000h to 247FFFh SA76 32 Kwords 248000h to 24FFFFh SA77 32 Kwords 250000h to 257FFFh SA78 32 Kwords 258000h to 25FFFFh SA79 32 Kwords 260000h to 267FFFh SA80 32 Kwords 268000h to 26FFFFh SA81 32 Kwords 270000h to 277FFFh SA82 32 Kwords 278000h to 27FFFFh SA83 32 Kwords 280000h to 287FFFh SA84 32 Kwords 288000h to 28FFFFh SA85 32 Kwords 290000h to 297FFFh SA86 32 Kwords 298000h to 29FFFFh SA87 32 Kwords 2A0000h to 2A7FFFh SA88 32 Kwords 2A8000h to 2AFFFFh SA89 32 Kwords 2B0000h to 2B7FFFh SA90 32 Kwords 2B8000h to 2BFFFFh SA91 32 Kwords 2C0000h to 2C7FFFh SA92 32 Kwords 2C8000h to 2CFFFFh SA93 32 Kwords 2D0000h to 2D7FFFh SA94 32 Kwords 2D8000h to 2DFFFFh SA95 32 Kwords 2E0000h to 2E7FFFh SA96 32 Kwords 2E8000h to 2EFFFFh SA97 32 Kwords 2F0000h to 2F7FFFh SA98 32 Kwords 2F8000h to 2FFFFFh (Continued) 14 MB84SD23280FA/MB84SD23280FE-70 (Continued) Bank Bank A Sector Sector Size (×16) Address Range SA99 32 Kwords 300000h to 307FFFh SA100 32 Kwords 308000h to 30FFFFh SA101 32 Kwords 310000h to 317FFFh SA102 32 Kwords 318000h to 31FFFFh SA103 32 Kwords 320000h to 327FFFh SA104 32 Kwords 328000h to 32FFFFh SA105 32 Kwords 330000h to 337FFFh SA106 32 Kwords 338000h to 33FFFFh SA107 32 Kwords 340000h to 347FFFh SA108 32 Kwords 348000h to 34FFFFh SA109 32 Kwords 350000h to 357FFFh SA110 32 Kwords 358000h to 35FFFFh SA111 32 Kwords 360000h to 367FFFh SA112 32 Kwords 368000h to 36FFFFh SA113 32 Kwords 370000h to 377FFFh SA114 32 Kwords 378000h to 37FFFFh SA115 32 Kwords 380000h to 387FFFh SA116 32 Kwords 388000h to 38FFFFh SA117 32 Kwords 390000h to 397FFFh SA118 32 Kwords 398000h to 39FFFFh SA119 32 Kwords 3A0000h to 3A7FFFh SA120 32 Kwords 3A8000h to 3AFFFFh SA121 32 Kwords 3B0000h to 3B7FFFh SA122 32 Kwords 3B8000h to 3BFFFFh SA123 32 Kwords 3C0000h to 3C7FFFh SA124 32 Kwords 3C8000h to 3CFFFFh SA125 32 Kwords 3D0000h to 3D7FFFh SA126 32 Kwords 3D8000h to 3DFFFFh SA127 32 Kwords 3E0000h to 3E7FFFh SA128 32 Kwords 3E8000h to 3EFFFFh SA129 32 Kwords 3F0000h to 3F7FFFh SA130 8 Kwords 3F8000h to 3F9FFFh SA131 8 Kwords 3FA000h to 3FBFFFh SA132 8 Kwords 3FC000h to 3FDFFFh SA133 8 Kwords 3FE000h to 3FFFFFh 15 MB84SD23280FA/MB84SD23280FE-70 • Sector Protection Verify Autoselect Codes Table Type Manufacture’s Code Device Code Extended Device Code*1 Sector lock/ unlock A21 to A13 A7 A6 A5 A4 A3 A2 A1 A0 Code (HEX) BA*2 L L L L L L L L 04h 2 L L L L L L L H 227Eh BA L L L L H H H L 2224h BA L L L L H H H H 2201h Sector Addresses L L L L L L H L 01h*2 BA* Legend: L = VIL, H = VIH. See “■DC CHARACTERISTICS” for voltage levels. *1: A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh *2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. 16 MB84SD23280FA/MB84SD23280FE-70 • Flash Memory Command Definitions Command Sequence Bus Write Cycles Req’d First Bus Write Cycle Second Write Cycle Third Write Fourth Write Cycle Cycle Fifth Write Cycle Sixth Write Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read / Reset 1 XXXh F0h RA RD — — — — — — — — Read / Reset 3 555h AAh 2AAh 55h 555h F0h RA RD — — — — Autoselect 3 555h AAh 2AAh 55h (BA) 555h 90h — — — — — — Program 4 555h AAh 2AAh 55h 555h A0h PA PD — — — — Chip Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h Sector Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h Erase Suspend 1 BA B0h — — — — — — — — — — Erase Resume 1 BA 30h — — — — — — — — — — Fast Program 2 XXXh A0 PA PD Set to Fast Mode 3 555h AAh 2AAh 55h 555h 20h — — — — — — Reset from Fast Mode *1 2 BA 90h XXXh F0h*2 — — — — — — — — Sector Lock/Unlock 3 XXXh 60h XXXh 60h SLA 60h — — — — — — Query 1 (BA) 55h 98h — — — — — — — — — — Legend: RA = Address of the memory location to be read. PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, and A14 will uniquely select any sector. BA = Bank Address. Address setted by A22, A21 will select Bank A, Bank B, Bank C and Bank D. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of write pulse. CR = Configuration Register address bits A19 to A12. *1: This command is valid during Fast Mode. *2: The data “00h” is also acceptable. Notes: • Address bits A21 to A11 = X = “H” or “L” for all address commands except for PA, SA, BA. • Bus operations are defined in “■ DEVICE BUS OPERATION”. • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 17 MB84SD23280FA/MB84SD23280FE-70 2. AC Characteristics • Read Operations Parameter Symbol Value Unit JEDEC Standard Min Max Access Time from CEf Low — tCE 70 ns Access Time *1 — tACC 70 ns Output Enable to Output Valid — tOE 20 ns 0 ns — tOEH 10 ns — tOEZ 10 ns Output Enable Hold Time Read Toggle and Data Polling Output Enable to High-Z *2 *1 : Access Time is from the last of either stable addresses. *2 : Not 100% tested. • Hardware Reset (RESET) Parameter Value Unit JEDEC Standard Min Max RESET Pin Low (During Embedded Algorithms) to Read Mode* — tREADY 20 µs RESET Pin Low (NOT During Embedded Algorithms) to Read Mode* — tREADY 500 ns RESET Pulse Width — tRP 500 ns Reset High Time Before Read* — tRH 200 ns RESET Low to Standby Mode — tRPD 20 µs * : Not 100% tested. 18 Symbol MB84SD23280FA/MB84SD23280FE-70 • Erase/Program Operations Symbol Value Parameter Unit JEDEC Standard Min Typ Max Write Cycle Time*1 tAVAV tWC 80 ns Address Setup Time*2 tAVWL tAS 0 ns Address Hold Time*2 tWLAX tAH 45 ns Data Setup Time tDVWH tDS 45 ns Data Hold Time tWHDX tDH 0 ns Read Recovery Time Before Write tGHWL tGHWL 0 ns CE Hold Time tWHEH tCH 0 ns Write Pulse Width tEHWH tWP 50 ns Write Pulse Width High tWHWL tWPH 30 ns — tSR/W 0 ns tWHWH1 tWHWH1 8 µs tWHWH2 0.5 tWHWH2 67.0 Latency Between Read and Write Operations Programming Operation*3 Sector Erase Operation*3, *4 Chip Erase Operation*3, *4 VCC Setup Time CE Setup Time to WE s — tVCS 50 µs tELWL tCS 0 ns *1 : Not 100% tested. *2 : Addresses are latched on the falling edge of WE. *3 : See the “Erase and Programming Performance” section in “BDS64xF” datasheet for more information. *4 : Does not include the preprogramming time. 19 MB84SD23280FA/MB84SD23280FE-70 3. Erase and Programming Performance Value Parameter Unit Typ Max Sector Erase Time — 0.5 2.0 s Excludes programming prior to erasure Word Programming Time — 6 100 µs Excludes system level overhead Chip Programming Time — 25.2 95 s Excludes system level overhead 100,000 — — cycle Erase/Program Cycle Note: Typical Erase Conditions: TA = + 25°C, VCCf = 1.8 V Typical Program Conditions: TA = + 25°C, VCCf = 1.8 V, Data = checker 20 Comments Min — MB84SD23280FA/MB84SD23280FE-70 • Read Mode CEf tOE OE tOEH WE tCE DQ15 to DQ0 tOEZ Valid RD tACC RA A21 to A0 tCAS Note: RA = Read Address, RD = Read Data. • Reset Timings CEf, OE tRH RESET tRP tREADY Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms CEf, OE tREADY RESET tRP 21 MB84SD23280FA/MB84SD23280FE-70 • Program Operation Timings Program Command Sequence (last two cycles) Address 555h VA PA Data A0h Read Status Data VA In Progress PD Complete tDS tDH CEf tCH OE tWP WE tWHWH1 tCS tWPH tWC tVCS VCCf Notes : • PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. • “In progress” and “complete” refer to status of program operation in “MBM29BS64LF” Data sheet. • A21 to A12 are don’t care during command sequence unlock cycles. 22 MB84SD23280FA/MB84SD23280FE-70 • Chip/Sector Erase Command Sequence Erase Command Sequence (last two cycles) Address Data VA SA 2AAh Read Status Data 555h for chip erase 10h for chip erase 555h/55h 10h/30h VA In Progress Complete tDS tDH CEf tCH OE tWP WE tWHWH2 tCS tWPH tWC tVCS VCCf Notes : • SA is the sector address for Sector Erase. • Address bits A21 to A12 are don’t cares during unlock cycles in the command sequence. 23 MB84SD23280FA/MB84SD23280FE-70 • Data Polling Timings (During Embedded Algorithm) tCEZ tCE CEf tCH tOEZ tOE OE tOEH WE tACC Address VA VA Status Data Status Data Note : VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data Polling will output true data. 24 MB84SD23280FA/MB84SD23280FE-70 • Toggle Bit Timings (During Embedded Algorithm) tCEZ tCE CEf tCH tOEZ tOE OE tOEH WE tACC Address VA VA Status Data Status Data Note : VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 25 MB84SD23280FA/MB84SD23280FE-70 • Bank-to-Bank Read/Write Cycle Timings Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank tWC tRC Begin another write or program command sequence tRC tWC CEf OE tOE tOEH tGHWL WE tWPH tWP tDS tDH Data tOEZ tACC PD/30h tOEH AAh RD RD tSR/W Address PA/SA RA RA 555h Note: Break points in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. 26 MB84SD23280FA/MB84SD23280FE-70 ■ 8M SRAM for MCP 1.8 V 1. AC Characteristics • Read Cycle (SRAM) Parameter Symbol Value Min Max Unit Read Cycle Time tRC 70 — ns Address Access Time tAA — 70 ns Chip Enable (CE1s) Access Time tCO1 — 70 ns Chip Enable (CE2s) Access Time tCO2 — 70 ns Output Enable Access Time tOE — 35 ns LB, UB to Output Valid tBA — 70 ns Chip Enable (CE1s Low and CE2s High) to Output Active tCOE 5 — ns Output Enable Low to Output Active tOEE 0 — ns LB, UB Enable Low to Output Active tBE 5 — ns Chip Enable (CE1s High or CE2s Low) to Output High-Z tOD — 25 ns Output Enable High to Output High-Z tODO — 25 ns LB, UB Output Enable to Output High-Z tBD — 25 ns Output Data Hold Time tOH 5 — ns Note: Test Conditions–Output Load:1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 1.8 V Timing measurement reference level Input: 0.5 × VCCs Output: 0.5 × VCCs 27 MB84SD23280FA/MB84SD23280FE-70 • Read Cycle (SRAM) tRC Address tAA tOH tCO1 CE1s tCOE tOD tCO2 CE2s tOD tOE OE tODO tOEE LB, UB tBD tBA tBE tCOE DQ Note: WE remains High for the read cycle. 28 Valid Data Output MB84SD23280FA/MB84SD23280FE-70 • Write Cycle (SRAM) Parameter Symbol Value Min Max Unit Write Cycle Time tWC 70 — ns Write Pulse Width tWP 55 — ns CE1s to End of Write tCW1 55 — ns CE2s to End of Write tCW2 55 — ns Address valid to End of Write tAW 55 — ns LB, UB to End of Write tBW 55 — ns Address Setup Time tAS 0 — ns Write Recovery Time tWR 0 — ns WE Low to Output High-Z tODW — 25 ns WE High to Output Active tOEW 0 — ns Data Setup Time tDS 30 — ns Data Hold Time tDH 0 — ns 29 MB84SD23280FA/MB84SD23280FE-70 • Write Cycle*1 (WE control) (SRAM) tWC Address tAS tWP tWR WE tAW tCW CE1s CE2s tCW tBW LB, UB tOEW tODW DOUT *2 *3 tDS DIN *4 tDH Valid Data Input *4 *1 : If OE is High during the write cycle, the outputs will remain at high impedance. *2 : If CE1s goes Low (or CE2s goes High) coincident with or after WE goes Low, the output will remain at high impedance. *3 : If CE1s goes High (or CE2s goes Low) coincident with or before WE goes High, the output will remain at high impedance. *4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 30 MB84SD23280FA/MB84SD23280FE-70 • Write Cycle*1 (CE1s control) (SRAM) tWC Address tAS tWP tWR WE tAW tCW CE1s CE2s tCW tBW LB, UB tBE tCOE tODW DOUT tDS DIN *2 tDH Valid Data Input *2 *1: If OE is High during the write cycle, the outputs will remain at high impedance. *2: Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 31 MB84SD23280FA/MB84SD23280FE-70 • Write Cycle*1 (CE2s Control) (SRAM) tWC Address tAS tWP tWR WE tCW CE1s tAW CE2s tCW tBW LB, UB tBE tCOE tODW DOUT tDS DIN *2 tDH Valid Data Input *2 *1 : If OE is High during the write cycle, the outputs will remain at high impedance. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 32 MB84SD23280FA/MB84SD23280FE-70 • Write Cycle*1 (LB, UB Control) (SRAM) tWC Address tWP tWR WE tCW CE1s tCW CE2s tAW tAS tBW LB, UB tBE tCOE tODW DOUT tDS DIN *2 tDH Valid Data Input *2 *1 : If OE is High during the write cycle, the outputs will remain at high impedance. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 33 MB84SD23280FA/MB84SD23280FE-70 2. Data Retention Characteristics (SRAM) Parameter Symbol Data Retention Supply Voltage Standby Current VDH = 1.8 V Chip Deselect to Data Retention Mode Time Recovery Time Value Unit Min Typ Max VDH 1.0 — 1.95 V IDDS2 — 0.3 14 µA tCDR 0 — — ns tR tRC — — ns Note : tRC: Read cycle time • CE1s Controlled Data Retention Mode *1 VCCs DATA RETENTION MODE 1.65 V VIH VDH *2 *2 VCCS – 0.2 V CE1s tCDR tR VSS *1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to VCCs–0.2 V or VSS to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to VCCs+0.3 V. *2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition of VCCs from Vccs Max to VIH Min level. 34 MB84SD23280FA/MB84SD23280FE-70 • CE2s Controlled Data Retention Mode* VCCs DATA RETENTION MODE 1.65 V VDH VIH tCDR tR CE2s VIL 0.2 V VSS * : In CE2s controlled data retention mode, input and input/output pins can be used between –0.3 V to Vccs+0.3 V. 35 MB84SD23280FA/MB84SD23280FE-70 ■ PIN CAPACITANCE Parameter Symbol Test Setup Value Min Typ Max Input Capacitance CIN VIN = 0 — — 16.0 pF Output Capacitance COUT VOUT = 0 — — 22.0 pF Control Pin Capacitance CIN2 VIN = 0 — — 18.0 pF Note : Test conditions TA = + 25 °C, f = 1.0 MHz ■ HANDLING OF PACKAGE Please handle this package carefully since the sides of package create acute angles. ■ CAUTION • The high voltage (VID) cannot apply to address pins and control pins. 36 Unit MB84SD23280FA/MB84SD23280FE-70 ■ ORDERING INFORMATION MB84SD23280 FA/E -70 PBS PACKAGE TYPE PBS = 73-ball FBGA SPEED OPTION Device Revision DEVICE NUMBER/DESCRIPTION 64 Mega-bit (4 M × 16-bit) Dual Operation Flash Memory 1.8 V-only Read, Program, and Erase 8 Mega-bit (512K × 16-bit) SRAM 37 MB84SD23280FA/MB84SD23280FE-70 ■ PACKAGE DIMENSION 73-ball plastic FBGA (BGA-73P-M03) 11.60±0.10(.457±.004) 0.20(.008) S B B +0.15 –0.10 +.006 –.004 1.19 .047 (Seated height) 0.80(.031) REF 0.40(.016) REF 10 9 0.80(.031) REF 8 7 A 6 8.00±0.10 (.315±.004) 5 0.40(.016) REF 4 3 0.10(.004) S 2 1 INDEX-MARK AREA 0.39±0.10 (Stand off) (.015±.004) M L K J H G F E D S C B A INDEX BALL 0.20(.008) S A +0.10 73-ø0.45 –.005 +.004 ø0.08(.003) M S AB 73-ø0.18 –.002 0.10(.004) S C 2003 FUJITSU LIMITED B73003S-c-1-1 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 38 MB84SD23280FA/MB84SD23280FE-70 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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