EMIF02-MIC03F2 ® 2 LINE EMI FILTER AND ESD PROTECTION IPAD™ MAIN PRODUCT CHARACTERISTICS: Where EMI filtering in ESD sensitive equipment is required : ■ Mobile phones and communication systems ■ Computers, printers and MCU Boards DESCRIPTION The EMIF02-MIC03 is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF02 Flip-Chip packaging means the package size is equal to the die size. This filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up 15 kV. Flip-Chip package BENEFITS ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency in EMI filtering ■ Very low PCB space consuming: 1.07 mm x 1.47 mm ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression ■ High reliability offered by monolithic integration ■ High reducing of parasitic elements through integration & wafer level packaging PIN CONFIGURATION (bump side) 3 2 1 I2 COMPLIES WITH THE FOLLOWING STANDARDS: IEC 61000-4-2 Level 4 on input pins 15 kV (air discharge) 8 kV (contact discharge) Level 1 on output pins 2 kV (air discharge) 2 kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3 I1 B GND O2 A O1 C BASIC CELL CONFIGURATION Low-pass Filter Input Output Ri/o = 68 Ω Cline = 100 pF GND GND GND TM: IPAD is a trademark of STMicroelectronics. October 2004 REV. 1 1/6 EMIF02-MIC03F2 ABSOLUTE RATINGS (limiting values) Symbol Tj Parameter and test conditions Value Unit 125 °C Maximum junction temperature Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to 150 °C ELECTRICAL CHARACTERISTICS (Tamb = 25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage I IPP VCL VBR VRM VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between Input & Output Cline Input capacitance per line Symbol IR IRM IRM IR VRM VBR VCL V IPP Test conditions Min. Typ. 6 8 Max. Unit VBR IR = 1 mA IRM VRM = 3 V per line RI/O Tolerance ± 20 % 68 Ω Cline VR = 0 V 100 pF V 500 Fig. 1: S21 (dB) attenuation measurements and Aplac simulation. nA Fig. 2: Analog crosstalk measurements. 0.00 dB -10.00 0.00 dB -5.00 -10.00 -20.00 -15.00 -30.00 -20.00 -25.00 -40.00 -30.00 -50.00 -35.00 -60.00 -40.00 -70.00 -45.00 -50.00 100.0k 2/6 1.0M 10.0M f/Hz 100.0M 1.0G -80.00 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz ® EMIF02-MIC03F2 Fig. 3: ESD response to IEC61000-4-2 (+15kV air discharge) on one input V(in) and one output V(out). Fig. 4: ESD response to IEC61000-4-2 (–15kV air discharge) on one input V(in) and one output V(out). Fig. 5: Line capacitance versus applied voltage. C(pF) 140 120 F=1MHz Vosc=30mVRMS Tj=25°C 100 80 60 40 20 VR(V) 0 0 ® 1 2 3 4 5 3/6 EMIF02-MIC03F2 Aplac model IN1 Rmic Rbump Lbump Lmic Lbump Rbump GND OUT1 Lsub model = D1 model = D2 Rsub Rbump GND model = D3 Lbump model = D1 model = D2 Lgnd Cgnd IN2 Rgnd OUT2 Rbump Lbump Rmic Lmic Lbump Rbump Ground return EMIF02-MIC03F1 model Aplac parameters Model D1 Model D3 Model D2 aplacvar Rmic 68 CJO=Cdiode1 CJO=Cdiode3 CJO=Cdiode2 aplacvar Lmic 10p BV=7 BV=7 BV=7 aplacvar Cdiode1 100pF IBV=1u IBV=1u IBV=1u aplacvar Cdiode2 3.6pF IKF=1000 IKF=1000 IKF=1000 aplacvar Cdiode3 1.17nF IS=10f IS=10f IS=10f aplacvar Lbump 50pH ISR=100p ISR=100p ISR=100p aplacvar Rbump 20m N=1 N=1 N=1 aplacvar Rsub 0.5m M=0.3333 M=0.3333 M=0.3333 aplacvar Rgnd 10m RS=0.7 RS=0.12 RS=0.3 aplacvar Lgnd 50pH VJ=0.6 VJ=0.6 VJ=0.6 aplacvar Cgnd 0.15pF TT=50n TT=50n TT=50n aplacvar Lsub 10pH ORDER CODE EMIF yy - xxx zz F x 1: Pitch = 500µm Bump = 315µm 2: Leadfree Pitch = 500µm Bump = 315µm EMI Filter Number of lines Flip Chip x: resistance value (Ohms) z: capacitance value / 10(pF) or Application (3 letters) and Version (2 digits) 4/6 ® EMIF02-MIC03F2 PACKAGE MECHANICAL DATA FLIP CHIP 500µm ± 10 650µm ± 50 315µm ± 50 50 0µ m ± 15 1.47mm ± 50µm 250µm ± 10 1.07mm ± 50µm FOOT PRINT RECOMMENDATIONS Copper pad Diameter : 250µm recommended , 300µm max Solder stencil opening : 330µm Solder mask opening recommendation : 340µm min for 300µm copper pad diameter MARKING Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) E x x z y ww ® 5/6 EMIF02-MIC03F2 PACKING Dot identifying Pin A1 location Ø 1.5 ± 0.1 1.75 ± 0.1 ST E ST E ST E xxz yww xxz yww xxz yww 0.73 ± 0.05 3.5 ± 0.1 8 ± 0.3 4 ± 0.1 4 ± 0.1 User direction of unreeling All dimensions in mm In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. OTHER INFORMATION Ordering code Marking Package Weight Base qty Delivery mode EMIF02-MIC03F2 FW Flip-Chip 2.1 mg 5000 Tape & reel (7”) Note: More packing informations are available in the application notes AN1235: ''Flip-Chip: Package description and recommendations for use'' AN1751: "EMI Filters: Recommendations and measurements" REVISION HISTORY Date Revision 14-Oct-2005 1 Changes Initial release. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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