EMIF09-SD01F3 IPAD™ 9 line EMI filter and ESD protection Main application ■ Secure digital memory card in mobile phones and communication systems Description The EMIF09-SD01F3 is a highly integrated array designed to suppress EMI/RFI noise for secure digital memory cards. The EMIF09-SD01F3 is in a flip chip package to offer space saving and high RF performance. Flip-Chip (24 bumps) Pin Configuration (bump side) This low-pass filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 15 kV. This filter also has a low line capacitance to be compatible with high data rate signals. 5 4 3 2 1 A B C Benefits D ■ 9 line EMI low-pass filter and ESD protection ■ High efficiency in EMI filtering ■ Lead free package ■ 400 µm pitch Complies with the following standards: ■ Very low PCB space consumption: < 4 mm2 IEC 61000-4-2: ■ Very thin package: 0.6 mm ■ High reliability offered by monolithic integration ■ Reduction of parasitic elements thanks to CSP integration. Level 4 on external pins 15 kV (air discharge) 8 kV (contact discharge) Level 2 on internal pins 2 kV (air discharge) 2 kV (contact discharge) E MIL STD 833F - Method 3015.7 Class 3 PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION A1 DATA2 B1 CD C1 DAT3_PD D1 WP+CD E1 DATA1 A2 DATA3 B2 CMD C2 WP D2 CLK E2 DATA0 A3 GND_H B3 C3 DAT3_PU D3 GND_C E3 GND_C A4 SDDATA2 B4 SDCD C4 SDWP D4 SDWP+CD E4 SDDATA1 A5 SDDATA3 B5 SDCMD C5 VSD D5 SDCLK E5 SDDATA0 TM: IPAD is a trademark of STMicroelectronics. February 2006 Rev 2 1/8 www.st.com 8 EMIF09-SD01F3 1 Characteristics 1 Characteristics Figure 1. Configuration VSD R15 R14 R12 R13 R11 DAT3_PU CLK SDCMD R2 DATA0 SDDATA0 R3 DATA1 SDDATA1 R4 DATA2 SDDATA2 R5 DATA3 SDDATA3 R6 CD SDCD R7 WP SDWP R8 WP+CD DAT3_PD SDWP+CD R9 R21 GND_H Table 1. SDCLK R1 CMD GND_C Absolute Maximum Ratings Symbol VPP Tj Parameter Value Unit Internal pins (A1, B1, C1, D1, E1, A2, B2, C2, D2, E2, C3) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge External pins (A4, B4, C4, D4, E4, A5, B5, C5, D5, E5) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge 15 8 Junction temperature 125 °C 2 2 kV Top Operating temperature range -30 to + 85 °C Tstg Storage temperature range -55 to 150 °C GND bumps (GND_H and GND_C - A3, D3 and E3) must be connected to ground on the printed circuit board for ESD testing and RF measurements. 2/8 EMIF09-SD01F3 1.1 1 Characteristics Electrical characteristics (Tamb = 25°C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage IPP Peak pulse current Rd Dynamic impedance I IPP VCLVBR VRM IR IRM V IRM IR RI/O Series resistance between Input & Output Cline Input capacitance per line Symbol IPP Test conditions VBR IR = 1 mA IRM VRM = 5 V per line VRMVBR VCL Min. Typ. Max. 14 Unit V 0.5 µA R1, R2, R3, R4, R5, R6, R7, R8, R9 Tolerance ± 20% 40 Ω R11, R12, R13, R14 Tolerance ± 30% 50 kΩ R15 Tolerance ± 30% 15 kΩ R21 Tolerance ± 30% 470 kΩ Cline Vline = 0V, VOSC = 30 mV, F = 1 MHz (under zero light conditions) Figure 2. S21(db) all lines attenuation measurement Figure 3. db 20 pF Analog cross talk measurements db 0.00 0.00 -10.00 -10.00 -20.00 -30.00 -20.00 -40.00 -30.00 -50.00 -60.00 -40.00 F (Hz) -50.00 100.0k 1.0M data0 data2 10.0M F (Hz) -70.00 100.0M data1 data3 1.0G -80.00 100.0k 1.0M 10.0M 100.0M 1.0G data0_data1 3/8 EMIF09-SD01F3 1 Characteristics Figure 4. Digital crosstalk measurement Figure 5. ESD response to IEC61000-4-2 (+15kV air discharge) on one input (VIN) and on one output (VOUT) Output Line 2 200mV/d Vexternal=20V/d Input Line 1 1V/d Vinternal =10V/d 10ns/d 5Gs/s Figure 6. ESD response to IEC61000-4-2 (-15kV air discharge) on one input (VIN) and on one output (VOUT) 100ns/d Figure 7. Line capacitance versus applied voltage Cline (pF) 25 Vexternal=20V/d F = 1 MHz VOSC = 30 mV Tj = 25°C 20 15 10 Vinternal =10V/d 100ns/d 5 Vline (V) 0 0 4/8 2 4 6 8 10 12 14 EMIF09-SD01F3 Figure 8. 2 Ordering information scheme Aplac model data0 Lbump Rbump Rline MODEL = D1 Rbump Lbump sddata0 MODEL = D2 Rsub MODEL = D3 Figure 9. Rbump Rbump Rbump Lbump Lbump Lbump Rgnd Rgnd Rgnd Lgnd Lgnd Lgnd Aplac model variables Variables aplacvar Rline 40 aplacvar C_d1 14.5p aplacvar C_d2 6.5p aplacvar C_d3 303p aplacvar C_d4 14.5p aplacvar Lbump 43pH aplacvar Rbump 17m aplacvar Cbump 150f aplacvar Lgnd 150pH aplacvar Rgnd 10m aplacvar Rsub 5 2 MODEL = D4 Diode D1 BV=7 IBV=1m CJO=C_d1 M=0.28 RS=1.13 VJ=0.6 TT=100n Diode D2 BV=7 IBV=1m CJO=C_d2 M=0.28 RS=0.8 VJ=0.6 TT=100n Diode D3 BV=7 IBV=1m CJO=C_d3 M=0.28 RS=0.37 VJ=0.6 TT=100n Diode D4 BV=7 IBV=1m CJO=C_d4 M=0.28 RS=1.13 VJ=0.6 TT=100n Ordering information scheme EMIF yy - xx zz F3 EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 2 letters = application 2 digits = version Package F = Flip-Chip 3 = Lead free Pitch = 400µm, Bump = 260µm 5/8 EMIF09-SD01F3 3 Package information 3 Package information Figure 10. Mechanical data 400 µm ± 40 605 µm ± 55 1.97 mm ± 30 µm 400 µm ± 40 255 µm± 40 1.97 mm ± 30 µm Figure 11. Foot print recommendations Figure 12. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended 260 µm maximum E Solder mask opening: 300 µm minimum x x z y ww Solder stencil opening : 220 µm recommended Figure 13. Flip-chip tape and reel specifications Dot identifying Pin A1 location 3.5 +/- 0.1 2.11 ST E 2.11 xxz yww xxz yww ST E 6/8 ST E All dimensions in mm xxz yww 8 +/- 0.3 2.11 0.69 +/- 0.05 1.75 +/- 0.1 Ø 1.5 +/- 0.1 4 +/- 0.1 4 +/- 0.1 User direction of unreeling EMIF09-SD01F3 4 Ordering information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 4 Ordering information Part Number Marking Package Weight Base qty Delivery mode EMIF09-SD01F3 GZ Flip-Chip 5.2 mg 5000 Tape and reel (7”) Note: More information is available in the application note : AN1235 :"Flip Chip : Package description and recommendations for use" AN1751 : EMI Filters: Recommendations and measurements 5 Revision history Date Revision Changes 19-Oct-2005 1 Initial release. 09-Feb-2006 2 Tape cavity dimensions added in Figure 13. Other graphics improved. 7/8 EMIF09-SD01F3 5 Revision history Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 8/8