HCF4067B ANALOG SINGLE 16 CHANNEL MULTIPLEXER/DEMULTIPLEXER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LOW ON RESISTANCE : 125Ω (Typ.) OVER 15V p-p SIGNAL INPUT RANGE FOR VDD - VSS = 15V HIGH OFF RESISTANCE : CHANNEL LEAKAGE OF 10pA (Typ.) at VDD - VSS = 10V MATCHED SWITCH CHARACTERISTICS : ∆RON = 5Ω (Typ.) FOR VDD - VSS =15V VERY LOW QUIESCENT POWER DISSIPATION UNDER A DIGITAL CONTROL INPUT AND SUPPLY CONDITIONS : 0.2µW (Typ.) at VDD - VSS = 10V BINARY ADDRESS DECODING ON CHIP QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" SOP ORDER CODES PACKAGE TUBE T&R SOP HCF4067BM1 HCF4067M013TR HCF4067B, analog multiplexer/demultiplexer CMOS, is a digitally controlled analog switches device having low ON impedance, low OFF leakage current and internal address decoding. In addition, the ON resistance is relatively constant over the full input-signal range. HCF4067B ia a 16-channel multiplexer with four binary control inputs A, B, C, D, and an inhibit input, arranged so that any combination of the inputs selects one switch. DESCRIPTION HCF4067B is monolithic integrated circuits fabricated in Metal Oxide Semiconductor technology available in SOP package. PIN CONNECTION September 2002 1/10 HCF4067B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 10, 11, 14, 13 A, B, C, D COMMON OUT/IN INHIBIT 1 15 9, 8, 7, 6, 5, 4, 3, 2, 23, 22, 21, 20, 19, 18, 17, 16 0 to 15 CHANNEL IN/OUT NAME AND FUNCTION Binary Control Inputs Common Out/In Inhibit Input 16 channel In/Out 12 VSS Negative Supply Voltage 24 VDD Positive Supply Voltage FUNCTIONAL DIAGRAM TRUTH TABLE 2/10 A B C D INH SELECTED CHANNEL X L H L H L H L H L H L H L H L H X L L H H L L H H L L H H L L H H X L L L L H H H H L L L L H H H H X L L L L L L L L H H H H H H H H H L L L L L L L L L L L L L L L L NONE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HCF4067B LOGIC DIAGRAM 3/10 HCF4067B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/10 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4067B STATIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C,Typical temperature coefficient for all VDD value is 0.3 %/°C) Test Condition Symbol IL Parameter Resistance ∆RON (between any 2 of 4 switches) OFF (•) Channel Leakage Current Any Channel Off Channel Leakage Current All Channel Off (Common Out/In) C Capacitance Input Output capacitance Feedthrough CONTROL Input Low Voltage VIL VIH II CI VEE (V) VSS (V) Quiescent Supply Current SWITCH RON On Resistance ∆ON VIS (V) Input High Voltage Input Leakage Current Input Capacitance 0 < VI < VDD 0 0 0 0 0 0 Value VDD (V) TA = 25°C Min. -40 to 85°C -55 to 125°C Unit Typ. Max. Min. Max. Min. Max. 5 10 15 20 0.04 0.04 0.04 0.08 5 10 20 100 150 300 600 3000 150 300 600 3000 µA 5 10 15 5 10 15 470 180 125 10 10 5 1050 400 240 1200 500 300 1200 520 300 Ω 18 ±0.1 100 Ω 1000 1000 µA 0 0 18 ±0.1 -5 5 5 55 0.2 VEE = VSS RL = 1KΩ to = VDD VSS thru I < IS 2µA (on 1KΩ all OFF channels) 5 10 15 5 10 15 VI = 0/18V 18 Any Address or Inhibit Input 100 1000 1000 pF 1.5 3 4 3.5 7 11 1.5 3 4 3.5 7 11 ±10-3 ±0.1 5 7.5 1.5 3 4 3.5 7 11 ±1 V V ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V • Determined by minimum feasible leakage measurement for automating testing 5/10 HCF4067B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol SWITCH tpd Parameter Propagation Delay Time (Signal Input to Output) Frequency Response Channel "ON" (Sine Wave Input) at VC (V) = VDD = VDD RL fI (KΩ) (KHz) VI (V) 200 1 5 (•) Value* VSS (V) VDD (V) Typ. Max. 0 5 10 15 30 15 11 60 30 20 0 10 VO 20 Log –––– = -3dB VI Feedthrough (All channels OFF) at VO 20 Log ––– =-40dB VI = VSS Frequency Signal Crosstalk at VC(A) =VDD VO(A) 20 Log ––– =-40dB VI(B) tW Sine Wave Distortion (fIS = 1KHz sine wave) CONTROL(Address or Inhibit) tPLH, tPHL Propagation Delay Time:Address or Inhibit to Signal OUT (Channel Turning ON) tPLH, tPHL Propagation Delay Time:Address or Inhibit to Signal OUT (Channel Turning OFF) Address or Inhibit to Signal Crosstalk VC(B) =VSS 5 10 15 1 5 (•) 1 10 1 1 0.3 10** (*) Typical temperature coefficient for all VDD value is 0.3 %/°C (**) : Both Ends of Channel (•) : Peak to Peak voltage symmetrical about (VDD - VSS) / 2 6/10 0 10 14 VO at Any Channel 60 VO at Common Out/In 20 VO at Any Channel 8 Between Any two (A and B) Channels 1 MHz % ns MHz 0 10 2 (•) 3 (•) 5 (•) 0 5 10 15 0.3 0.2 0.12 5 10 325 135 650 270 15 95 190 5 10 220 90 440 180 15 65 130 10 75 0 0 ns VO at Common Out/In 5 (•) 0 Unit ns ns mV peak HCF4067B APPLICATION INFORMATION In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/R L (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the HCF4067B. When switching from one address to another, some of the ON periods of the channels of the multiplexers will overlap momentarily, which may be objectionable in certain applications. Also, when a channel is turned ON or OFF by an address input, there is a momentary conductive path from the channel to VSS, which will dump some charge from any capacitor connected to the input or output of the channel. The inhibit input turning on a channel will similarly dump some charge to VSS. The amount of charge dumped is mostly a function of the signal level above VSS. Typically, at VDD - VSS = 10V, a 100 pF capacitor connected to the input or output of the channel will lose 3-4% of its voltage at the moment the channel turns ON or OFF. This loss of voltage is essentially independent of the address or inhibit signal transition time, if the transition time is less than 12 ms. When the inhibit signal turns a channel off, there is no change dumping of VSS. Rather, there is a slight rise in the channel voltage level (65 mV typ.) due to the capacitance coupling from inhibit input to channel input or output. Address input also couple some voltage steps onto the channel signal levels. In certain applications, the external load-resistor current may include both VDD and signal line components. To avoid drawing VDD current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.8V (calculated from RON values shown in ELECTRICAL CHARACTERISTICS CHART). No VDD current will flow through RL if the switch current flows into terminal 1 on the HCF4067B. TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) 7/10 HCF4067B WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 8/10 HCF4067B SO-24 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 2.65 a1 0.1 0.104 0.2 a2 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45˚ (typ.) D 15.20 15.60 0.598 0.614 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 S 8 ˚ (max.) L s e3 b1 e a1 b A a2 C c1 E D 13 F 24 1 1 2 PO13T 9/10 HCF4067B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 10/10