ETC HCF40108

HCF40108B
4 x 4 MULTIPORT REGISTER
■
■
■
■
■
■
■
■
■
■
■
■
ONE INPUT AND TWO OUTPUT BUSES
UNLIMITED EXPANSION IN BIT AND WORD
DIRECTION
DATA LINES HAVE LATCHED INPUTS
3-STATE OUTPUTS
SEPARATE CONTROL OF EACH BUS,
ALLOWING SIMULTANEOUS
INDEPENDENT READING AND ANY OF
FOUR REGISTERS ON BUS A AND BUS B
AND INDEPENDENT WRITING INTO ANY
OF THE FOUR REGISTERS
40108B IS PIN-COMPATIBLE WITH
INDUSTRY TYPE MC14580
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40108B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in SOP packages.
HCF40108B is a 4 x 4 multiport register containing
SOP
ORDER CODES
PACKAGE
TUBE
T&R
SOP
HCF40108BM1
HCF40108M013TR
four 4-bit registers, a write address decoder, two
separate read address decoders, and two 3-state
output buses. When the ENABLE input is low, the
corresponding
output
bus
is
switched,
independently of the clock, to a high impedance
state. The high impedance third state provides the
outputs with the capability of being connected to
the bus lines in a bus organized system without
the need for interface or pull-up components.
When the WRITE ENABLE input is high, all data
input lines are latched on the positive transition of
the CLOCK and the data is entered into the word
selected by the write address lines. When WRITE
ENABLE is low, the CLOCK is inhibited and no
new data is entered. In either case, the contents of
any word may be accessed via the read address
lines independent of the state of the CLOCK input.
PIN CONNECTION
September 2002
1/11
HCF40108B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
4, 5, 6, 7
22, 23, 2, 1
20, 19, 18,
17
16
15
21
3
8, 9
Q0A to Q3A Word A Output
Q0B to Q3B Word B Output
D0 to D3
Data Inputs
CLOCK
WRITE
ENABLE
3-STATE B
3-STATE A
WRITE 0,
Clock Input
Write Enable Input
3 State Output
3 State Output
Write Address Inputs
12
Negative Supply Voltage
24
VDD
Positive Supply Voltage
13, 14
2/11
NAME AND FUNCTION
WRITE 1
READ 0B,
READ 1B
READ 0A,
READ 1A
VSS
10, 11
FUNCTIONAL DIAGRAM
SYMBOL
Read Address Inputs
Read Address Inputs
HCF40108B
LOGIC DIAGRAM
3/11
HCF40108B
SCHEMATIC DIAGRAM
4/11
HCF40108B
TRUTH TABLE
CLOCK
X
X
Write Write 1 Write 2
Enable
Read
1A
Read
0A
Read
1B
Read
0B
Enable Enable
A
B
H
S1
S2
S1
S2
S1
S2
H
H
H
S1
S2
S1
S2
S1
S2
H
L
X
X
X
X
X
X
X
L
L
H
L
L
L
H
H
L
H
H
L
L
L
L
H
H
L
H
H
X
X
X
H
L
L
H
H
X
X
X
X
X
X
X
X
H
H
Dn
DnA
QnB
H
H
H
L
L
L
Z
Z
Z
Dn to Word 1 Word 2
word 0
Out
Out
Word 0
Word 1 Word 2
not
Out
Out
altered
Word 2 Word 1
X
Out
Out
X
NC
NC
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
PD
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
5/11
HCF40108B
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Value
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
DC SPECIFICATIONS
Test Condition
Symbol
IL
VOH
VOL
VIH
VIL
IOH
IOL
II
IOZ
CI
Parameter
Quiescent Current
High Level Output
Voltage
Low Level Output
Voltage
VI
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Input
Voltage
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
3-State Output
Leakage Current
Input Capacitance
VO
(V)
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
Value
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
TA = 25°C
Min.
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-40 to 85°C
-55 to 125°C
Min.
Min.
150
300
600
3000
4.95
9.95
14.95
0.05
0.05
0.05
4.95
9.95
14.95
3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
3.5
7
11
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
µA
V
0.05
0.05
0.05
V
V
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
V
mA
mA
0/18
Any Input
18
±10-5
±0.1
±1
±1
µA
0/18
Any Input
18
±10-4
±0.4
±12
±12
µA
5
7.5
Any Input
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
6/11
Max.
150
300
600
3000
0.05
0.05
0.05
3.5
7
11
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
Unit
pF
HCF40108B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
tPHL tPLH Propagation Delay Time
Clock or Write Enable to Q
Propagation Delay Time
Read or Write Address to
Q
tPZH tPHZ 3-State Disable Delay
Time
tPZL tPLZ 3-State Display Delay Time
tTHL tTLH Output Transition Time
tsetup
Setup Time Data to Clock
ts(D)
Setup Time Write Enable
to Clock ts(WE)
Setup Time Write Address
to Clock ts(WA)
tr, ts
thold
Clock Rise and Fall Time
Hold Time Data to Clock
ts(D)
Hold Time Write Enable to
Clock ts(WE)
Hold Time Write Address
to Clock ts(WA)
tW
Clock Pulse Width
Clock or Write Enable
tW(CL)
tW
Clock Pulse Width
Write Address tW(WA)
fCL
Maximum Clock Input
Frequency
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Value (*)
Unit
Min.
Typ.
Max.
720
280
200
600
240
170
200
100
80
260
120
100
200
100
80
0
0
0
250
100
70
250
100
70
360
140
100
300
120
85
100
50
40
130
60
50
100
50
40
-95
-35
-20
125
50
35
125
50
35
110
50
40
135
65
40
165
70
45
175
65
45
150
75
45
3
7
9
ns
ns
ns
ns
ns
ns
ns
15
5
5
220
100
80
270
130
80
330
140
90
350
130
90
300
150
90
1.5
3.5
4.5
ns
ns
ns
ns
ns
ns
ns
MHz
7/11
HCF40108B
TEST CIRCUIT
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VDD
tPZH, tPHZ
VSS
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM : ENABLE AND DISABLE TIME
8/11
HCF40108B
SWITCHING WAVEFORM
9/11
HCF40108B
SO-24 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
MAX.
2.65
a1
0.1
0.104
0.2
a2
0.004
0.008
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
0.020
c1
45˚ (typ.)
D
15.20
15.60
0.598
0.614
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
13.97
0.550
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
S
8 ˚ (max.)
L
s
e3
b1
e
a1
b
A
a2
C
c1
E
D
13
F
24
1
1
2
PO13T
10/11
HCF40108B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
© http://www.st.com
11/11