M48Z35AV 5.0V or 3.3V, 256Kbit (32Kbit x 8) ZEROPOWER® SRAM Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time ■ Battery low flag (BOK) ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltage: (VPFD = Power-fail deselect voltage) – M48Z35AV: 2.7V ≤ VPFD ≤ 3.0V ■ Self-contained battery in the CAPHAT™ DIP package ■ Packaging includes a 28-lead SOIC and SNAPHAT® top (to be ordered separately) ■ Pin and function compatible with JEDEC standard 32Kbit x 8 SRAMs ■ SOIC package provides direct connection for a SNAPHAT top which contains the battery ■ 28 1 PCDIP28 (PC) Battery CAPHAT SNAPHAT (SH) battery 28 1 RoHS compliant – Lead-free second level interconnect November 2007 SOH28 (MH) Rev 6 1/24 www.st.com 1 Contents M48Z35AV Contents 1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 M48Z35AV List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PMDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data. . . . . . . . . . . . . . . . 18 SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 19 SH – 4-pin SNAPHAT housing for 48mAh battery, pack. mech. data . . . . . . . . . . . . . . . . 20 SH – 4-pin SNAPHAT housing for 120 mAh battery, pack. mech. data . . . . . . . . . . . . . . . 21 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3/24 List of figures M48Z35AV List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. 4/24 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 BOK check routine example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 18 SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 19 SH – 4-pin SNAPHAT housing for 48mAh battery, package outline. . . . . . . . . . . . . . . . . . 20 SH – 4-pin SNAPHAT housing for 120mAh battery, package outline. . . . . . . . . . . . . . . . . 21 M48Z35AV 1 Summary Summary The M48Z35AV ZEROPOWER® RAM is a 32Kbit x 8, non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z35AV is a non-volatile pin and function equivalent to any JEDEC standard 32K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28 pin 600mil DIP CAPHAT™ houses the M48Z35AV silicon with a long life lithium button cell in a single package. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is “M4Z28BR00SH1.” Figure 1. Logic diagram VCC 15 8 A0-A14 W DQ0-DQ7 M48Z35AV E G VSS AI02781B 5/24 Summary M48Z35AV Table 1. Signal names A0-A14 Address inputs DQ0-DQ7 Figure 2. Data inputs / outputs E Chip enable input G Output enable input W WRITE enable input VCC Supply voltage VSS Ground DIP connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z35AV 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI02782B Figure 3. SOIC connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z35AV 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AI02783 6/24 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 M48Z35AV Figure 4. Summary Block diagram A0-A14 LITHIUM CELL POWER VOLTAGE SENSE AND SWITCHING CIRCUITRY 32K x 8 SRAM ARRAY DQ0-DQ7 E VPFD W G VCC VSS AI01619B 7/24 Operating modes 2 M48Z35AV Operating modes The M48Z35AV also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single power supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately VSO, the control circuitry connects the battery which maintains data until valid power returns. Table 2. Operating modes Mode VCC Deselect WRITE READ 3.0 to 3.6V READ Deselect VSO to VPFD Deselect (min)(1) ≤ VSO(1) E G W DQ0-DQ7 Power VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active X X X High Z CMOS standby X X X High Z Battery back-up mode 1. See Table 10 on page 17 for details. Note: X = VIH or VIL; VSO = Battery back-up switchover voltage. 2.1 Read mode The M48Z35AV is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 264,144 locations in the static storage array. Thus, the unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. 8/24 M48Z35AV Figure 5. Operating modes Read mode AC waveforms tAVAV VALID A0-A14 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI00925 Note: WRITE enable (W) = High. Table 3. Read mode AC characteristics M48Z35AV Parameter(1) Symbol –100 Min Unit Max tAVAV READ cycle time tAVQV Address valid to output valid 100 ns tELQV Chip enable low to output valid 100 ns tGLQV Output enable low to output valid 50 ns (2) 100 ns Chip enable low to output transition 10 ns tGLQX(2) tEHQZ(2) tGHQZ(2) Output enable low to output transition 5 ns tAXQX Address transition to output transition tELQX Chip enable high to output Hi-Z 50 ns Output enable high to output Hi-Z 40 ns 10 ns 1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 10 on page 15). 2.2 Write mode The M48Z35AV is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during 9/24 Operating modes M48Z35AV WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. Write enable controlled, write mode AC waveforms tAVAV A0-A14 VALID tAVWH tWHAX tAVEL E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI00926 Figure 7. Chip enable controlled, write mode AC waveforms tAVAV VALID A0-A14 tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI00927 10/24 M48Z35AV Operating modes Table 4. Write mode AC characteristics M48Z35AV Parameter(1) Symbol –100 Min tAVAV WRITE cycle time tAVWL Unit Max 100 ns Address valid to WRITE enable low 0 ns tAVEL Address valid to chip enable low 0 ns tWLWH WRITE enable pulse width 80 ns tELEH Chip enable low to chip enable high 80 ns tWHAX WRITE enable high to address transition 10 ns tEHAX Chip enable high to address transition 10 ns tDVWH Input valid to WRITE enable high 50 ns tDVEH Input valid to chip enable high 50 ns tWHDX WRITE enable high to input transition 5 ns tEHDX Chip enable high to input transition 5 ns tWLQZ (2)(3) WRITE enable low to output Hi-Z 50 ns tAVWH Address valid to WRITE enable high 80 ns tAVEH Address valid to chip enable high 80 ns WRITE enable high to output transition 10 ns tWHQX(2)(3) 1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 10 on page 15). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 2.3 Data retention mode With valid VCC applied, the M48Z35AV operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as “Don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z35AV may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z35AV for an accumulated period of at least 10 years (at 25°C) when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD(min) plus tREC(min). Normal RAM operation can resume tREC after VCC exceeds VPFD(max). 11/24 Operating modes M48Z35AV Also, as VCC rises, the battery voltage is checked. If the voltage is less than approximately 2.5V, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 8 illustrates how a BOK check routine could be structured. For more information on Battery Storage Life refer to the Application Note AN1012. Figure 8. BOK check routine example POWER-UP READ DATA AT ANY ADDRESS WRITE DATA COMPLEMENT BACK TO SAME ADDRESS READ DATA AT SAME ADDRESS AGAIN IS DATA COMPLEMENT OF FIRST READ? (BATTERY OK) YES NO (BATTERY LOW) NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED) WRITE ORIGINAL DATA BACK TO SAME ADDRESS CONTINUE AI00607 12/24 M48Z35AV 2.4 Operating modes VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). Figure 9. Supply voltage protection VCC VCC 0.1μF DEVICE VSS AI02169 13/24 Maximum rating 3 M48Z35AV Maximum rating Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5. Absolute maximum ratings Symbol TA Parameter Value Unit 0 to 70 °C SNAPHAT –40 to 85 °C ® CAPHAT DIP –40 to 85 °C SOIC –55 to 125 °C 260 °C Ambient operating temperature ® top TSTG TSLD(1)(2) Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds VIO Input or output voltages –0.3 to 4.6 V VCC Supply voltage –0.3 to 4.6 V IO Output current 20 mA PD Power dissipation 1 W 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds). Caution: Negative undershoots below –0.3V are not allowed on any pin while in the battery back-up mode. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 14/24 M48Z35AV 4 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 6: Operating and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions Parameter M48Z35AV Unit 3.0 to 3.6 V 0 to 70 °C Load capacitance (CL) 50 pF Input rise and fall times ≤5 ns 0 to 3 V 1.5 V Supply voltage (VCC) Ambient operating temperature (TA) Input pulse voltages Input and output timing ref. voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 10. AC measurement load circuit 645Ω DEVICE UNDER TEST CL = 100pF or 5pF CL includes JIG capacitance Note: 1.75V AI03211 50pF for M48Z35AV. Table 7. Capacitance Parameter(1)(2) Symbol CIN CIO (3) Min Max Unit Input capacitance 10 pF Input / output capacitance 10 pF 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs deselected. 15/24 DC and AC parameters Table 8. M48Z35AV DC characteristics Symbol ILI(2) Test condition(1) Parameter Input leakage current ILO((2) Output leakage current Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±5 µA Outputs open 50 mA E = VIH 3 mA E = VCC – 0.2V 3 mA ICC Supply current ICC1 Supply current (TTL standby) ICC2 Supply current (CMOS standby) VIL Input low voltage –0.3 0.8 V VIH Input high voltage 2.2 VCC + 0.3 V VOL Output low voltage IOL = 2.1mA VOH Output high voltage IOH = –1mA 0.4 V 2.4 V 1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 2. Outputs deselected. Figure 11. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tDR tPD INPUTS tRB RECOGNIZED trec DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI01168C Table 9. Symbol tPD tF (2) tFB (3) Power down/up AC characteristics Parameter(1) E or W at VIH before power down Min Max Unit 0 µs VPFD (max) to VPFD (min) VCC fall time 300 µs VPFD (min) to VSS VCC fall time 10 µs tR VPFD (min) to VPFD (max) VCC rise time 10 µs tRB VSS to VPFD (min) VCC rise time 1 µs trec VPFD (max) to inputs recognized 40 200 ms 1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 16/24 M48Z35AV Table 10. DC and AC parameters Power down/up trip points DC characteristics Parameter(1)(2) Symbol VPFD Power-fail deselect voltage VSO Battery back-up switchover voltage tDR(3) Expected data retention time Min Typ Max Unit 2.7 2.9 3.0 V VPFD – 100mV 10 V YEARS 1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). 3. At 25°C, VCC = 0V. 17/24 Package mechanical data 5 M48Z35AV Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline A2 A1 B1 B A L C e1 eA e3 D N E 1 Note: PCDIP Drawing is not to scale. Table 11. PMDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data mm inches Symbol Typ 18/24 Min Max A 8.89 A1 Typ Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 28 M48Z35AV Package mechanical data Figure 13. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 12. SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data mm inches Symbol Typ Min A Max Typ Min Max 3.05 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – e 1.27 0.050 eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 a 0° 8° 0° 8° N 28 CP 28 0.10 0.004 19/24 Package mechanical data M48Z35AV Figure 14. SH – 4-pin SNAPHAT housing for 48mAh battery, package outline A1 A2 A eA A3 B L eB D E SHZP-A Note: Drawing is not to scale. Table 13. SH – 4-pin SNAPHAT housing for 48mAh battery, pack. mech. data mm inches Symbol Typ Min A Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 20/24 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48Z35AV Package mechanical data Figure 15. SH – 4-pin SNAPHAT housing for 120mAh battery, package outline A1 A2 A3 A eA B L eB D E SHZP-A Note: Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT housing for 120 mAh battery, pack. mech. data mm inches Symb Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 21/24 Part numbering 6 M48Z35AV Part numbering Table 15. Ordering information scheme Example: M48Z 35AV –10 MH 1 E Device type M48Z Supply voltage and write protect voltage 35AV = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V Speed –10 = 100ns (35AV) Package PC = PCDIP28 MH(1) = SOH28 Temperature range 1 = 0 to 70°C Shipping method For SOH28: E = Lead-free package (ECOPACK®), tubes F = Lead-free package (ECOPACK®), tape & reel For PCDIP28: blank = tubes 1. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under the part number “M4Zxx-BR00SH1” in plastic tubes (see Table 16). Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH1” in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 16. SNAPHAT battery table Part number 22/24 Description Package M4Z28-BR00SH1 Lithium battery (48mAh) SNAPHAT SH M4Z32-BR00SH1 Lithium battery (120mAh) SNAPHAT SH M48Z35AV 7 Revision history Revision history Table 17. Document revision history Date Revision Changes Sep-1999 1.0 First Issue 20-Apr-2000 1.1 SH and SH28 packages for 2-pin and 2-socket removed 22-Jun-2001 2.0 Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10) 05-Jul-2001 2.1 Removed reference to “Crystal” in Features Summary 17-Dec-2001 2.2 Changed speed grade designator to “–10” (Table 15) 29-May-2002 2.3 Modified reflow time and temperature footnotes (Table 5) 03-Oct-2002 2.4 Update VCC for Supply Voltage (Table 5) 07-Nov-2002 2.5 Update Absolute Maximum Ratings (Table 5) 02-Apr-2003 3.0 v2.2 template applied; test condition updated (Table 10) 24-Mar-2004 4.0 Reformatted; updated Lead-free information (Table 5, 15) 09-Jun-2005 5 Removal of SNAPHAT, Industrial temperature sales types (Table 3, 4, 5, 6, 8, 9, 10, 15) 6 Reformatted document; added lead-free second level interconnect information to cover page and Section 5: Package mechanical data; removed M48Z35AY and references throughout document; updated Table 2, 3, 4, 5, 6, 8, 9, 15 and 16. 05-Nov-2007 23/24 M48Z35AV Please Read Carefully: Information in this document is provided solely in connection with ST products. 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