STA2062A Cartesio™ family infotainment application processor with embedded GPS Data Brief Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU (up to 333 MHz) MCU memory organization – Cache: 16 Kbyte instruction, 16 Kbyte data – 8 Kbyte instruction TCM (tightly coupled memory) – 8 Kbyte data TCM – 32 Kbyte embedded ROM for boot – Two banks of 64 Kbyte embedded SRAM – 512 Byte embedded SRAM for back-up – 4 Gbyte total linear address space – Memory extension through: Flexible static memory controller-FSMC (NOR/NAND Flash, CF/CF+, ROM, SRAM support) Mobile DDR/SDRAM controller: 16 bit data @166 MHz, 2 Chip Select, 512 Kbit each Interrupt – 64-channel interrupt controller (VIC) – 16-vectorized interrupts with 16 programmable priority level DMA – Two 8-channel double port system DMA controllers – 32 DMA request for each controller – Two external DMA requests are supported 32-channel high performance GPS correlation embedded subsystem Eight 32-bit free running timers/counters Four 16-bit extended function timer (EFT) with input capture/output compare and PWM Real-time clock (RTC) Pulse width light modulator (PWL) 32-bit watchdog timer Four autobaud UART with 64X8 transmit and 64x12 receive FIFO with DMA and hardware flow control One IrDA(SIR/MIR/FIR) interface Three I2C multi-master/slave interfaces Two synchronous serial port (SSP) with 32x32 separate transmit and receive FIFO with April 2008 LFBGA361 (16x16x1.4mm) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Motorola-SPI, National-MICROWIRE and Texas- SSI support modes Four multichannel serial ports (MSP) with 32x8 separate transmit and receive FIFO Color LCD controller for STN,TFT or HR-TFT panels USB 2.0 OTG high speed dual role controller (ULPI interface) USB full speed dual role controller with integrated 1.1 physical layer transceiver Two secure-digital multimedia memory card interface (SD/SDIO/MMC) up to 8 bit data SPDIF input interface C3 hardware Reed-Solomon decoder Hardware sample rate converter (SaRaC) Two controller area network (CAN) Four 32-bit GPIO ports JTAG based in-circuit emulator (ICE) with embedded medium trace module Typical working condition: Vdd: 1.2 V ±10%, VIO: 1.8 V Overdrive: Vdd: 1.4 V ±5%, VIO: 1.8 V ±10%, 2.5 V ±10% Bus frequency: 166 MHz (overdrive) Bus/DDR frequency: 166 MHz HCMOS 0.90 µm process Package: – LFBGA16x16x1.4 mm (19x19 balls) – 0.8 mm ball pitch, (0.4 mm ball) – Full array Ambient temperature range: -40 / +85 °C Table 1. Rev 1 For further information contact your local STMicroelectronics sales office. Device summary Order code Package Packing STA2062A LFBGA361 Tray 1/5 www.st.com 5 2/5 M APB SPDIFIN IOs APB I/F APB I/F APB I/F APB I/F PORT SDMC VDD12 VDD33 PLL VDDPLL SUPPLY CORE SaRaC BD CHITF C3 SPDIF EFT(0,3) Audio & Automotive Bridge CLK2 AHB / APB GPS Bridge S S S S AHB / APB USB FS USB PHY USB OTG HS DMA 0 M0 CAN(0,1) DMA1 M0 GPIO(0,3) OCMPxA/OCMPxB ICAPxA/ICAPxB ECLK0-3 CANTxx CANRxx S AHB / APB Core Peripheral Bridge S LCD CTRL APB I/F MSPSCKx MSPRXDx MSPRFSx MSP(0,1,2,3) APB I/F MSPTFSx MSPTCKx MSPRCKx MSPTXDx SSP(0,1) UUID Support MTU(0,1) APB I/F APB I/F SSPCLKx SSPFRMx PMU APB I/F SSPTXDx URXD0 UCTSxn UDCD0n UDSR0n URI0n RTT WDT APB I/F RTC BACKUP PWL SRC APB I/F APB I/F SSPTXDx UART(0,3) PWLOUT UTXDx URTSxn UDTR0n PLL2 PLL1 S VIC APB I/F APB I/F MCDAT[7:0] APB I/F SD/SDIO/MMC(0,1) DM ULPI Interface APB I/F MCDIR0 MCDIR2 MCDIR31 MCDIR74 SXTAL MXTAL IM LCDC Interface APB I/F MCFBCLK MCCMD MCCMDDIR MCCLK I2C(0,1,2) S AHB / APB DMA Bridge 16 KB I / 16KB DCACHE 8K ITCM / 8K DTCM ARM926EJ M1 S M0 DMA 0 DREQ1 APB I/F I2CSCLx APB I/F I2CSDAx IrDA (FIR/MIR/SIR) S S M0 S M1 DACK1 APB I/F FIRTXD SDMC FSMC DREQ0 DMA 1 DACK0 APB I/F FIRRXD DATA CTRL ADDRESS DATA CTRL ADDRESS JTAG TEST PORT (JTAG) APB I/F MCU APB PORT FSMC MXTAL CLK16 CLK2 Emerald DSP HPGPS Interface 32-Channels GPS Correlator Y RAM (12K x 16) (8K x 16) Memory (128 x 32) RAM BACKUP (32K x 32) eSRAM (8K x 32) P RAM WDT ,EFT EIC S S eROM (8K x 32) Acquisition Memory ARM HPGPS X RAM ARM7TMIS LCD AHB DMA 0/1 M1 ARM AHB Instruction ARM AHB Data S Figure 1. GPSCLK 1 uC2 APB ETM Description STA2062A Description The STA2062A is an highly integrated SoC application processor combining host capability with embedded GPS. STA2062A targets vehicles and personal mobile navigation (PND), telematics, advance audio and connectivity systems. Figure 1: Block diagram gives an overview of the complete processor, showing how the ARM926 microcontroller and its peripherals are interfaced. Block diagram STA2062A 2 Package information Package information In order to meet environmental requirements, ST offers this device in ECOPACK® packages. This package has a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. LFBGA361 (16x16x1.4mm) mechanical data & package dimensions mm inch DIM. MIN. TYP. A A1 MAX. MIN. TYP. 1.400 0.210 MAX. 0.0551 0.0082 A2 0.985 A3 0.200 A4 0.0387 0.0079 0.800 b 0.350 15.850 16.000 16.150 0.6240 0.6299 0.6358 E 0.400 0.0315 D D1 OUTLINE AND MECHANICAL DATA 0.450 0.0138 0.0157 0.0177 14.400 0.5669 15.850 16.000 16.150 0.6240 0.6299 0.6358 E1 14.400 0.5669 e 0.800 0.0315 F 0.800 0.0315 Body: 16 x 16 x 1.4mm ddd 0.100 0.0039 eee 0.150 0.0059 fff 0.080 0.0031 LFBGA361 Low profile Fine Pitch Ball Grid Array 8033008 B 3/5 Revision history 3 STA2062A Revision history Table 2. 4/5 Document revision history Date Revision 16-Apr-2008 1 Changes Initial release. STA2062A Please Read Carefully: Information in this document is provided solely in connection with ST products. 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