STMICROELECTRONICS STA2062

STA2062
Cartesio™
Infotainment application processor with embedded GPS
Data Brief
Features
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High performance ARM926 MCU (up to 333MHz)
MCU memory organization
– Cache: 16KByte instruction, 16KByte data
– 8KByte instruction TCM (tightly coupled memory)
– 8KByte data TCM
– 32KByte embedded ROM for boot
– Two banks of 64KByte embedded SRAM
– 512Byte embedded SRAM for back-up
– 4GByte total linear address space
– Memory extension through:
Flexible static memory controller-FSMC
(NOR/NAND Flash, CF/CF+, ROM, SRAM
support)
Mobile DDR/SDRAM controller:
16bit data @166MHz, 2 Chip Select,
512Kbit each
Interrupt
– 64-channel interrupt controller (VIC)
– 16-vectorized interrupts with 16
programmable priority Level
DMA
– Two 8-channel double port system DMA
controllers
– 32 DMA request for each controller
– Two external DMA requests are supported
32 channel high performance GPS correlation
embedded subsystem
Eight 32-bit free running timers/counters
Four 16-bit extended function timer (EFT) with
input capture/output compare and PWM
Real time clock (RTC)
Pulse width light modulator (PWL)
32-bit watchdog timer
Four autobaud UART with 64X8 transmit and 64x12
receive FIFO with DMA and hardware flow control
One IrDA(SIR/MIR/FIR) interface
Three I2C multi-master/slave interfaces
Two synchronous serial port (SSP) with 32x32
separate transmit and receive FIFO with
Motorola-SPI, National-MicroWire and TexasSSI support modes
October 2007
LFBGA361 (16x16x1.4mm)
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Four multichannel serial ports (MSP) with 32x8
separate transmit and receive FIFO
Color LCD controller for STN,TFT or HR-TFT panels
USB 2.0 OTG high speed dual role controller
(ULPI interface)
USB full speed dual role controller with
integrated 1.1 physical layer transceiver
Two secure-digital multimedia memory card
Interface (SD/SDIO/MMC) up to 8 bit data
SPDIF input interface
C3 hardware Reed-Solomon decoder
Hardware sample rate converter (SaRaC)
Two controller area network (CAN)
Four 32-bit GPIO ports
JTAG based in-circuit emulator (ICE) with
embedded medium trace module
Typical working condition: Vdd: 1.2 ±10%V,
VIO: 1.8V
Overdrive: Vdd: 1.4 ±5%V, VIO: 1.8 ±10%V,
2.5 ±10%V
Bus frequency: 166 MHz (overdrive)
Bus/DDR frequency: 166 MHz
HCMOS 0.90µm process
Package:
– LFBGA16x16x1.4mm (19x19balls)
– 0.8mm ball pitch, (0.4mm ball)
– Full array
Ambient temperature range: -40 / +85°C
Table 1.
Rev 2
For further information contact your local STMicroelectronics sales office.
Device summary
Order code
Package
Packing
STA2062
LFBGA361
Tray
1/5
www.st.com
5
2/5
MSP(0,1,2,3)
M
APB
SPDIFIN
IOs
SaRaC
BD
CHITF
C3
SPDIF
EFT(0,3)
APB I/F
APB I/F
APB I/F
APB I/F
PORT SDMC
VDD12
VDD33
VDDPLL
PLL
Audio & Automotive
Bridge
SUPPLY
CORE
S
S
S
AHB / APB
USB FS
USB PHY
USB OTG
HS
DMA 0 M0
CAN(0,1)
DMA1 M0
GPIO(0,3)
OCMPxA/OCMPxB
ICAPxA/ICAPxB
ECLK0-3
CANTxx
CANRxx
S
AHB / APB
Core Peripheral
Bridge
S
LCD CTRL
APB I/F
MSPSCKx
MSPRXDx
MSPRFSx
APB I/F
MSPTFSx
MSPTCKx
MSPRCKx
MSPTXDx
SSP(0,1)
UUID
Support
MTU(0,1)
APB I/F
APB I/F
SSPCLKx
SSPFRMx
PMU
WDT
RTT
APB I/F
SSPTXDx
URXD0
UCTSxn
UDCD0n
UDSR0n
URI0n
APB I/F
APB I/F
SSPTXDx
UART(0,3)
APB I/F
RTC
BACKUP
PWL
SRC
APB I/F
APB I/F
MCDAT[7:0]
APB I/F
SD/SDIO/MMC(0,1)
PWLOUT
UTXDx
URTSxn
UDTR0n
PLL2
PLL1
S
VIC
APB I/F
MCDIR0
MCDIR2
MCDIR31
MCDIR74
I2C(0,1,2)
DM
ULPI Interface
APB I/F
MCFBCLK
MCCMD
MCCMDDIR
MCCLK
SXTAL
MXTAL
IM
LCDC Interface
APB I/F
I2CSCLx
APB I/F
I2CSDAx
IrDA
S
AHB / APB
DMA
Bridge
16 KB I / 16KB
DCACHE
8K ITCM / 8K DTCM
ARM926EJ
DMA 0
DREQ1
M1 S M0
APB I/F
(FIR/MIR/SIR)
S
S
M0 S M1
DACK1
APB I/F
FIRTXD
SDMC
FSMC
DREQ0
DMA 1
DACK0
APB I/F
FIRRXD
DATA
CTRL
PORT FSMC
ADDRESS
DATA
CTRL
ADDRESS
JTAG
TEST PORT
(JTAG)
LCD AHB
DMA 0/1 M1
ARM AHB Instruction
ARM AHB Data
S
S
S
eROM
(128 x 32)
RAM
BACKUP
(32K x 32)
eSRAM
(8K x 32)
Figure 1.
MCU APB
1
MXTAL
ETM
Description
STA2062
Description
The STA2062 is an highly integrated SOC application processor combining host capability
with embedded GPS.
STA2062 targets in vehicle and mobile navigation (PND), telematics, advance audio and
connectivity systems.
Figure 1: block diagram gives an overview of the complete processor, showing how the
ARM926 microcontroller and its peripherals are interfaced.
block diagram
STA2062
2
Package information
Package information
In order to meet environmental requirements, ST offers this device in ECOPACK® packages.
This package has a Lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 2.
LFBGA361 (16x16x1.4mm) mechanical data & package dimensions
mm
inch
DIM.
MIN.
TYP.
A
A1
MAX.
MIN.
TYP.
1.400
0.210
MAX.
0.0551
0.0082
A2
0.985
A3
0.200
A4
0.0387
0.0079
0.800
b
0.350
15.850 16.000 16.150 0.6240 0.6299 0.6358
E
0.400
0.0315
D
D1
OUTLINE AND
MECHANICAL DATA
0.450 0.0138 0.0157 0.0177
14.400
0.5669
15.850 16.000 16.150 0.6240 0.6299 0.6358
E1
14.400
0.5669
e
0.800
0.0315
F
0.800
0.0315
Body: 16 x 16 x 1.4mm
ddd
0.100
0.0039
eee
0.150
0.0059
fff
0.080
0.0031
LFBGA361
Low profile Fine Pitch Ball Grid Array
8033008 B
3/5
Revision history
3
STA2062
Revision history
Table 2.
4/5
Document revision history
Date
Revision
Changes
3-Oct-2007
1
Initial release.
12-Oct-2007
2
Minor changes.
STA2062
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