TI SN74AC573DW

SN54AC573, SN74AC573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996
D
SN54AC573 . . . J OR W PACKAGE
SN74AC573 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3-State Outputs Drive Bus Lines Directly
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
description
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
2D
1D
OE
VCC
SN54AC573 . . . FK PACKAGE
(TOP VIEW)
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D Inputs.
3D
4D
5D
6D
7D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-impedance state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
1Q
D
D
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC573 is characterized for operation over the full military temperature range of –55_C to 125_C.
The SN74AC573 is characterized for operation from –40_C to 85_C.
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54AC573, SN74AC573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996
logic symbol†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
logic diagram (positive logic)
EN
OE
1
C1
1D
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
LE
11
1Q
C1
2Q
3Q
1D
2
19
1Q
1D
4Q
5Q
6Q
7Q
To Seven Other Channels
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through, VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . . 1.3 W
PW package . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54AC573, SN74AC573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996
recommended operating conditions (see Note 3)
SN54AC573
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
∆t/∆v
2
6
MAX
2
6
3.15
3.15
0
Low-level output current
MIN
2.1
0
High-level output current
SN74AC573
2.1
VCC = 4.5 V
VCC = 5.5 V
Output voltage
IOL
MAX
3.85
Input voltage
IOH
MIN
3.85
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
0
VCC
VCC
– 12
– 12
– 24
– 24
VCC = 5.5 V
VCC = 3 V
– 24
– 24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
V
V
VCC = 3 V
VCC = 4.5 V
Input transition rise or fall rate
UNIT
V
V
V
mA
mA
0
8
0
8
ns/V
– 55
125
– 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = – 50 µA
VOH
IOH = – 12 mA
IOH = – 24 mA
IOH = – 75 mA†
IOL = 50 µA
VOL
IOL = 12 mA
IOL = 24 mA
II
IOZ
ICC
Ci
VCC
MIN
TA = 25°C
TYP
MAX
SN54AC573
MIN
MAX
SN74AC573
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.48
2.48
4.5 V
3.94
3.8
3.8
5.5 V
4.94
5.5 V
4.8
4.8
3.85
3.85
MAX
UNIT
V
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.44
0.44
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
V
IOL = 75 mA
VI = VCC or GND
5.5 V
5.5 V
±0.1
±1
±1
µA
VO = VCC or GND
VI = VCC or GND,
5.5 V
±0.25
±5
±2.5
µA
80
40
µA
IO = 0
5.5 V
4
VI = VCC or GND
5V
5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54AC573, SN74AC573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
Pulse duration, LE high
th
Hold time, data after LE↓
Setup time, data before LE↓
SN54AC573
MIN
MAX
SN74AC573
MIN
MAX
UNIT
6
8
7
ns
3.5
5
4
ns
2
3
2
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54AC573
MIN
MAX
SN74AC573
MIN
MAX
UNIT
tw
tsu
Pulse duration, LE high
4
6
5
ns
Setup time, data before LE↓
3
4.5
3.5
ns
th
Hold time, data after LE↓
2
3
2
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
TA = 25°C
MIN
MAX
SN54AC573
SN74AC573
MIN
MAX
MIN
MAX
2.5
13
1.5
16.5
2
15
2.5
12
1.5
15.5
2
14
2.5
13
1.5
16.5
2
15
2.5
12
1.5
15.5
2
14
2.5
11
1.5
13.5
2
12
2.5
11
1.5
14
2
12.5
2.5
12.5
1.5
15
2
13.5
2.5
9.5
1.5
12
2
10.5
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
TA = 25°C
MIN
MAX
SN54AC573
SN74AC573
MIN
MAX
MIN
MAX
2.5
10
1.5
13
2
11.5
2.5
9.5
1.5
12.5
2
11
2.5
9.5
1.5
12.5
2
11
2.5
8.5
1.5
11.5
2
10
2.5
9
1.5
11.5
2
10
2.5
8.5
1.5
11
2
9.5
2.5
11
1.5
13.5
2
12
2.5
8
1.5
10.5
2
9
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
25
pF
SN54AC573, SN74AC573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
500 Ω
CL = 50 pF
(see Note A)
LOAD CIRCUIT
VCC
50% VCC
Timing Input
0V
tw
tsu
3V
Input 50% VCC
50% VCC
Data Input
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
50% VCC
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VCC
50% VCC
VOH
50% VCC
VOL
Output
Waveform 2
S1 at Open
(see Note B)
50% VCC
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
50% VCC
0V
VOLTAGE WAVEFORMS
50% VCC
VCC
50% VCC
0V
Input
th
50% VCC
tPHZ
tPZH
VOLTAGE WAVEFORMS
VOL + 0.3 V
VOL
50% VCC
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
5
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Copyright  1998, Texas Instruments Incorporated