TI 54AC16240WD

54AC16240, 74AC16240
16-BIT BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS234B – JULY 1990 – REVISED OCTOBER 1996
D
D
D
D
D
D
D
54AC16240 . . . WD PACKAGE
74AC16240 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus  Family
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Flow-Through Architecture Optimizes PCB
Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center Pin
Spacings
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description
The ’AC16240 are 16-bit buffers and line drivers
designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters.
They can be used as four 4-bit buffers, two 8-bit
buffers, or one 16-bit buffer. These devices
provide inverting outputs and symmetrical
active-low output-enable (OE) inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
The 74AC16240 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed circuit board area.
The 54AC16240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74AC16240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
L
H
L
L
L
H
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
54AC16240, 74AC16240
16-BIT BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS234B – JULY 1990 – REVISED OCTOBER 1996
logic symbol†
1OE
2OE
3OE
4OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
48
25
24
EN1
EN2
EN3
EN4
47
1
1
3
44
5
43
6
41
8
1
2
40
9
38
11
37
12
36
1
3
13
35
14
33
16
32
17
30
19
1
4
29
20
27
22
26
23
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
2
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
54AC16240, 74AC16240
16-BIT BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS234B – JULY 1990 – REVISED OCTOBER 1996
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power dissipation at TA = 55°C (in still air)(see Note 2): DL package . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
54AC16240, 74AC16240
16-BIT BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS234B – JULY 1990 – REVISED OCTOBER 1996
recommended operating conditions (see Note 3)
54AC16240
VCC
Supply voltage
VIH
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
3
5
5.5
NOM
MAX
3
5
5.5
2.1
3.15
3.15
0.9
1.35
1.35
1.65
1.65
0
VCC
VCC
0
–4
–4
–24
–24
VCC = 5.5 V
VCC = 3 V
–24
–24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
V
V
0.9
VCC
VCC
0
Input transition rise or fall rate
UNIT
3.85
VCC = 3 V
VCC = 4.5 V
Low-level output current
MIN
2.1
0
High-level output current
∆t/∆v
MAX
VCC = 4.5 V
VCC = 5.5 V
Output voltage
IOL
NOM
3.85
Input voltage
IOH
74AC16240
MIN
V
V
V
mA
mA
0
10
0
10
ns/V
–55
125
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = – 50 µA
VOH
IOH = – 4 mA
ICC
Ci
Co
TA = 25°C
TYP
MAX
54AC16240
MIN
74AC16240
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
2.58
2.48
2.48
3.94
3.8
3.8
IOH = – 24 mA
A
5.5 V
4.94
IOH = – 75 mA†
5.5 V
IOL = 12 mA
4.8
4.8
3.85
3.85
MAX
UNIT
V
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.44
0.44
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
V
IOL = 75 mA†
VI = VCC or GND
5.5 V
5.5 V
±0.1
±1
±1
µA
VO = VCC or GND
VI = VCC or GND,
5.5 V
±0.5
±5
±5
µA
8
80
80
µA
VI = VCC or GND
VO = VCC or GND
IO = 0
5.5 V
5V
4.5
pF
5V
12
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
MAX
3V
IOL = 24 mA
II
IOZ
MIN
4.5 V
IOL = 50 µA
VOL
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
54AC16240, 74AC16240
16-BIT BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS234B – JULY 1990 – REVISED OCTOBER 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
MIN
TA = 25°C
TYP
MAX
54AC16240
74AC16240
MIN
MAX
MIN
MAX
1.8
5.4
7.5
1.8
8.3
1.8
8.3
2.5
7
9.3
2.5
10.2
2.5
10.2
2.1
6.1
8.5
2.1
9.5
2.1
9.5
2.9
8.4
11.3
2.9
12.6
2.9
12.6
4.3
6.2
8.3
4.3
8.7
4.3
8.7
3.6
6
7.8
3.6
8.4
3.6
8.4
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
MIN
TA = 25°C
TYP
MAX
54AC16240
74AC16240
MIN
MAX
MIN
MAX
1.3
3.3
5.3
1.3
5.8
1.3
5.8
1.9
4.3
6.5
1.9
7.1
1.9
7.1
1.6
3.8
5.9
1.6
6.6
1.6
6.6
3.2
4.7
7.2
3.2
8.1
3.2
8.1
4.2
6
7.7
4.2
8.1
4.2
8.1
3.4
5.1
6.9
3.4
7.3
3.4
7.3
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per latch
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
pF
f = 1 MHz
TYP
42
6
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
54AC16240, 74AC16240
16-BIT BUS DRIVERS
WITH 3-STATE OUTPUTS
SCAS234B – JULY 1990 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
CL = 50 pF
(see Note A)
LOAD CIRCUIT
VCC
50%
Input
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VCC
Output
Waveform 2
S1 at GND
(see Note B)
50%
50%
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
Output
Control
(low-level
enabling)
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright  1998, Texas Instruments Incorporated