TI 74AC16373DL

54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
54AC16373 . . . WD PACKAGE
74AC16373 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus  Family
3-State True Outputs
Full Parallel Access for Loading
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description
The ’AC16373 are 16-bit transparent D-type
latches with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers. The device can be used as two 8-bit
latches or one 16-bit latch. When the latch-enable
(LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are
latched at the levels set up at the D inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
The 74AC16373 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
1EN
48
24
25
47
C1
2EN
C2
1D
46
2
1
44
5
43
6
41
8
40
9
38
11
37
12
36
2D
35
13
2
14
33
16
32
17
30
19
29
20
27
22
26
23
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
1OE
1LE
1
2OE
48
2LE
C1
1D1
47
1D
24
25
C1
2
1Q1
2D1
36
1D
13
2Q1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
recommended operating conditions (see Note 3)
54AC16373
VCC
NOM
MAX
3
5
5.5
Supply voltage
VIH
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
∆t/∆v
3
5
5.5
3.15
3.85
0
0.9
1.35
1.35
1.65
1.65
0
VCC
VCC
0
–4
–4
–24
–24
VCC = 5.5 V
VCC = 3 V
–24
–24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
V
V
0.9
VCC
VCC
VCC = 3 V
VCC = 4.5 V
Input transition rise or fall rate
UNIT
3.85
0
Low-level output current
MAX
3.15
Output voltage
IOL
NOM
2.1
VCC = 4.5 V
VCC = 5.5 V
High-level output current
MIN
2.1
Input voltage
IOH
74AC16373
MIN
V
V
V
mA
mA
0
10
0
10
ns/V
– 55
125
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VOH
IOH = –4 mA
IOL = –24
24 mA
IOH = –75 mA†
IOL = 12 mA
IOL = 24 mA
II
IOZ
ICC
Ci
Co
MIN
TA = 25°C
TYP
MAX
54AC16373
MIN
MAX
MIN
3V
2.9
2.9
2.9
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.48
2.48
4.5 V
3.94
3.8
3.8
5.5 V
4.94
4.8
4.8
3.85
3.85
MAX
UNIT
V
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.44
0.44
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
V
IOL = 75 mA†
VI = VCC or GND
5.5 V
5.5 V
±0.1
±1
±1
µA
VO = VCC or GND
VI = VCC or GND,
5.5 V
±0.5
±5
±5
µA
8
80
80
µA
IO = 0
VI = VCC or GND
VO = VCC or GND
5.5 V
5V
4.5
pF
5V
12
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
74AC16373
4.5 V
5.5 V
IOL = 50 µA
VOL
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
Pulse duration, LE high
th
Hold time, data after LE↓
Setup time, data before LE↓
54AC16373
MIN
MAX
74AC16373
MIN
MAX
UNIT
5
5
5
ns
1.5
1.5
1.5
ns
3
3
3
ns
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
54AC16373
MIN
MAX
74AC16373
MIN
MAX
UNIT
tw
tsu
Pulse duration, LE high
4
4
4
ns
Setup time, data before LE↓
1.5
1.5
1.5
ns
th
Hold time, data after LE↓
2.5
2.5
2.5
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
MIN
TA = 25°C
TYP
MAX
54AC16373
74AC16373
MIN
MAX
MIN
MAX
3.7
10.6
13.4
3.7
15.1
3.7
15.1
4.3
11.3
14
4.3
14.8
4.3
14.8
4.6
12.9
15.8
4.6
18.6
4.6
18.6
4.5
12.1
14.6
4.5
16.4
4.5
16.4
4.2
11.8
14.8
4.2
17.5
4.2
17.5
5.4
16.3
19.8
5.4
22.3
5.4
22.3
4.2
7.9
9.5
4.2
10.2
4.2
10.2
3.8
7.1
8.9
3.8
9.8
3.8
9.8
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
MIN
TA = 25°C
TYP
MAX
54AC16373
MIN
74AC16373
MAX
MIN
MAX
3.1
6.7
8.5
3.1
9.7
3.1
9.7
3.5
7.3
9.1
3.5
10.1
3.5
10.1
3.8
8.2
10.2
3.8
11.9
3.8
11.9
3.6
7.8
9.7
3.6
10.9
3.6
10.9
3.5
7.4
9.4
3.5
10.8
3.5
10.8
4.3
9.1
11.3
4.3
12.8
4.3
12.8
3.9
6.6
8
3.9
8.8
3.9
8.8
3.7
5.9
7.4
3.7
8.1
3.7
8.1
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per latch
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
pF
f = 1 MHz
TYP
43
5
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Timing Input
(see Note B)
0V
tw
50%
50%
th
tsu
VCC
Input
VCC
50%
VCC
50%
50%
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VCC
Input
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VCC
Output
Waveform 2
S1 at GND
(see Note B)
50%
50%
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
Output
Control
(low-level
enabling)
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated