SN54LV573, SN74LV573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D SN54LV573 . . . J OR W PACKAGE SN74LV573 . . . DB, DW, OR PW PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D GND 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 3D 4D 5D 6D 7D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND LE 8Q 7Q The ’LV573 feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 20 2 SN54LV573 . . . FK PACKAGE (TOP VIEW) description These octal transparent D-type latches are designed for 2.7-V to 5.5-V VCC operation. 1 OE VCC 1Q D EPIC (Enhanced-Performance Implanted CMOS) 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs 2D 1D D While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74LV573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LV573 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV573 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV573, SN74LV573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 logic diagram (positive logic) EN OE C1 1D 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 LE 1 11 1Q C1 2Q 3Q 1D 2 19 1Q 1D 4Q 5Q 6Q 7Q To Seven Other Channels 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for DB, DW, J, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 70 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV573, SN74LV573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996 recommended operating conditions (see Note 4) SN54LV573 VCC Supply voltage SN74LV573 MIN MAX MIN MAX 2.7 5.5 2.7 5.5 VIH High level input voltage High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL Low level input voltage Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage 0 Output voltage 0 IOH High level output current High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V –8 –8 –16 –16 IOL Low level output current Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 16 ∆t / ∆v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. 2 2 3.15 3.15 0.8 0.8 1.65 0 0 V V 1.65 VCC VCC UNIT VCC VCC V V mA mA 0 100 0 100 ns / V –55 125 –40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC† IOH = – 100 µA IOH = – 8 mA MIN to MAX IOH = – 16 mA IOL = 100 µA 4.5 V 3V SN54LV573 MIN TYP II VI = VCC or GND IOZ VO = VCC or GND ICC VI = VCC or GND, GND nICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND Co VO = VCC or GND IO = 0 MIN VCC – 0.2 2.4 VCC – 0.2 2.4 3.6 3.6 MIN to MAX IOL = 8 mA IOL = 16 mA SN74LV573 MAX TYP MAX UNIT V 0.2 0.2 3V 0.4 0.4 4.5 V 0.55 0.55 3.6 V ±1 ±1 5.5 V ±1 ±1 3.6 V ±5 ±5 5.5 V ±5 ±5 3.6 V 20 20 5.5 V 20 20 3 V to 3.6 V 500 500 3.3 V 2.5 2.5 5V 3 3 3.3 V 7 7 5V 10 10 V µA µA µA µA pF pF F † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV573, SN74LV573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN54LV573 VCC = 5.5 V ± 0.5 V MIN MAX VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX tw Pulse duration, LE high 9 12 14 ns tsu Setup time, data before LE↓ 4 6 7 ns th Hold time, data after LE↓ 4 6 6 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN74LV573 VCC = 5.5 V ± 0.5 V MIN MAX VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX tw Pulse duration, LE high 9 12 14 ns tsu Setup time, data before LE↓ 4 6 7 ns th Hold time, data after LE↓ 4 6 6 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LV573 PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 5 V ± 0.5 V MIN TYP MAX D LE Q VCC = 3.3 V ± 0.3 V MIN TYP MAX VCC = 2.7 V MIN MAX 9 19 13 23 29 12 21 19 25 31 UNIT ns ten OE Q 11 18 16 22 28 ns tdis OE Q 15 21 21 28 29 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LV573 PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 5 V ± 0.5 V MIN TYP MAX D LE Q VCC = 2.7 V MIN MAX 9 19 13 23 29 12 21 19 25 31 UNIT ns ten OE Q 11 18 16 22 28 ns tdis OE Q 15 21 21 28 29 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 VCC = 3.3 V ± 0.3 V MIN TYP MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV573, SN74LV573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996 operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Cpd Power dissi dissipation ation ca capacitance acitance per er latch Outputs disabled Outputs enabled 33V 3.3 CL = 50 pF F, Outputs disabled POST OFFICE BOX 655303 VCC • DALLAS, TEXAS 75265 TYP 14 f = 10 MHz 5V UNIT 30 pF F 36 16 5 SN54LV573, SN74LV573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION S1 1 kΩ From Output Under Test Vz Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Vz GND 1 kΩ WAVEFORM CONDITION Vm Vi Vz LOAD CIRCUIT VCC = 4.5 V to 5.5 V 0.5 × VCC VCC 2 × VCC VCC = 2.7 V to 3.6 V 1.5 V 2.7 V 6V Vi Vm Timing Input 0V tw tsu Vi Input Vm th Vi Vm Vm Data Input Vm 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Vi Vm Input 0V VOH Vm Output Vm VOL Output VOH Vm 0V Vm VOL tPLZ Output Waveform 1 S1 at Vz (see Note B) tPLH tPHL Vm Vm tPZL tPHL tPLH Vi Output Control Vm Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Vm tPZH 0.5 × Vz VOL + 0.3 V VOL tPHZ Vm VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. 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