STMICROELECTRONICS STCD1040RDM6F

STCD1020, STCD1030, STCD1040
Multi-channel clock distribution circuit
Features
■
2, 3 or 4 outputs buffered clock distribution
■
Single-ended sine wave or square wave clock
input and output
■
Individual clock enable for each output
■
Lower fan-out on clock source
■
No AC coupling capacitor needed at the input
■
Ultra-low phase noise and standby current
■
2.5 V to 3.6 V supply voltage(a)
■
10 pF typical load driving capability
■
Available in TDFN packages
– STCD1020 - 8-lead (2 mm x 2 mm)
– STCD1030 - 10-lead (2 mm x 2.5 mm)
– STCD1040 - 12-lead (2 mm x 3 mm)
■
Operational temperature : –40°C to 85°C
Applications
■
Multi-mode RF clock reference
■
Baseband peripheral devices clock reference
a. For the 1.65 to 2.75 V version, please contact local ST
sales office
Table 1.
TDFN (8, 10 or 12 lead)
Description
The STCD1020, STCD1030 and STCD1040 are
2, 3 or 4 outputs unity gain clock distribution
circuits, which are used to provide a common
frequency clock to multi-mode mobile RF
applications. It can also be used for those
baseband peripheral applications in a mobile
phone such as WLAN, Bluetooth, GPS and DVBH as a clock reference. The STCD1020,
STCD1030 and STCD1040 isolate each device
driven by their clock outputs and minimize
interference between the devices. Each of the
clock buffers can be disabled to lower the power
consumption if the connected device does not
need the clock. The STCD1020, STCD1030 and
STCD1040 accept commonly used mobile master
clock frequencies ranging from 10 MHz to 52
MHz.
The STCD1020, STCD1030 and STCD1040 are
available in 2 mm x 2 mm 8-lead, 2 mm x 2.5 mm
10-lead and 2 mm x 3 mm 12-lead TDFN
packages and can be operated with a single 2.8 V
(or 1.8 V) supply. The operational temperature is
–40°C to +85°C.
Device summary
Order code
Operating temperature range
Channel
Supply
Package
STCD1020RDG6E
–40°C to 85°C
2
2.8 V
TDFN8
STCD1030RDH6E
–40°C to 85°C
3
2.8 V
TDFN10
STCD1040RDM6F
–40°C to 85°C
4
2.8 V
TDFN12
May 2008
Rev 4
1/40
www.st.com
1
Contents
STCD1020, STCD1030, STCD1040
Contents
1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
Connection of the source clock to MCLK . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/40
STCD1020, STCD1030, STCD1040
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Truth table for enable signals (EN 1-4) and output clocks (CLK1-4) . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings (1.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings (2.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating and AC measurement conditions (1.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC characteristics (1.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and AC measurement conditions (2.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC characteristics (2.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TDFN - 8-lead (2 x 2 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TDFN - 10-lead (2 x 2.5 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TDFN - 12-lead (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/40
List of figures
STCD1020, STCD1030, STCD1040
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
4/40
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connections diagram (STCD1020, 2-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connections diagram (STCD1030, 3-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connections diagram (STCD1040, 4-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application circuit using STCD1040 for RF ends of TD-SCDMA/GSM dual mode
mobile phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical application circuit using STCD1040 for baseband peripherals in mobile phone . . 12
Direct connection of the source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connection of the DC-CUT capacitor and bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Quiescent current (IQ) vs. supply voltage (VCC) (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Quiescent current (IQ) vs. temperature (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, Cload = 30 pF, no master clock input) . . . . . . . . . . . . . . . . . . . . . 18
Standy current (ISB) vs. supply voltage (VCC) (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=0, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Active current (IACT) vs. supply voltage (VCC) (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO) . . . . . . . . . . 19
Active current (IACT) vs. master clock input voltage level (Vpp) (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input) . . . . . . . . . . . . . . . . . . . . 20
Active current (IACT) vs. input frequency (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, master clock input Vpp = 1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STCD10x0 recovery time from standby to active (STCD1040, 2.8 V version,
EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1) . . . . . . . . . . . . . . . . . . . . . . . . 21
STCD10x0 buffer recovery time from off to on (STCD1040, 2.8 V version,
EN2=EN3=EN4=1, measure CLK1 when EN1 from 0 to 1) . . . . . . . . . . . . . . . . . . . . . . . . 21
Sine wave input clock vs. output clock (STCD1040, 2.8 V version, 26 MHz sine wave
master clock input from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Rise and fall time for square wave output (STCD1040, 2.8 V, 10 MHz square wave
master clock input, Cload = 20 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input clock phase noise (STCD1040, 2.8 V version, 26 MHz master clock input
from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output clock phase noise (STCD1040, 2.8V version, this phase noise includes the
additive phase noise from TCXO and STCD1040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock bandwidth (STCD1040, 2.8 V version, Cload = 10 pF) . . . . . . . . . . . . . . . . . . . . . . . 24
Quiescent current (IQ) vs. supply voltage (VCC) (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Quiescent current (IQ) vs. temperature (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, Cload = 30 pF, no master clock input) . . . . . . . . . . . . . . . . . . . . 25
Standby current (ISB) vs. supply voltage (VCC) (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=0, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Active current (IACT) vs. supply voltage (VCC) (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO) . . . . . . . . . . 26
Active current (IACT) vs. master clock input voltage level (Vpp) (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input) . . . . . . . . . . . . . . . . . . . . 26
Active current (IACT) vs. input frequency (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, master clock input Vpp=1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STCD1020, STCD1030, STCD1040
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
List of figures
STCD10x0 recovery time from standby to active (STCD1040, 1.8 V version,
EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1) . . . . . . . . . . . . . . . . . . . . . . . . 27
STCD10x0 buffer recovery time from off to on (STCD1040, 1.8 V version,
EN2 =EN3=EN4=1, measure CLK1 when EN1 from 0 to 1). . . . . . . . . . . . . . . . . . . . . . . . 28
Sine wave input clock vs. output clock (STCD1040, 1.8 V version, 26 MHz sine wave
master clock input from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Rise and fall time for square wave output (STCD1040, 1.8 V version, 10MHz square wave
master clock input, Cload = 20 pF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Input clock phase noise (STCD1040, 1.8 V version, 26 MHz master clock input
from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output clock phase noise (STCD1040, 1.8 V version, this phase noise includes the
additive phase noise from TCXO and STCD1040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock bandwidth (STCD1040, 1.8 V version, Cload = 10 pF) . . . . . . . . . . . . . . . . . . . . . . . 30
TDFN - 8-lead, 2 x 2 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TDFN - 10-lead, 2 x 2.5 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TDFN - 12-lead, 2 x 3 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5/40
Device overview
1
STCD1020, STCD1030, STCD1040
Device overview
Figure 1.
Logic diagram
V
CC
MCLK
CLK1
STCD1040
EN1
EN2
CLK2
Clock
distribution
EN3
CLK3
CLK4
EN4
GND
ai13948
Note:
No EN3, EN4, CLK3 nor CLK4 for STCD1020 and no EN4 nor CLK4 for STCD1030.
Figure 2.
Connections diagram (STCD1020, 2-channel)
V CC
1
MCLK
2
EN1
3
EN2
4
STCD1020
TDFN8
8
GND
7
NC
6
CLK1
5
CLK2
ai13949
6/40
STCD1020, STCD1030, STCD1040
Figure 3.
Device overview
Connections diagram (STCD1030, 3-channel)
VCC
1
MCLK
2
EN1
3
EN2
EN3
10
GND
9
NC
8
CLK1
4
7
CLK2
5
6
CLK3
STCK1030
TDFN10
ai13950
Figure 4.
Connections diagram (STCD1040, 4-channel)
V CC
1
12
GND
MCLK
2
11
NC
EN1
3
10
CLK1
EN2
4
9
CLK2
EN3
5
8
CLK3
EN4
6
7
CLK4
STCD1040
TDFN12
ai13951
7/40
Device overview
Table 2.
STCD1020, STCD1030, STCD1040
Pin names and functions
Pin
Type
CLK1, CLK2, CLK3, CLK4
Output
EN1, EN2, EN3, EN4
Input
Clock output channel #1, #2, #3, #4 enable, active
high
MCLK
Input
Master clock input
VCC
Supply
Supply voltage. Bypass to GND with a 0.1 μ F
capacitor.
GND
Supply
Supply ground
NC
Figure 5.
Function
Clock output channel #1, #2, #3, #4. A 0.001μ F DC
cut capacitor needed outside.
Not connected
Block diagram
VCC
EN4
STCD1040
4
CLK4
EN3
3
MCLK
CLK3
EN2
2
CLK2
EN1
1
GND
8/40
CLK1
ai13952
STCD1020, STCD1030, STCD1040
Figure 6.
Device overview
Hardware hookup
VCC
Clock enable
control
VCC
STCD1040
Master
Clock input
MCLK
GND
EN4
CLK4
EN3
CLK3
EN2
CLK2
EN1
CLK1
Clock #4
output
Clock #3
output
Clock #2
output
Clock #1
output
ai13953
9/40
Device operation
2
STCD1020, STCD1030, STCD1040
Device operation
The STCD1020, STCD1030 and STCD1040 are 2, 3 or 4 buffered unity gain clock
distribution circuits. They accept the clock input from an external clock source and send 2, 3
or 4 buffered outputs to different devices.
Each clock output of the STCD1020, STCD1030 and STCD1040 can be enabled for the
device connected to it. If the device connected is in standby and does not require a clock,
the buffer can be disabled to save power consumption. If all the devices connected are in
standby, the STCD1020, STCD1030 and STCD1040 will also be put into standby mode for
further power consumption saving. The enable signals and output clock signals truth table
are given in Table 3.
The input DC cut capacitor is embedded in STCD1020, STCD1030 and STCD1040. A
capacitor outside is needed for each of the clock outputs. The STCD1020, STCD1030 and
STCD1040 are internally biased at 1/2 VCC DC voltage level at the outputs.
Table 3.
Note:
10/40
Truth table for enable signals (EN 1-4) and output clocks (CLK1-4)
EN1
EN2
EN3
EN4
CLK1
CLK2
CLK3
CLK4
0
0
0
0
NO CLOCK
NO CLOCK
NO CLOCK
NO CLOCK
1
0
0
0
CLOCK
NO CLOCK
NO CLOCK
NO CLOCK
1
1
0
0
CLOCK
CLOCK
NO CLOCK
NO CLOCK
...
...
...
...
...
...
...
...
1
1
1
1
CLOCK
CLOCK
CLOCK
CLOCK
"0" means logic low and "1" means logic high. When NO CLOCK outputs, the CLKx pins
stay at High Impedance.
STCD1020, STCD1030, STCD1040
Application information
3
Application information
3.1
Typical applications
The STCD1020, STCD1030 and STCD1040 distribute a source clock (for example, from
VCTCXO) to 2, 3 or 4 channel outputs. The typical application circuits using STCD1040 are
shown in Figure 7 and Figure 8 below.
In Figure 7, the clock from VCTCXO is distributed to the TD-SCDMA transmitter and
receiver and GSM transceiver separately.
In Figure 8, the buffer #4 output is fed into the Bluetooth system. In order to allow minimum
power consumption, a Bluetooth system always has a clock request feature. If the Bluetooth
system does not require the clock, the clock request will disable the clock output.
The enable pins can also be connected to logic high to let the channel output always on. If
the channels of STCD1020, STCD1030 and STCD1040 are not used in the application, the
enable pins of the channels should be connected to ground on PCB.
Figure 7.
Typical application circuit using STCD1040 for RF ends of TDSCDMA/GSM dual mode mobile phone
VCC
Mode
selection
VCC
VCTCXO
STCD1040 EN4
CLK4
EN3
CLK3
MCLK
EN2
CLK2
GND
TD-SCDMA
transmitter
TD-SCDMA
receiver
EN1
CLK1
GSM
transceiver
ai13954
11/40
Application information
Figure 8.
STCD1020, STCD1030, STCD1040
Typical application circuit using STCD1040 for baseband peripherals in
mobile phone
VCC
BT_External_Req
Internal_Req
VCC
VCTCXO
Bluetooth
STCD1040 EN4
CLK4
MCLK
EN3
CLK3
WLAN
EN2
CLK2
GND
GPS
EN1
CLK1
Other
device
ai13955
3.2
Connection of the source clock to MCLK
If the output of the clock source voltage level is within the supply rails of the STCD1020,
STCD1030 and STCD1040, the output of the source clock should be connected directly to
the MCLK of the clock distribution circuits. This is described in Figure 9. The direct
connection of the source clock is the common case and a DC-CUT capacitor is saved on
PCB.
Figure 9.
Direct connection of the source clock
VCC
OUT
VCTCXO
MCLK
STCD1020
STCD1030
STCD1040
ai13956
Note:
12/40
The input clock voltage level of the STCD1020, STCD1030, and STCD1040 cannot exceed
the supply rails when it is directly connected to the source clock. If it is needed to connect a
source clock with the voltage level exceeds the supply rails of the clock distribution circuits,
the user needs to connect a DC-CUT capacitor serially as shown in Figure 10. A voltage
divider formed by a resistor string is also needed to set a proper DC bias for the clock input
STCD1020, STCD1030, STCD1040
Application information
of the STCD1020, STCD1030 and STCD1040. The proper DC voltage is around half of the
supply.
The connection of the DC-CUT capacitor and bias for the STCD1020, STCD1030 and
STCD1040 is only needed when the output of VCTCXO voltage level exceeds the supply of
the clock distribution circuit (see Figure 10).
Figure 10. Connection of the DC-CUT capacitor and bias
VCC
R1
VCTCXO
OUT
0.1μF
DC-CUT
MCLK
R2
STCD1020
STCD1030
STCD1040
ai13957
13/40
Maximum rating
4
STCD1020, STCD1030, STCD1040
Maximum rating
Stressing the device above the rating listed in the "Absolute maximum ratings" table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Absolute maximum ratings (1.8 V supply)
Symbol
TSTG
TSLD
(1)
TJ
Parameter
Value
Unit
Lead solder temperature for 10 seconds
260
Maximum junction temperature
150
°C
°C
°C
Storage temperature (VCC off)
-55 to 150
VCC
Supply voltage
-0.3 to 3.6
V
VIN
Input voltage level
-0.3 to 3.6
V
VEN
Voltage on enable pins
-0.3 to 3.6
V
θJA
Thermal resistance (junction to ambient)
TDFN8
149.0
TDFN10
136.6
TDFN12
132.4
°C/W
°C/W
°C/W
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
Table 5.
Absolute maximum ratings (2.8 V supply)
Symbol
TSTG
TSLD(1)
TJ
Parameter
Value
Unit
Lead solder temperature for 10 seconds
260
Maximum junction temperature
150
°C
°C
°C
Storage temperature (VCC off)
-55 to 150
VCC
Supply voltage
-0.3 to 6
V
VIN
Input voltage level
-0.3 to 6
V
VEN
Voltage on enable pins
-0.3 to 6
V
θJA
Thermal resistance (junction to ambient)
TDFN8
149.0
TDFN10
136.6
TDFN12
132.4
°C/W
°C/W
°C/W
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
14/40
STCD1020, STCD1030, STCD1040
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow are derived from tests performed under the measurement conditions summarized in
Table 6. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 6.
Operating and AC measurement conditions (1.8 V supply)
Parameter
Condition
Unit
1.65 to 2.75
V
Output clock voltage (CLK1…CLK4)
0 to VCC
V
Device enable voltage (EN1…EN4)
0 to VCC
V
Ambient operating temperature (TA)
-40 to +85
°C
VCC supply
Table 7.
DC and AC characteristics (1.8 V supply)
Symbol
Parameter
Condition(1)
Min
Typ
Max
Unit
fMCLK
Master clock (eg. from VCTCXO)
Sine wave/square wave
10
26
52
MHz
1.65
1.8
2.75
V
0.75
1
Vpp
-1.5
-0.5
dB
VCC
Supply voltage
Vin
Input clock voltage level(2)
Vout
IQ
IACT
Output gain level
Quiescent
(3)
current(4)
Active current(5)
CL = 10 pF
2 buffers version
1.6
2.6
3 buffers version
2.0
3.3
4 buffers version
2.6
4
1 channel enabled
1.7
2 channels enabled
2.2
3 channels enabled
2.7
4 channels enabled
3.2
mA
mA
Standby current
All buffers disabled
RIN
Input resistance
At DC level
>100
CIN
Input capacitance
f = 26 MHz
3
4
pF
tr/f
Rise/fall time(6)
Vin = 1 Vpp, CL = 10 pF
Square wave input/output
2
5
ns
Vin = 1 Vpp, –1 dB, CL = 10 pF
Sine wave input/output
52
BW
VENH
VENL
Signal bandwidth(3)
Enable voltage high(7)
Enable voltage
low(7)
EN1~EN4
EN1~EN4
1
μA
ISB
kΩ
MHz
1.2
V
0.6
V
15/40
DC and AC parameters
Table 7.
DC and AC characteristics (1.8 V supply)
Symbol
PN
STCD1020, STCD1030, STCD1040
Condition(1)
Parameter
Additive phase
noise(3)(8)
Min
Typ
Max
Unit
at 1 kHz offset
-135
at 10 kHz offset
-145
at 100 kHz offset
-150
STCD10x0 active
20
μs
μs
tRECB
Buffer recovery time from off to
on
tRECC
STCD10x0 active recovery time
from standby to active
50
CL
Capacitive load for each channel
10
RL
Resistive load for each channel
dBc/
Hz
20
pF
10
kΩ
1. Valid for ambient operating temperature: TA = -40°C to 85°C; VCC = 1.65 V to 2.75 V; typical TA = 25°C; Load
capacitance = 10 pF (except where noted).
2.
Clock input voltage level should not exceed supply rails.
3. Simulated and determined via design and NOT 100% tested.
4. The quiescent current is measured when the enable pins are active, but without input master clock signal (fmclk = 0 Hz).
5. The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The
typical test condition is 26 MHz sine wave with 1 Vpp master clock input, CL = 10 pF.
6. The rise time is measured when clock edge transfers from 10% VCC to 90% VCC. The fall time is measured when clock
edge transfers from 90% VCC to 10% VCC.
7. Other test results are under test condition VENH = 1.8 V and VENL = 0 V.
8. Guaranteed with the supply noise of 30 μ Vrms from 300 Hz to 50 kHz.
Table 8.
Operating and AC measurement conditions (2.8 V supply)
Parameter
Condition
Unit
VCC supply
2.5 to 3.6
V
Output clock voltage (CLK1…CLK4)
0 to VCC
V
Device enable voltage (EN1…EN4)
0 to VCC
V
Ambient operating temperature (TA)
-40 to +85
°C
Table 9.
Symbol
fMCLK
VCC
DC and AC characteristics (2.8 V supply)
Parameter
Master clock (eg. from VCTCXO)
Input clock voltage
Vout
Output gain level(3)
16/40
Min
Typ
Max
Unit
Sine wave/square wave
10
26
52
MHz
2.5
2.8
3.6
V
0.75
1
Vpp
-1.5
-0.5
dB
Supply voltage
Vin
IQ
Condition(1)
Quiescent current
level(2)
(4)
CL = 10 pF
2 buffers version
1.7
2.6
3 buffers version
2.2
3.3
4 buffers version
2.8
4
mA
STCD1020, STCD1030, STCD1040
Table 9.
Symbol
IACT
DC and AC parameters
DC and AC characteristics (2.8 V supply) (continued)
Condition(1)
Parameter
Active current(5)
Min
Typ
1 channel enabled
1.8
2 channels enabled
2.3
3 channels enabled
2.85
4 channels enabled
3.4
Max
Unit
mA
μA
ISB
Standby current
All buffers disabled
RIN
Input resistance
At DC level
>100
CIN
Input capacitance
f = 26 MHz
3
4
pF
tr/f
Rise/fall times(6)
Vin = 1Vpp, CL = 10 pF
Square wave input/output
2
5
ns
Vin =1 Vpp, -1dB, CL = 10 pF
Sine wave input/output
52
BW
VENH
VENL
PN
Signal bandwidth(3)
Enable voltage high(7)
Enable voltage
EN1~EN4
low(7)
Additive phase noise(3)(8)
1
kΩ
MHz
1.2
V
EN1~EN4
0.6
V
at 1 kHz offset
-135
at 10 kHz offset
-145
at 100 kHz offset
-150
STCD10x0 active
20
μs
μs
tRECB
Buffer recovery time from off to on
tRECC
STCD10x0 active recovery time
from standby to active
50
CL
Capacitive load for each channel
10
RL
Resistive load for each channel
dBc/
Hz
20
pF
10
kΩ
1. Valid for ambient operating temperature: TA = -40°C to 85°C; VCC = 2.5 V to 3.6 V; typical TA = 25°C;
Load capacitance = 10 pF (except where noted).
2.
Clock input voltage level should not exceed supply rails.
3. Simulated and determined via design and NOT 100% tested.
4. The quiescent current is measured when the enable pins are active, but without input master clock signal (fMCLK = 0 Hz).
5. The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The typical
test condition is 26 MHz sine wave with 1 Vpp master clock input, CL = 10 pF.
6. The rise time is measured when clock edge transfers from 10% VCC to 90% VCC. The fall time is measured when clock
edge transfers from 90% VCC to 10% VCC.
7. Other test results are under test condition VENH = 1.8 V and VENL = 0 V.
8. Guaranteed with the supply noise of 30 μ Vrms from 300 Hz to 50 kHz.
17/40
Typical operating characteristics
6
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Typical operating characteristics of STCD1040 are VCC = 2.8 V; TA = 25°C;
load capacitance = 10 pF, 26 MHz TCXO ENE3127B from NDK (except where noted).
Figure 11. Quiescent current (IQ) vs. supply voltage (VCC) (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, no master clock input)
Quiescent current vs. Supply voltage
3
2.9
10pF
2.8
20pF
2.7
30pF
2.6
2.5
3.
6
3.
4
3.
2
3
2.
8
2.
6
2.4
2.
4
Quiescent current (mA)
3.1
Supply voltage (V)
Figure 12. Quiescent current (IQ) vs. temperature (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, Cload = 30 pF, no master clock input)
Quiescent current (mA)
Quiescent current vs. Temperature
3.2
3
2.8
2.6
2.4
2.2
2
-50
-30
-10
10
30
50
Temperature (ºC)
18/40
70
90
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 13. Standy current (ISB) vs. supply voltage (VCC) (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=0, no master clock input)
Standby current vs. Supply voltage
Standby current (µA)
1
0.5
0
-0.5
-1
2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7
Supply voltage (V)
Figure 14. Active current (IACT) vs. supply voltage (VCC) (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO)
Active current vs. Supply voltage
Active current (mA)
6
4
10pF
2
20pF
30pF
0
2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7
Supply voltage (V)
19/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 15. Active current (IACT) vs. master clock input voltage level (Vpp)
(STCD1040, 2.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave
master clock input)
Active current vs. Master clock voltage level
Active current (mA)
6
5
4
3
2
10pF
1
20pF
30pF
1.
3
1.
2
1.
1
1
0.
9
0.
8
0.
7
0
Master clock voltage level Vpp(V)
Figure 16. Active current (IACT) vs. input frequency (STCD1040, 2.8 V version,
EN1=EN2=EN3=EN4=1, master clock input Vpp = 1 V)
Active current vs. Input frequency
Active current (mA)
10
8
6
4
10pF
2
20pF
30pF
0
1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Frequency (MHZ)
20/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 17. STCD10x0 recovery time from standby to active (STCD1040, 2.8 V
version, EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1)
Figure 18. STCD10x0 buffer recovery time from off to on (STCD1040, 2.8 V version,
EN2=EN3=EN4=1, measure CLK1 when EN1 from 0 to 1)
21/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 19. Sine wave input clock vs. output clock (STCD1040, 2.8 V version, 26 MHz
sine wave master clock input from TCXO)
Figure 20. Rise and fall time for square wave output (STCD1040, 2.8 V, 10 MHz
square wave master clock input, Cload = 20 pF)
22/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 21. Input clock phase noise (STCD1040, 2.8 V version, 26 MHz master clock
input from TCXO)
Figure 22. Output clock phase noise (STCD1040, 2.8V version, this phase noise
includes the additive phase noise from TCXO and STCD1040)
23/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 23. Clock bandwidth (STCD1040, 2.8 V version, Cload = 10 pF)
Output gain (dB)
Clock bandwidth
0.00
-1.00
-2.00
-3.00
-4.00
-5.00
-6.00
-7.00
-8.00
0
1
10
Input frequency (MHz)
100
Figure 24. Quiescent current (IQ) vs. supply voltage (VCC) (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, no master clock input)
Quiescent current vs. Supply voltage
2.8
2.6
2.4
10pF
2.2
20pF
2
Supply voltage (V)
24/40
2.
7
2.
5
2.
3
2.
1
1.
9
1.
7
30pF
1.
5
Quiescent current (mA)
3
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 25. Quiescent current (IQ) vs. temperature (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, Cload = 30 pF, no master clock input)
Quiescent current (mA)
Quiescent current vs. Temperature
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
-50
-30
-10
10
30
50
70
90
Temperature (˚C)
Figure 26. Standby current (ISB) vs. supply voltage (VCC) (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=0, no master clock input)
Standby current vs. Supply voltage
0.5
0
-0.5
2.
7
2.
5
2.
3
2.
1
1.
9
1.
7
-1
1.
5
Standby current (µA)
1
Supply voltage (V)
25/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 27. Active current (IACT) vs. supply voltage (VCC) (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO)
Active current vs. Supply voltage
Active current (mA)
6
4
10pF
2
20pF
30pF
0
1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
Supply voltage (V)
Figure 28. Active current (IACT) vs. master clock input voltage level (Vpp)
(STCD1040, 1.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave
master clock input)
Active current vs. Master clock voltage level
Active current (mA)
6
5
4
3
10pF
2
20pF
1
30pF
1.
3
1.
2
1.
1
1
0.
9
0.
8
0.
7
0
Master clock voltage level Vpp(V)
26/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 29. Active current (IACT) vs. input frequency (STCD1040, 1.8 V version,
EN1=EN2=EN3=EN4=1, master clock input Vpp=1 V)
Active current vs. Input frequency
Active current (mA)
12
10
8
6
10pF
4
20pF
2
30pF
0
1
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Frequency (MHZ)
Figure 30. STCD10x0 recovery time from standby to active (STCD1040, 1.8 V
version, EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1)
27/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 31. STCD10x0 buffer recovery time from off to on (STCD1040, 1.8 V version,
EN2 =EN3=EN4=1, measure CLK1 when EN1 from 0 to 1)
Figure 32. Sine wave input clock vs. output clock (STCD1040, 1.8 V version, 26 MHz
sine wave master clock input from TCXO)
28/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 33. Rise and fall time for square wave output (STCD1040, 1.8 V version,
10MHz square wave master clock input, Cload = 20 pF)
Figure 34. Input clock phase noise (STCD1040, 1.8 V version, 26 MHz master clock
input from TCXO)
29/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 35. Output clock phase noise (STCD1040, 1.8 V version, this phase noise
includes the additive phase noise from TCXO and STCD1040)
Figure 36. Clock bandwidth (STCD1040, 1.8 V version, Cload = 10 pF)
Output gain(db)
Clock bandwidth
30/40
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
0
1
10
Input frequency(MHz)
100
STCD1020, STCD1030, STCD1040
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
31/40
Package mechanical data
STCD1020, STCD1030, STCD1040
Figure 37. TDFN - 8-lead, 2 x 2 mm package outline
D
A
B
0.10 C 2x
E
PIN 1 INDEX AREA
0.10 C 2x
TOP VIEW
A
A1
0.10 C
C
SEATING
PLANE
SIDE VIEW
0.08 C
e
b
PIN 1 INDEX AREA
1
0.10
4
C A B
L
Pin#1 ID
5
8
BOTTOM VIEW
TDFN-8L
32/40
STCD1020, STCD1030, STCD1040
Table 10.
Package mechanical data
TDFN - 8-lead (2 x 2 mm) package mechanical data
mm
inches
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
2.00
BSC
0.079
BSC
E
2.00
BSC
0.079
BSC
e
0.50
0.020
L
0.45
0.55
0.65
0.018
0.022
0.026
33/40
Package mechanical data
STCD1020, STCD1030, STCD1040
Figure 38. TDFN - 10-lead, 2 x 2.5 mm package outline
D
A
B
0.10 C 2x
E
PIN 1 INDEX AREA
0.10 C 2x
TOP VIEW
A
A1
0.10 C
SEATING
PLANE
0.08 C
SIDE VIEW
e
b
PIN 1 INDEX AREA
0.10
C A B
L
Pin#1 ID
BOTTOM VIEW
TDFN-10L
34/40
STCD1020, STCD1030, STCD1040
Table 11.
Package mechanical data
TDFN - 10-lead (2 x 2.5 mm) package mechanical data
mm
inches
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
2.50
BSC
0.098
BSC
E
2.00
BSC
0.079
BSC
e
0.50
0.020
L
0.45
0.55
0.65
0.018
0.022
0.026
35/40
Package mechanical data
STCD1020, STCD1030, STCD1040
Figure 39. TDFN - 12-lead, 2 x 3 mm package outline
D
A
B
INDEX AREA
0.10 C 2x
E
(D/2xE/2)
0.10 C
TOP VIEW
A
A1
0.10 C
C
SEATING
PLANE
SIDE VIEW
0.08 C
e
b
1
6
12
7
0.10
C A B
PIN#1 ID
INDEX AREA
L
(D/2xE/2)
BOTTOM VIEW
TDFN-12L
36/40
STCD1020, STCD1030, STCD1040
Table 12.
Package mechanical data
TDFN - 12-lead (2 x 3 mm) package mechanical data
mm
inches
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
3.00
BSC
0.118
E
2.00
BSC
0.079
e
0.50
0.020
L
0.45
0.55
0.65
0.018
0.022
0.026
37/40
Part numbering
8
STCD1020, STCD1030, STCD1040
Part numbering
Table 13.
Ordering information scheme
Example:
STCD
1020
R
DG
6
E
Device type
STCD = clock distribution
Channels
1020 = 2-channel
1030 = 3-channel
1040 = 4-channel
Operating voltage
R = 2.5 to 3.6 V
P = 1.65 to 2.75 V(1)
Package
DG = TDFN8 (2-channel)
DH = TDFN10 (3-channel)
DM = TDFN12 (4-channel)
Temperature range
6 = –40°C to +85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
38/40
STCD1020, STCD1030, STCD1040
9
Revision history
Revision history
Table 14.
Document revision history
Date
Revision
Changes
08-Aug-2007
1
Initial release.
08-Oct-2007
2
Addition of footnote 4 in Table 7: DC and AC characteristics (1.8 V
supply); updated Vout in Table 7 and Table 9; minor text changes.
03-Apr-2008
3
Updated cover page, Table 2, 5, 7, 9, 13, Figure 1, 6, 11, 12, 13, 14,
15, 16, 17, 18, 19, 20, Section 2 and 6; added Figure 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36.
08-May-2008
4
Updated cover page, Table 7, 8, Figure 14, 15, 27, 28, and Section 6;
datasheet status upgraded to full datasheet.
39/40
STCD1020, STCD1030, STCD1040
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40/40