STCD22x0, STCD23x0, STCD24x0 Multichannel clock distribution circuit Features ■ 2, 3 or 4 output buffered clock distribution ■ Single-ended square wave (or sine wave) clock input ■ Rail-to-rail (0 V to VTCXO) square wave output ■ Individual enable pin for each output ■ 1.8 V, high PSRR LDO for external clock source voltage supply (VTCXO) ■ No AC coupling capacitor needed ■ Ultra-low phase noise and standby current ■ Common system clock request, open drain, active low ■ Clock enable signal polarities factory programmable (STCD23x0) ■ Option pins allow clock enable polarities to be user configurable (STCD22x0 and STCD24x0) Applications ■ High isolation output-to-output & output-to-input ■ Multimode RF clock reference ■ 2.5 V to 5.1 V battery supply voltage ■ Baseband peripheral device clock reference ■ 40 pF max load driving capability per output ■ Mobile Internet Devices (MIDs) ■ Available in chip scale package (CSP) ■ Operating temperature : –20 °C to 85 °C Table 1. Flip Chip (12-bump, 16-bump) Device summary Reference Part number Channels STCD22x0 STCD2200(1) 2-channel STCD2410 (1) Package Flip Chip 12-bump (1.2 mm x 1.6 mm) User program STCD2400 STCD24x0 Enable polarity 4-channel Flip Chip 16-bump (1.6 mm x 1.6 mm) STCD2300(1) STCD2310(1) STCD23x0 STCD2320 (1) 3-channel Factory program Flip Chip 12-bump (1.2 mm x 1.6 mm) STCD2330(1) 1. Contact local ST sales office for availability. January 2010 Doc ID 15400 Rev 2 1/39 www.st.com 1 Contents STCD22x0, STCD23x0, STCD24x0 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Enable polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 LDO input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 LDO output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 LDO BYP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 MCREQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 Output trace line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 Typical application connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin functions (STCD22x0, 2-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin functions (STCD23x0, 3-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin functions (STCD24x0, 4-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table for clock enable (EN1-4), master clock request (MCREQ) and VTCXO . . . . . . 12 Truth table for enable signals (EN1-4), master clock input (MCLK) and output clocks (CLK1-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STCD22x0, STCD23x0 and STCD24x0 and enable polarity options . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flip Chip 12-bump, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flip Chip 16-bump, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Doc ID 15400 Rev 2 3/39 List of figures STCD22x0, STCD23x0, STCD24x0 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. 4/39 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware hookup (master clock enable active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware hookup (master clock enable active high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connections diagram Flip Chip 12-bump (STCD22x0, 2-channel). . . . . . . . . . . . . . . . . . . . 8 Connections diagram Flip Chip 12-bump (STCD23x0, 3-channel). . . . . . . . . . . . . . . . . . . . 9 Connections diagram Flip Chip 16-bump (STCD24x0, 4-channel). . . . . . . . . . . . . . . . . . . . 9 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical application circuit using STCD24x0 for RF ends of TD-SCDMA/GSM dual-mode mobile phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical application circuit using STCD24x0 for baseband peripherals in mobile phone. . . 18 Quiescent current vs. supply voltage (EN1 = EN2 = EN3 = EN4 = 1, no master clock input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Quiescent current vs. temperature (EN1 = EN2 = EN3 = EN4 = 1, Cload = 20 pF, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Active current vs. temperature (EN1 = EN2 = EN3 = EN4 = 1, Cload = 20 pF, VCC = 3.8 V, fMCLK = 26 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Standby current vs. supply voltage (EN1 = EN2 = EN3 = EN4 = 0, no master clock input) 20 Active current vs. supply voltage (EN1 = EN2 = EN3 = EN4 = 1, fMCLK = 26 MHz, Cload = 20 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Active current vs. master clock input voltage level (EN1 = EN2 = EN3 = EN4 = 1, fMCLK = 26 MHz, Cload = 20 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Active current vs. master clock frequency (EN1 = EN2 = EN3 = EN4 = 1, Cload = 20 pF) . 21 STCD2400 recovery time from standby to active (VTCXO is on) . . . . . . . . . . . . . . . . . . . . 22 STCD2400 recovery time from off to on (VTCXO first in standby) . . . . . . . . . . . . . . . . . . . 22 Output clock rise/fall time (Cload = 40 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STCD2400 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STCD2400 power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Phase noise input (from the clock source, 26 MHz square wave XO KC2520C26 from Kyocera) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Phase noise output (include the clock source and STCD2400 additive phase noise) . . . . 26 Flip Chip 12-bump, package mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flip Chip 16-bump, package mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flip Chip 12-bump tape and reel specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flip Chip 16-bump tape and reel specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 1 Description Description The STCD22x0, STCD23x0 and STCD24x0 are 2, 3 or 4 output clock distribution circuits which accept external square wave or sine wave signals and output rail-to-rail (0 V to VTCXO) square wave signals. They are used to provide a common frequency clock to multimode mobile RF applications. They can also be used for those baseband peripheral applications in mobile phones such as WLAN, Bluetooth, GPS and DVB-H as the clock reference. The STCD22x0, STCD23x0 and STCD24x0 isolate each device driven by their clock outputs and minimize interference between the devices. Each of the clock buffers can be disabled to lower the power consumption whenever the connected device does not need the clock. The STCD22x0, STCD23x0 and STCD24x0 accept commonly used mobile master clock frequencies ranging from 10 MHz to 52 MHz. The STCD22x0, STCD23x0 and STCD24x0 have a common clock request (open drain output, active low) controlling the external clock source. A 1.8 V, high PSRR LDO is also integrated in the STCD22x0, STCD23x0 and STCD24x0 to supply power to the external clock source (for example, TCXO). STMicroelectronics offers different versions for the enable polarities. The STCD22x0, STCD23x0 and STCD24x0 are available in, respectively, 1.2 mm x 1.6 mm (12-bump), 1.2 mm x 1.6 mm (12-bump) and 1.6 mm x 1.6 mm (16-bump) chip scale packages and can be operated with a battery supply voltage ranging from 2.5 V to 5.1 V. The operating temperature is –20 to +85 °C. Doc ID 15400 Rev 2 5/39 Device overview 2 STCD22x0, STCD23x0, STCD24x0 Device overview Figure 1. Logic diagram VCC MCLK MC REQ EN1 EN2 CLK1 STCD24x0 (1) CLK2 EN3 (1)(2) EN4 Clock Distribution (1) CLK3 (1)(2) BYP CLK4 (2) OPT1 VTCXO (2) OPT2 GND 1. EN3, CLK3, EN4, and CLK4 do not exist for STCD22x0. 2. OPT1, OPT2, EN4, and CLK4 do not exist for STCD23x0. 6/39 Doc ID 15400 Rev 2 ai14020 STCD22x0, STCD23x0, STCD24x0 Figure 2. Device overview Block diagram VCC STCD24x0 VCC VTCXO CLK4 4 Bandgap BYP VTCXO LDO VTCXO EN3 CLK3 3 VTCXO MC REQ EN4 EN2 CLK2 2 OPT1 OPT2 VTCXO MCLK 1 EN1 CLK1 GND Note: ai14021 Enable signals (EN1-4) can be factory programmed either active high or active low for STCD23x0 and can have different polarity options by configuring OPT1 and OPT2 for STCD22x0 and STCD24x0. Master clock request (MCREQ) is open drain output and active low. Figure 3. Hardware hookup (master clock enable active low) VCC Enable control C EN4 BYP C VTCXO VIO C CLK4 EN3 STCD24x0 CLK3 XO Clock #4 output VDD MCREQ EN VCC MCLK Clock #3 output EN2 CLK2 OPT1 EN1 OPT2 CLK1 Clock #2 output Clock #1 output ai14028a Doc ID 15400 Rev 2 7/39 Device overview Figure 4. STCD22x0, STCD23x0, STCD24x0 Hardware hookup (master clock enable active high) VCC Enable control C EN4 BYP C Clock #4 output CLK4 VTCXO C EN3 STCD24x0 CLK3 XO VDD EN2 MCREQ EN VCC Clock #3 output Clock #2 output CLK2 MCLK OPT1 EN1 OPT2 CLK1 Clock #1 output ai14028b Figure 5. Connections diagram Flip Chip 12-bump (STCD22x0, 2-channel) 3 CLK1 EN1 EN2 CLK2 3 CLK2 EN2 EN1 CLK1 2 BYP GND MCREQ OPT1 2 OPT1 MCREQ GND BYP 1 VCC VTCXO MCLK OPT2 1 OPT2 MCLK VTCXO VCC Bottom view Top view A B C D D C B A ai14017 Note: 8/39 OPT1 is used to configure EN1 polarity. Connect OPT1 to VCC to configure EN1 active high or connect OPT1 to GND to configure EN1 active low. In the same way OPT2 is used to configure EN2. Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Figure 6. Device overview Connections diagram Flip Chip 12-bump (STCD23x0, 3-channel) 3 CLK1 EN1 EN2 CLK2 3 CLK2 EN2 EN1 CLK1 2 BYP GND MCREQ CLK3 2 CLK3 MCREQ GND BYP 1 VCC VTCXO MCLK EN3 1 EN3 MCLK VTCXO VCC Bottom view Top view A B C D D C B A ai14018 Note: EN1~EN3 can be active high or active low. STMicroelectronics offers several polarity options, refer to Section 3.2: Enable polarity for detailed information. Figure 7. Connections diagram Flip Chip 16-bump (STCD24x0, 4-channel) 4 3 2 1 CLK2 EN2 EN3 CLK3 CLK1 EN1 EN4 CLK4 BYP GND MCREQ OPT1 VCC VTCXO MCLK OPT2 CLK3 EN3 EN2 CLK2 CLK4 EN4 EN1 CLK1 2 OPT1 MCREQ GND BYP 1 OPT2 MCLK VTCXO VCC 4 3 Top view A B Bottom view C D D C B A ai14019 Note: OPT1 is used to configure EN1 and EN2 polarity. Connect OPT1 to VCC to configure EN1 and EN2 active high or connect OPT1 to GND to configure EN1 and EN2 active low. In the same way OPT2 is used to configure EN3 and EN4. STMicroelectronics offers different control options, refer to Section 3.2: Enable polarity for detailed information. Doc ID 15400 Rev 2 9/39 Device overview Table 2. Pin functions (STCD22x0, 2-channel) Pin number Pin name A1 VCC B1 Description Supply voltage (decouple with a 1 µF capacitor to GND) VTCXO LDO output for external clock source (decouple with a 1 µF capacitor to GND) C1 MCLK Master clock input D1 OPT2 Optional pin 2. Connect to VCC or GND on PC board to field configure EN2 active high/low. Refer to Section 3.2: Enable polarity for detailed information. A2 BYP Bypass capacitor input pin (10 nF capacitor should be connected to GND in order to improve thermal noise performance) B2 GND Supply ground C2 MCREQ Master clock request signal (open drain, active low) D2 OPT1 Optional pin 1. Connect to VCC or GND on PC board to field configure EN1 active high/low. Refer to Section 3.2: Enable polarity for detailed information. A3 CLK1 Clock output channel - output 1 B3 EN1 Clock output channel enable-1 (active high/low OPT1 field programmable) C3 EN2 Clock output channel enable-2 (active high/low OPT2 field programmable) D3 CLK2 Clock output channel - output 2 Table 3. Pin functions (STCD23x0, 3-channel) Pin number Pin name A1 VCC B1 Description Supply voltage (decouple with a 1 µF capacitor to GND) VTCXO LDO output for external clock source (decouple with a 1 µF capacitor to GND) C1 MCLK D1 EN3 Clock output channel enable-3 (active high/low factory laser programmable) A2 BYP Bypass capacitor input pin (10 nF capacitor should be connected to GND in order to improve thermal noise performance) B2 GND Supply ground C2 10/39 STCD22x0, STCD23x0, STCD24x0 Master clock input MCREQ Master clock request signal (open drain, active low) D2 CLK3 Clock output channel - output 3 A3 CLK1 Clock output channel - output 1 B3 EN1 Clock output channel enable-1 (active high/low factory laser programmable) C3 EN2 Clock output channel enable-2 (active high/low factory laser programmable) D3 CLK2 Clock output channel - output 2 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Table 4. Pin functions (STCD24x0, 4-channel) Pin number Pin name A1 VCC B1 Device overview Description Supply voltage (decouple with a 1 µF capacitor to GND) VTCXO LDO output for external clock source (decouple with a 1 µF capacitor to GND) C1 MCLK Master clock input D1 OPT2 Optional pin 2. Connect to VCC or GND on PC board to field configure EN3 and EN4 active high/low. Refer to Section 3.2: Enable polarity for detailed information. A2 BYP Bypass capacitor input pin (10 nF capacitor should be connected to GND in order to improve thermal noise performance) B2 GND Supply ground C2 MCREQ Master clock request signal (open drain, active low) D2 OPT1 Optional pin 1. Connect to VCC or GND on PC board to field configure EN1 and EN2 active high/low. Refer to Section 3.2: Enable polarity for detailed information. A3 CLK1 Clock output channel - output 1 B3 EN1 Clock output channel enable-1 (active high/low OPT1 field programmable) C3 EN4 Clock output channel enable-4 (active high/low OPT2 field programmable) D3 CLK4 Clock output channel - output 4 A4 CLK2 Clock output channel - output 2 B4 EN2 Clock output channel enable-2 (active high/low OPT1 field programmable) C4 EN3 Clock output channel enable-3 (active high/low OPT2 field programmable) D4 CLK3 Clock output channel - output 3 Doc ID 15400 Rev 2 11/39 Device operation STCD22x0, STCD23x0, STCD24x0 3 Device operation 3.1 Operation The STCD22x0, STCD23x0 and STCD24x0 are 2, 3 or 4 buffered clock distribution circuits. They accept the clock (either square wave or sine wave) input from an external clock source and send 2, 3 or 4 buffered rail-to-rail (0 V to VTCXO) square wave outputs to different devices. A 1.8 V, high PSRR LDO (VTCXO) is also integrated in the STCD22x0, STCD23x0 and STCD24x0 which can be used as a voltage supply for the external master clock source (such as a TCXO). This LDO stops the current increase through PMOS when the load current reaches the limit value of the current-limit protection circuit. When the load current falls below the limit values, the current limit is released. Each of the STCD22x0, STCD23x0 and STCD24x0 clock outputs can be enabled individually. If the device connected to the output is in standby, and does not require a clock, the buffered output can be disabled to save power consumption. Once the buffered output is disabled, it is pulled down to GND internally. If all the devices connected are in standby, the STCD22x0, STCD23x0 and STCD24x0 are also put into standby mode (the internal LDO is also shut down) for further power consumption savings. All of the output enable signals are logic ORed with an open drain output (MCREQ) to control the output of the source clock. If the output clock is required by at least one device, the LDO wakes up and the MCREQ activates the clock source. The truth table for enable signals, the master clock request signal and the VTCXO is given in Table 5. The truth table for enable signals, output clock signals and the master clock is given in Table 6. The STCD22x0, STCD23x0 and STCD24x0 have the master clock input detector integrated. If the input master clock peak-to-peak voltage is below the minimum specified level, even if the outputs are enabled, there are no clock outputs and STCD22x0, STCD23x0 and STCD24x0 enter standby mode. Once the master clock peak-to-peak voltage level reaches the minimum value, the output clocks are asserted if the enable pins are active. In Table 5 and 6, the enable signals are active high and the MCREQ is active low. These enable signals can be active high or active low. The enable polarity is described in Section 3.2: Enable polarity. Customers can select different polarity options for different applications. Contact the STMicroelectronics local sales office for availability. Table 5. Note: 12/39 Truth table for clock enable (EN1-4), master clock request (MCREQ) and VTCXO EN1 EN2 EN3 EN4 MCREQ VTCXO 0 0 0 0 1 GND 1 0 0 0 0 1.8 V 1 1 0 0 0 1.8 V - - - - 0 1.8 V 1 1 1 1 0 1.8 V "0" means logic low which disables the clock output and "1" means logic high which enables the clock output. This is an active high truth table. Refer to Section 3.2: Enable polarity for the detailed enable active high/low options. Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Table 6. Device operation Truth table for enable signals (EN1-4), master clock input (MCLK) and output clocks (CLK1-4) EN1 EN2 EN3 EN4 MCLK CLK1 CLK2 CLK3 CLK4 0 0 0 0 X NO CLOCK NO CLOCK NO CLOCK NO CLOCK 1 0 0 0 CLOCK CLOCK NO CLOCK NO CLOCK NO CLOCK 1 1 0 0 CLOCK CLOCK CLOCK NO CLOCK NO CLOCK - - - - - - - - - 1 1 1 1 CLOCK CLOCK CLOCK CLOCK CLOCK Note: "0" means logic low and "1" means logic high. When there is NO CLOCK output, the CLKx pin stays at logic low. "X" means don't care. This is an active high truth table. Refer to Section 3.2: Enable polarity for the detailed enable active high/low options. 3.2 Enable polarity In different applications, the user may have different requirements for enable active high or active low (enable polarities). MCREQ is active low. STMicroelectronics offers different solutions for the user to obtain different enable polarities. In the STCD22x0 and STCD24x0, the user can configure the enable active high or active low on the PC board by connecting OPT1 and OPT2 to either VCC or ground. Refer to Table 7 for detailed information. In the STCD23x0, STMicroelectronics offers 4 enable polarity options by factory programming for the user. Refer to Table 7 for detailed information. The user should note that OPT1 and OPT2 must be connected to either VCC or GND on the PC board and floating on these pins could cause problems. Table 7. STCD22x0, STCD23x0 and STCD24x0 and enable polarity options Part number Enable polarities (OPT1, OPT2) STCD2200 OPT1 connected to VCC, EN1 active high OPT1 connected to GND, EN1 active low OPT2 controls EN2 STCD2400 OPT1 connected to VCC, EN1 and EN2 active high OPT1 connected to GND, EN1 and EN2 active low OPT2 controls EN3 and EN4 STCD2410 OPT1 connected to VCC, EN1 active high OPT1 connected to GND, EN1 active low OPT2 controls EN2, EN3, and EN4 STCD2300 EN1, EN2 and EN3 all active low STCD2310 EN1, EN2 active low, and EN3 active high STCD2320 EN1, EN2 active high and EN3 active low STCD2330 EN1, EN2 and EN3 all active high Enable polarity program method User program Factory program Doc ID 15400 Rev 2 13/39 Application information STCD22x0, STCD23x0, STCD24x0 4 Application information 4.1 LDO input capacitor A 1 µF input capacitor is required for the input of the LDO of the STCD22x0, STCD23x0 and STCD24x0 (the amount of capacitance can be increased without limit). This capacitor must be located as close as possible to the VCC pin on the PC board and return to a clean analog ground. Any good quality ceramic, tantalum or film capacitor can be used for this capacitor. 4.2 LDO output capacitor A 1 µF external capacitor is required for the output VTCXO of the LDO of the STCD22x0, STCD23x0 and STCD24x0. The STCD22x0, STCD23x0 and STCD24x0 are designed to work with low ESR (equivalent series resistance) ceramic capacitors. Make sure the ESR is lower than 500 mΩ to stabilize the VTCXO. Also, capacitor tolerance and variation with temperature must be considered to assure the minimum amount of capacitance provided at all times. This capacitor should be located as close as possible to the VTCXO pin on the PC board. 4.3 LDO BYP pin A 10 nF ceramic capacitor is required for the LDO BYP pin to ensure lower noise. Any good quality ceramic, tantalum or film capacitor can be used. The capacitor should be located as close as possible to the BYP pin on the PC board. 4.4 MCREQ pin In the STCD22x0, STCD23x0, and STCD24x0, the MCREQ pin is open drain and active low. Since MCREQ is active low, if none of the clock output is required, the STCD22x0, STCD23x0 and STCD24x0 are set to standby mode which turns off the internal LDO VTCXO. MCREQ is designed as an open drain structure. A pull-up resistor (50 kΩ recommended) is needed on the PC board to connect this pin to an external 1.8 V supply. Make sure the current flowing through this pin is kept within 3 mA to guarantee the proper function of the circuit. If the MCREQ function is not used in the application, the user can connect this pin to GND or leave it unconnected. Other functions of the STCD2xx0 will not be affected. 14/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 4.5 Application information Phase noise Phase noise is a frequency domain phenomenon and is a critical specification in reference clocks. It is illustrated by a continuous spreading of the energy of the wave mainly caused by random noise. The phase noise is normally specified with a unit of dBc/Hz at a given offset in frequency (for example, 10 kHz) from the carrier wave (for example, 26 MHz). The value of the phase noise is the difference of the power contained within 1 Hz bandwidth of the offset frequency to the power at the carrier frequency. The total phase noise of the clock tree is obtained by adding the additive phase noise of STCD22x0, STCD23x0 and STCD24x0 and the phase noise of the clock source (for example, TCXO) in power which is illustrated in Equation 1. Equation 1 PN T = 10 log(10 PN C 10 + 10 PN X 10 ) < PN A where: PNT is the total phase noise in dBc/Hz PNC is the additive phase noise of STCD22x0, STCD23x0 and STCD24x0 and PNX is the phase noise of clock source Make sure the total phase noise is kept within the phase noise requirement of each application PNA. The user should choose the right TCXO with proper phase noise to meet the requirement. Doc ID 15400 Rev 2 15/39 Application information 4.6 STCD22x0, STCD23x0, STCD24x0 Jitter In the time domain, energy spreading can result in jitter, which is the same phenomenon as phase noise in the frequency domain. As a sine wave passes its zero-crossing or a square wave changes state, the real clock signal transition is not exactly the same as the ideal case, thus causing variation in the waveform transition point. This deviation of the transition point is known as jitter as illustrated in Figure 8. Figure 8. Jitter Ideal transfer point 1 2 3 PI1 4 PI2 PI3 5 PI4 PR1 PR2 PR3 PR4 6 7 8 9 t 10 Real square wave transfer point ai14029 In Figure 8 the square wave ideal transition point should happen at points 1, 2, 3, 4 and 5, and each "ideal" period PI1 to PI4 should be the same, thus no time jitter has occurred. Actually, the real transition point happens at points 6, 7, 8, 9 and 10, thus causing "real" periods PR1 to PR4 to not be the same, and exhibit visible jitter. If each of the real periods of the cycles (PR1 to PR4) is measured, period jitter is obtained. The cycle-to-cycle jitter is also obtained by calculating the difference between two adjacent periods (for example, PR2PR1, PR3-PR2 …). These periods of jitter are described as peak-to-peak jitter and are calculated by subtracting the minimum value from the maximum value or may also be described by the root-meansquare (RMS) value, representing one standard deviation of the Gaussian distribution. 4.7 Output trace line The STCD22x0, STCD23x0 and STCD24x0 is designed with maximum 50 Ω impedance output. On the PC board, a 50 Ω transmission line with proper series termination should be used to avoid signal distortion and reflection. 16/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 4.8 Application information Typical application connections The STCD2400 clock distribution circuit requires a source clock input as the reference clock (for example, XO). At most 4 devices can be connected to the outputs. The typical application circuit using STCD2400 is shown in Figure 9 and 10 . The MCREQ is open drain output and active low. A pull-up resistor is needed to connect to an external 1.8 V supply VIO. If the clock source enable is active high, the user can use VTCXO as the master clock enable control signal, please refer to Figure 4 for the detailed connection. In Figure 9, the clock from XO is distributed to the TD-SCDMA transmitter and receiver and GSM transceiver separately to be used as reference clocks. In Figure 10, the buffer #4 output is fed into the Bluetooth system. In order to allow minimum power consumption, a Bluetooth system always has a clock request feature. If the Bluetooth system does not require the clock, the clock request disables the clock output. The enable pins can also be connected to an external 1.8 V supply to force the buffer to always be on. In Figure 9 and 10, all the output clock enables are active high since both OPT1 and OPT2 are connected to VCC. Figure 9. Typical application circuit using STCD24x0 for RF ends of TDSCDMA/GSM dual-mode mobile phone VCC Mode Selection C STCD24x0 C VIO BYP VTCXO C XO EN4 CLK4 TD-SCDMA Transmitter EN3 CLK3 VDD MCREQ EN VCC MCLK EN2 CLK2 TD-SCDMA Receiver EN1 OPT1 CLK1 OPT2 GND GSM Transceiver ai14022 Doc ID 15400 Rev 2 17/39 Application information STCD22x0, STCD23x0, STCD24x0 Figure 10. Typical application circuit using STCD24x0 for baseband peripherals in mobile phone VCC BT_External_Req Internal_Req C STCD24x0 BYP Bluetooth EN4 CLK4 C VIO VTCXO C VDD EN XO VCC MCREQ MCLK EN3 CLK3 WLAN EN2 CLK2 GPS EN1 OPT1 CLK1 OPT2 GND Other device ai14023 18/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Typical operating characteristics Typical operating characteristics are at TA = 25 °C, Cload = 20 pF at each channel, VCC = 3.8 V, fMCLK = 26 MHz. Figure 11. Quiescent current vs. supply voltage (EN1 = EN2 = EN3 = EN4 = 1, no master clock input) Quiescent current ICC (µA) 75 74 73 72 71 70 69 68 67 2. 7 2. 3 3. 1 4. 3 3. 9 3. 5 4. 7 5. 5 5.1 Supply voltage VCC (V) AM00496v1 Figure 12. Quiescent current vs. temperature (EN1 = EN2 = EN3 = EN4 = 1, Cload = 20 pF, no master clock input) Quiescent current ICC (µA) 5 Typical operating characteristics 100 80 60 40 20 0 –30 –20 0 25 50 85 Temperature (°C) AM00497v1 Doc ID 15400 Rev 2 19/39 Typical operating characteristics STCD22x0, STCD23x0, STCD24x0 Figure 13. Active current vs. temperature (EN1 = EN2 = EN3 = EN4 = 1, Cload = 20 pF, VCC = 3.8 V, fMCLK = 26 MHz) Active current IACT (mA) 8 6 1 channel enabled 2 channels enabled 4 3 channels enabled 4 channels enabled 2 0 –30 –20 0 25 50 85 Temperature (°C) AM00498v1 Standby current ISB (µA) Figure 14. Standby current vs. supply voltage (EN1 = EN2 = EN3 = EN4 = 0, no master clock input) 0.25 0.2 0.15 0.1 0.05 2. 3 2. 5 2. 7 2. 9 3. 1 3. 3 3. 5 3. 7 3. 9 4. 1 4. 3 4. 5 4. 7 4. 9 5. 1 5. 3 5. 5 0 Supply voltage VCC (V) 20/39 Doc ID 15400 Rev 2 AM00500v1 STCD22x0, STCD23x0, STCD24x0 Typical operating characteristics Active current IACT (mA) Figure 15. Active current vs. supply voltage (EN1 = EN2 = EN3 = EN4 = 1, fMCLK = 26 MHz, Cload = 20 pF) 6 5 1 channel enabled 4 2 channels enabled 3 3 channels enabled 2 4 channels enabled 1 0 2. 3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 Supply voltage VCC (V) AM00612v1 Active current IACT (mA) Figure 16. Active current vs. master clock input voltage level (EN1 = EN2 = EN3 = EN4 = 1, fMCLK = 26 MHz, Cload = 20 pF) 7 6 1 channel enabled 5 2 channels enabled 4 3 3 channels enabled 2 4 channels enabled 1 0 0. 5 0. 8 1. 1 1. 4 1.8 Master clock fMCLK voltage level (Vpp) AM00613v1 Figure 17. Active current vs. master clock frequency (EN1 = EN2 = EN3 = EN4 = 1, Cload = 20 pF) Active current IACT (mA) 15 10 1 channel enabled 2 channels enabled 3 channels enabled 4 channels enabled 5 0 5 10 15 20 25 30 35 40 45 50 Master clock frequency fMCLK (MHz) Doc ID 15400 Rev 2 55 AM00614v1 21/39 Typical operating characteristics STCD22x0, STCD23x0, STCD24x0 Figure 18. STCD2400 recovery time from standby to active (VTCXO is on) Figure 19. STCD2400 recovery time from off to on (VTCXO first in standby) 22/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Typical operating characteristics Figure 20. Output clock rise/fall time (Cload = 40 pF) Doc ID 15400 Rev 2 23/39 Typical operating characteristics STCD22x0, STCD23x0, STCD24x0 Figure 21. STCD2400 power-up sequence Figure 22. STCD2400 power-down sequence 24/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Typical operating characteristics Figure 23. Phase noise input (from the clock source, 26 MHz square wave XO KC2520C26 from Kyocera) Doc ID 15400 Rev 2 25/39 Typical operating characteristics STCD22x0, STCD23x0, STCD24x0 Figure 24. Phase noise output (include the clock source and STCD2400 additive phase noise) 26/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 6 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8. Absolute maximum ratings Symbol TSTG TSLD(1) TJ 1. Parameter Value Unit Lead-free bump solder temperature for 10 seconds 260 Maximum junction temperature 150 °C °C °C –0.3 to 6 V Storage temperature (VCC off) –55 to 150 VCC Supply voltage VIN Input clock voltage –0.3 to 3.6 V VEN Voltage on enable pins –0.3 to 3.6 V VOPT Optional pins voltage –0.3 to 6 V MCREQ Master clock request –0.3 to 3.6 V Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. Doc ID 15400 Rev 2 27/39 DC and AC parameters 7 STCD22x0, STCD23x0, STCD24x0 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in Table 9. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 9. Operating and AC measurement conditions Parameter Condition Unit 2.5 to 5.1 V Input source clock voltage (MCLK) 0 to 1.8 V Output clock voltage (CLK1-4) 0 to 1.8 V Device enable voltage (EN1-4) 0 to 1.8 V Source clock request voltage (MCREQ) 0 to 1.8 V Optional pins voltage (OPT1, OPT2) 0 to VCC V Ambient operating temperature (TA) –20 to +85 °C Flip-chip thermal resistance (Rthja) 90 °C/W VCC supply Table 10. Sym. DC and AC characteristics Condition(1) Parameter Min Typ Max Unit 5.1 V 1.85 V 20 mA VTCXO (low dropout output) VCC Supply voltage VTCXO Output voltage IO Maximum output current VOACC ICL Total output accuracy regulation(3) Line IREG Load regulation(3) 28/39 ILOAD = 5 mA (2) Current limit protection VREG ITR 2.5 Load transient(3) 1.75 1.8 –5% 5% VTCXO = 0 V 30 90 mA ILOAD = 20 mA 0.5 10 mV ILOAD = 10 µA to 20 mA 0.4 10 mV ILOAD = 10 µA to 20 mA ITR = 1 µs 100 110 mV ILOAD = 20 mA to 10 µA ITR = 1 µs 100 110 mV Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Table 10. DC and AC parameters DC and AC characteristics (continued) Sym. Parameter PSRR Power supply rejection ratio(3)(4) Condition(1) Min Typ VCC = 2.5 V to 5.1 V, Fripple = 217 Hz, ILOAD = 20 mA 60 67 VCC = 2.5 V to 5.1 V, Fripple = 1 kHz, ILOAD = 20 mA 40 60 VCC = 2.5 V to 5.1 V, Fripple = 1 MHz, ILOAD = 20 mA 40 VCC = 2.5 V to 5.1 V, Fripple = 3.25 MHz, ILOAD = 20 mA 40 Max Unit dB eN Output noise voltage(3) ILOAD = 5 mA, 10 Hz to 100 kHz 45 tST Startup time(3) VTCXO > 90%, ILOAD = 10 µA to 20 mA 150 400 µs tF Output voltage falling time(3) VTCXO < 10%, ILOAD = 0 120 400 µs 10 26 52 MHz 40 50 60 % Square wave 0.8 1.8 VTCXO + 0.2 Vpp Sine wave 0.8 1 VTCXO + 0.2 Vpp µVrms Clock distribution fMCLK Master clock (from external clock source) Square wave / sine wave fCLK duty cycle VIN Input clock voltage level(5) VOH Output high CL = 20 pF VOL Output low CL = 20 pF Tr/f IQC ICC Rise/fall time(6) Quiescent current(7) (including LDO) Active current(8) ISB Standby current (including LDO) RIN Input impedance VTCXO – 0.05 VTCXO V 0.05 V 2 5 ns 1 channel enabled 80 200 2 channels enabled 80 200 3 channels enabled 80 200 4 channels enabled 80 200 1 channel enabled 1.9 2 channels enabled 3.0 3 channels enabled 4.1 4 channels enabled 5.2 All buffers off 0.2 CL =10 pF~ 40 pF 1 µA mA > 100 Doc ID 15400 Rev 2 1 µA kΩ 29/39 DC and AC parameters Table 10. STCD22x0, STCD23x0, STCD24x0 DC and AC characteristics (continued) Sym. Parameter CIN Condition(1) Typ Max Unit Input capacitance 3 4 pF IOO Output to output isolation 45 dB IOI Output to input isolation 45 dB VENH VENL (9) For EN1-EN4 (9) For EN1-EN4 Enable voltage high Enable voltage low Min 1.2 V 0.6 VOPTH OPT pins voltage high For OPT1 and OPT2 VOPTL OPT pins voltage low For OPT1 and OPT2 GND at 1 kHz offset –135 at 10 kHz offset –145 at 100 kHz offset –150 rms value 10 ps rms value 10 ps STCD2xx0 active 1 PN tJP tJC Additive phase noise(3)(10) Additive period jitter(3) Additive cycle-cycle jitter(3) tRECB Buffer recovery time from off to on tRECC STCD2xx0 recovery time from standby to active (include LDO wakeup time) tPD Input to output propagation delay(3) CL Capacitive load for each channel RL Resistive load for each channel ZOUT Output impedance for each channel VCC –0.3 V Voltage transfer at 50% VCC V GND+0.3 V dBc/ Hz 10 µs 500 µs 3.5 6 ns 20 40 pF 10 kΩ 50 Ω 1. Valid for ambient operating temperature: TA = –20 °C to 85 °C; VCC = 2.5 V to 5.1 V; typical TA = 25 °C; load capacitance = 20 pF, fMCLK = 26 MHz (except where noted). 2. Total accuracy includes line and load regulation, temperature and process condition. It does not include load and line transients. 3. Simulated and determined via design and not 100% tested. 4. Ripple voltage = 0.1 Vpp. 5. Clock input voltage level should not exceed VTCXO voltage. 6. The rise time is measured when clock edge transfers from 10% VCC to 90%VCC. The fall time is measured when clock edge transfers from 90%VCC to 10%VCC. The output rise/fall time is guaranteed for all input slew rates. 7. The quiescent current is measured when the enable pins are active, but with no input master clock signal (fMCLK = 0 Hz). 8. The active current depends on the input master clock Vpp and frequency and the load condition. The typical test condition is 26 MHz with 1.8 Vpp master clock input, CL = 20 pF. 9. The test condition is VENH = 1.8 V and VENL = 0 V. When output enables simultaneously, there is no intentional skew in design between the output clocks. 10. Guaranteed for all input clock slew rates. 30/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 25. Flip Chip 12-bump, package mechanical outline 7504892_L(E) Doc ID 15400 Rev 2 31/39 Package mechanical data Table 11. STCD22x0, STCD23x0, STCD24x0 Flip Chip 12-bump, package mechanical data mm in Symbol Min Typ Max Min Typ Max A 0.55 0.61 0.66 0.022 0.024 0.026 A1 0.17 0.21 0.24 0.007 0.008 0.009 A2 0.38 0.40 0.42 0.015 0.016 0.017 b 0.22 0.26 0.30 0.008 0.010 0.012 D 1.55 1.60 1.65 0.061 0.063 0.065 D1 E 1.20 1.15 E1 1.25 0.045 0.80 0.047 0.049 0.031 e 0.36 0.40 0.44 0.014 0.016 0.017 DE 0.18 0.20 0.22 0.007 0.008 0.009 f 0.185 0.195 0.210 0.007 0.008 0.008 ccc 32/39 1.20 0.047 0.05 Doc ID 15400 Rev 2 0.002 STCD22x0, STCD23x0, STCD24x0 Package mechanical data Figure 26. Flip Chip 16-bump, package mechanical outline 7504892_L(A) Doc ID 15400 Rev 2 33/39 Package mechanical data Table 12. STCD22x0, STCD23x0, STCD24x0 Flip Chip 16-bump, package mechanical data mm in Symbol Min Typ Max Min Typ Max A 0.55 0.61 0.66 0.022 0.024 0.026 A1 0.17 0.21 0.24 0.007 0.008 0.009 A2 0.38 0.40 0.42 0.015 0.016 0.017 b 0.22 0.26 0.30 0.008 0.010 0.012 D 1.55 1.60 1.65 0.061 0.063 0.065 D1 E 1.20 1.55 E1 1.65 0.061 1.20 0.063 0.065 0.047 e 0.36 0.40 0.44 0.014 0.016 0.017 SD 0.18 0.20 0.22 0.007 0.008 0.009 SE 0.18 0.20 0.22 0.007 0.008 0.009 f 0.185 0.195 0.210 0.007 0.008 0.008 ccc 34/39 1.60 0.047 0.05 Doc ID 15400 Rev 2 0.002 STCD22x0, STCD23x0, STCD24x0 Package mechanical data Figure 27. Flip Chip 12-bump tape and reel specifications 12bFC Doc ID 15400 Rev 2 35/39 Package mechanical data STCD22x0, STCD23x0, STCD24x0 Figure 28. Flip Chip 16-bump tape and reel specifications 16bFC 36/39 Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 9 Part numbering Part numbering Table 13. Ordering information scheme Example: STCD 22 0 0 F3 5 F Device type STCD = clock distribution Channels 22 = 2-channel(1) 23 = 3-channel(1) 24 = 4-channel Enable polarity STCD22x0 (user programmable) 0 = OPT1 sets EN1, OPT2 sets EN2 STCD23x0 (factory programmable) 0 = EN1, EN2, EN3 1 = EN1, EN2, EN3 2 = EN1, EN2, EN3 3 = EN1, EN2, EN3 STCD24x0 (user programmable) 0 = OPT1 sets EN1 and EN2, OPT2 sets EN3 and EN4 1 = OPT1 sets EN1, OPT2 sets EN2, EN3, and EN4(1) Master clock request (MCREQ) 0 = MCREQ active low Package F3 = Flip chip, lead-free, pitch = 400 µm, bump = 250 µm (12-bump for 2- or 3-channel, 16-bump for 4-channel) Temperature range 5 = –20 °C to +85 °C Shipping method F = ECOPACK® package, tape & reel 1. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 15400 Rev 2 37/39 Revision history 10 STCD22x0, STCD23x0, STCD24x0 Revision history Table 14. 38/39 Document revision history Date Revision Changes 26-Aug-2009 1 Initial release. 11-Jan-2010 2 Updated footnote 5 in Table 10: DC and AC characteristics. Doc ID 15400 Rev 2 STCD22x0, STCD23x0, STCD24x0 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15400 Rev 2 39/39