STMICROELECTRONICS STDVE003A

STDVE003A
Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer
Features
■
Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
■
Conforms to the transition minimized
differential signaling (TMDS) voltage standard
on input and output channels
■
340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
■
3.4 Gbps data rate per channel
■
Fully automatic adaptive equalizer
■
Single supply VCC: 3.135 to 3.465 V
■
ESD: ±8 KV contact for all I/Os
■
Integrated open-drain I2C buffer for display
data channel (DDC)
■
5.3 V tolerant DDC and HPD I/Os
■
Lock-up free operation of I2C bus
■
0 to 400 kHz clock frequency for I2C bus
■
Low capacitance of all the channels
■
Equalizer regenerates the incoming attenuated TMDS signal
■
Buffer drives the TMDS outputs over long PCB
track lengths
■
Low output skew and jitter
■
Tight input thresholds reduce bit error rates
■
On-chip selectable 50 Ω input termination
■
Low ground bounce
■
Data and control inputs provide undershoot
clamp diode
■
Available in TQFP80 package
■
-40°C to 85°C operating temperature range
TQFP80
Description
The STDVE003A integrates a 4-channel 3.4 Gbps
TMDS equalizer and a 3:1 switch to select one of
the three HDMI ports. The 3-input HDMI ports can
be either external ports or internal sources. Highspeed data paths and flow-through pinout
minimize the internal device jitter and simplify the
board layout. The equalizer overcomes the
intersymbol interference (ISI) jitter effects from
lossy cables. The buffer/driver on the output can
drive the TMDS output signals over long
distances. In addition to this, STDVE003A
integrates the 50 Ω termination resistor on all the
input channels to improve performance and
reduce board space. The device can be placed in
a low-power mode by disabling the output current
drivers. The STDVE003A is ideal for advanced TV
and STB applications supporting HDMI/DVI
standard. The differential signal from the
HDMI/DVI ports can be routed through the
STDVE003A to guarantee good signal quality at
the HDMI receiver. Designed for very low skew,
jitter and low I/O capacitance, the switch
preserves the signal integrity to pass the stringent
HDMI compliance requirements.
■
Evaluation kit is available
Table 1.
Device summary
Order code
Operating temperature
Package
Packaging
STDEV003ABTR
-40°C to 85°C
TQFP80
Tape and reel
July 2008
Rev 3
1/41
www.st.com
41
Contents
STDVE003A
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1
4
5
SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8
Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5
Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . 26
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2
Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.1
I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2/41
STDVE003A
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gain frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
OE_N operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC specifications for TMDS differential ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs . . . . . . . . . . . . . . . . . 19
Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DDC I/O pins (switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Status pins (Y_HPD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Status pins (A_HPD, B_HPD, C_HPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status pins (Y_HPD, A_HPD, B_HPD, C_HPD, SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TQFP-80 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3/41
List of figures
STDVE003A
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
4/41
STDVE003A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DDC I2C bus repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STDVE003A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin configuration (TQFP80 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STDVE003A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TQFP80 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TQFP80 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STDVE003A
1
Block diagram
Block diagram
Figure 1.
STDVE003A block diagram
HDMI input
port A
HDMI input
port B
3:1
HDMI
input
select
switch
Input stage
Output
driver/
transmitter
Equalizer
HDMI output
port Y
HDMI input
port C
2
2
DDC port A
DDC
switch
2
DDC port B
2
IC
repeater
DDC
port Y
2
DDC port C
S1,S2,S3
HPD port A
HPD
port Y
HPD
analog
switch
HPD port B
HPD port C
CS00061
Figure 2.
Equalizer functional diagram (one signal pair)
S1, S2, S3
Data+
Data+
Data-
50 Ω
termination
selectable
Switch
(3:1)
Pre-amp
Equalizer
Quantizer
Output
I
driver
Data-
OE_N
Current control
REXT
AM00715V1
5/41
Block diagram
STDVE003A
Figure 3.
DDC I2C bus repeater
2
I C bus repeater
Y_DDC_SDA
A_DDC_SDA
B_DDC_SDA
C_DDC_SDA
Switch
A_DDC_SCL
B_DDC_SCL
Y_DDC_SCL
C_DDC_SCL
S1, S2, S3
CS00062
1.1
Application diagrams
Figure 4.
STDVE003A in a digital TV
Game
console
DVD-R
STB
Digital TV
STDVE003A
HDMI receiver
CS00063
6/41
STDVE003A
Pin configuration
DDC_1_PWR
HPD2
VCC
62
61
63
GND
SCL2
SDA2
65
64
67
66
A21
B21
GND
68
VCC
B22
70
69
GND
A22
71
72
A23
74
B23
75
73
A24
B24
VCC
77
76
VCC
GND
78
80
HPD1
Pin configuration (TQFP80 package)
79
1
60
59
DDC_2_PWR
GND
SDA1
2
58
A34
SCL1
3
57
B34
GND
4
56
VCC
B11
5
55
A33
A11
6
54
B33
VCC
7
53
GND
A32
B12
8
52
A12
9
51
GND
10
50
B13
11
49
STDVE003A
B32
VCC
A31
37
38
39
40
SCL_SINK
SDA_SINK
HPD_SINK
Y4
GND
24
25
GND
36
23
S3
35
22
Z1
21
20
S1
DDC_Y_PWR
GND
41
34
19
EQ_BOOST
Y1
42
32
43
33
17
18
VCC
VCC
REXT
31
SDA3
HPD3
Z2
44
Y2
16
GND
GND
30
SCL3
45
29
46
15
Z3
14
A14
Y3
B14
28
B31
GND
26
48
47
27
12
13
Z4
A13
VCC
VCC
Figure 5.
S2
2
Pin configuration
VCC
OE_N
DDC_3_PWR
CS00064
Table 2.
Pin description
Pin number
Pin name
Type
Function
1
DDC_1_PWR
Power
External power to connect the pull-up resistor on
DDC A ports. Connect to GND if unused.
2, 3
SDA1, SCL1
I/O
Port1 DDC bus data and clock lines
4
GND
Power
Ground
5, 6
B11, A11
Input,TMDS
Port 1 differential inputs for channel 1
7
VCC
Power
Supply voltage (3.3 V ± 5%)
8, 9
B12, A12
Input,TMDS
Port 1 differential inputs for channel 2
10
GND
Power
Ground
11, 12
B13, A13
Input,TMDS
Port 1 differential inputs for channel 3
13
VCC
Power
Supply voltage (3.3 V ± 5%)
14, 15
B14, A14
Input, TMDS
Port 1 differential inputs for channel 4
7/41
Pin configuration
STDVE003A
Table 2.
8/41
Pin description (continued)
Pin number
Pin name
Type
Function
16
GND
Power
Ground
17
VCC
Power
Supply voltage (3.3 V ± 5%)
18
REXT
Analog
Connect to GND through a 4.7 KΩ ± 1% precision
reference resistor. Sets the output current to
generate the output voltage compliant with TMDS
19
EQ_BOOST
Input
Provides equalizer boost function. Set to L for
short cables and H for long cables.
20
DDC_Y_PWR
Power
External power to connect the pull-up resistor on
DDC Y ports. Connect to GND if unused.
21, 23
S1,S2,S3
Input
Source select inputs
24
GND
Power
Ground
25, 26
Y4, Z4
Output,
TMDS
Channel 4 differential outputs
27
VCC
Power
Supply voltage (3.3 V ± 5%)
28, 29
Y3, Z3
Output,
TMDS
Channel 3 differential outputs
30
GND
Power
Ground
31, 32
Y2, Z2
Output,
TMDS
Channel 2 differential outputs
33
VCC
Power
Supply voltage (3.3 V ± 5%)
34, 35
Y1, Z1
Output,
TMDS
Channel 1 differential outputs
36
GND
Power
Ground
37
GND
Power
Ground
38
SCL_SINK
I/O
Sink side DDC bus clock line
39
SDA_SINK
I/O
Sink side DDC bus data line
40
HPD_SINK
Input
Sink side hot plug detector input
High: 5 V power signal asserted from source to
sink and EDID is ready.
Low: No 5 V power signal is asserted from source
to sink or EDID is not ready.
41
DDC_3_PWR
Power
External power to connect the pull-up resistor on
DDC C ports. Connect to GND if unused.
42
OE_N
Input
Output enable, active low
43
VCC
Power
Supply voltage (3.3 V ± 5%)
44
HPD3
Output
Port 3 hot plug detector output. Open drain output.
Connect an external resistor according to the
HDMI specification.
45
SDA3
I/O
Port 3 DDC bus data line
46
SCL3
I/O
Port 3 DDC bus clock line
STDVE003A
Pin configuration
Table 2.
Pin description (continued)
Pin number
Pin name
Type
Function
47
GND
Power
48, 49
B31, A31
Input, TMDS
50
VCC
Power
51, 52
B32, A32
Input, TMDS
53
GND
Power
54, 55
B33, A33
Input, TMDS
56
VCC
Power
57, 58
B34, A34
Input, TMDS
59
GND
Power
Ground
60
DDC_2_PWR
Power
External power to connect the pull-up resistor on
DDC B ports. Connect to GND if unused.
61
VCC
Power
Supply voltage (3.3 V ± 5%)
62
HPD2
Output
Port 2 hot plug detector output. Open drain output.
Connect an external resistor according to the
HDMI specification.
63
SDA2
I/O
Port 2 DDC bus data line
64
SCL2
I/O
Port 2 DDC bus clock line
65
GND
Power
Ground
66
GND
Power
Ground
67, 68
B21, A21
Input, TMDS
69
VCC
Power
70, 71
B22, A22
Input, TMDS
72
GND
Power
73, 74
B23, A23
Input, TMDS
75
VCC
Power
76, 77
B24, A24
Input, TMDS
78
GND
Power
Ground
79
VCC
Power
Supply voltage (3.3 V ± 5%)
80
HPD1
Ground
Port 3 differential inputs for channel 1
Supply voltage (3.3 V ± 5%)
Port 3 differential inputs for channel 2
Ground
Port 3 differential inputs for channel 3
Supply voltage (3.3 V ± 5%)
Port 3 differential inputs for channel 4
Port 2 differential inputs for channel 1
Supply voltage (3.3 V ± 5%)
Port 2 differential inputs for channel 2
Ground
Port 2 differential inputs for channel 3
Supply voltage (3.3 V ± 5%)
Port 2 differential inputs for channel 4
Port 1 hot plug detector output. Open drain output.
Connect an external resistor according to the
HDMI specification.
9/41
Functional description
3
STDVE003A
Functional description
The STDVE003A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standard like TMDS. The device passes the
differential inputs from a video source to a common display when it is in the active mode of
operation. The device conforms to the TMDS standard on both inputs and outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE003A result in a very
small propagation delay. The device integrates SPDT-type switches for 3 differential data
TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for
DDC and HPD line switching with I2C repeater on the DDC lines.
The I2C interface of the selected input port is linked to the I2C interface of the output port,
and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the
unused ports, the I2C interfaces are isolated and the HPD pins are driven to L state.
3.1
Adaptive equalizer
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when VCC is absent or 0 V. In all other cases, the 50 Ω termination resistors
on input channels are present.
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.
The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The default setting of EQ_BOOST = L is
recommended for optimized operation.
Table 3.
10/41
Gain frequency response
Frequency
Gain in dB
Gain in dB
(MHz)
(EQ_BOOST = 0)
(EQ_BOOST = 1)
225
3
6.5
325
5
8.5
410
6.5
11
825
11
16
1650
16
21.5
STDVE003A
Figure 6.
Functional description
STDVE003A gain vs. frequency
The STDVE003A equalizer is fully adaptive and automatic in function. The default setting of
EQ_BOOST = L is recommended for optimal operation. The equalizer’s performance is
optimized for all frequencies over the cable lengths from 1 m to 25 m at EQ_BOOST = L.
If cable lengths greater than 25 m are desired in application, then EQ_BOOST = H setting is
recommended.
Input termination
The STDVE003A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all
its differential input channels. External terminations are not required. This gives better
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line. Since the
output driver consists of current steering devices, an output voltage is not generated without
a termination resistor. Output voltage levels are dependent on the value of the total
termination resistance. The STDVE003A produces TMDS output levels for point-to-point
links that are doubly terminated (100 Ω at each end). With the typical 10 mA output current,
the STDVE003A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a
termination line terminated at each end. The input terminations are selectable thus saving
power for the unselected ports.
Output buffers
Each differential output of the STDVE003A drives external 50 Ω load (pull-up resistor) and
conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential
current-steering devices.
The driver outputs are short-circuit current limited and are high-impedance to ground when
OE_N = H or the device is not powered. The current steering architecture requires a
resistive load to terminate the signal to complete the transmission loop from VCC to GND
through the termination resistor. Because the device switches the direction of the current
flow and not voltage levels, the output voltage swing is determined by VCC minus the voltage
drop across the termination resistor. The output current drivers are controlled by the OE_N
pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate
internal current mirrors of a stable reference current which is generated by band-gap voltage
11/41
Functional description
STDVE003A
across the REXT. The differential output driver provides a typical 10 mA current sink
capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses a
lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
3.2
Operating modes
Table 4.
OE_N operating modes
Input
Output
Function
OE_N
IN+
(ports A1, A2 or A3)
IN(ports B1, B2 or B3)
OUT+
OUT-
L
H
L
H
L
Active mode
L
L
H
L
H
Active mode
H
X
X
Hi-Z
Hi-Z
Low power mode
The OE_N input activates a hardware power down mode. When the power down mode is
active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off
and disabled.
Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a
delay associated with turning on band-references and input/output buffer circuits.
12/41
STDVE003A
3.2.1
Functional description
SEL operating modes
The active source is selected by configuring source select inputs, S1, S2 and S3. The
selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C
interface of the selected input port is linked to the I2C interface of the output port, and the
hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused
ports, the I2C interfaces are isolated, and the HPD pins are kept low.
Table 5.
SEL operating modes
Control pins
I/O selected
S1
S2
S3
Y/Z
H
X
X
A1/B1
L
H
X
L
L
L
L
SCL_SINK
Hot-plug detect status
HPD1
HPD2
HPD3
SCL1
SDA1
HPD_SINK
L
L
A2/B2
SCL2
SDA2
L
HPD_SINK
L
H
A3/B3
SCL3
SDA3
L
L
HPD_SINK
L
None
(Z)
None (Z)
L
L
L
SDA_SINK
H: logic high; L: logic low; X: don't care; Z: high impedance
3.3
HPD pins
The input pin HPD_SINK is 5 V tolerant, allowing direct connection to 5 V signals. The
switch is able to pass both 0 V and 5 V signal levels. The HPD_SINK is an input pin while
the A_HPD, B_HPD and C_HPD are open-drain outputs.
3.4
DDC channels
The DDC channels are designed with a bidirectional NMOS gate, providing 5 V signal
tolerance. The 5 V tolerance allows direct connection to a standard I2C bus, thus eliminating
the need for a level shifter. There should be external pull-up resistors on either side of the
device on both the SCL and SDA lines.
13/41
Functional description
3.5
STDVE003A
I2C DDC line repeater
The device contains two identical bidirectional open-drain, non-inverting buffer circuits that
enable I2C DDC bus lines to be extended without degradation in system performance. The
STDVE003A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C
bus, while retaining all the operating modes and features of the I2C system. This enables
two buses of 400 pF bus capacitance to be connected in an I2C application. These buffers
are operational from a supply V of 3.0 V to 3.6 V.
The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. The
STDVE003A enables the system designer to isolate the two halves of a bus,
accommodating more I2C devices or longer trace lengths. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz
bus is isolated when 400 kHz operation of the other bus is required. The STDVE003A can
be used to run the I2C bus at both 5 V and 3.3 V interface levels.
The S1, S2 and S3 (SEL) lines act as control signals for the corresponding A, B or C ports.
Note that the SEL line has an internal pull-down resistor. The SEL line should not change
state during an I2C operation, because disabling during bus operation hangs the bus and
enabling part way through a bus cycle could confuse the I2C parts being enabled. The SEL
input should change state only when the global bus and the repeater port are in idle state, to
prevent system failures.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage
of each internal buffer must be 70 mV or more below the output low level, when the output
internally is driven low. This prevents a lock-up condition from occurring when the input low
condition is released.
As with the standard I2C system, pull up resistors are required to provide the logic high
levels on the buffered bus. The STDVE003A has standard open collector configuration of
the I2C bus. The size of the pull up resistors depends on the system, but each side of the
repeater must have a pull up resistor.
This part is designed to work with standard mode and fast mode I2C devices. Standard
mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA
in a generic I2C system where standard mode devices and multiple masters are possible.
Under certain conditions, higher termination currents can be used.
3.6
Power-down condition
The SEL line has an internal pull-down resistor which prevents it from going into an
unknown state in the absence of supply to STDVE003A. Also there is no ESD protection
diode to supply on any of the IOs. This prevents a reverse current flow condition when the
main box is switched off while the TV is switched on.
The OE_N is used to disable most of the internal circuitry of STDVE003A that puts the
device in a low power mode of operation.
3.7
Bias
The bandgap reference voltage over the external REXT reference resistor sets the internal
bias reference current. This current and its factors (achieved by employing highly accurate
and well matched current mirror circuit topologies) are generated on-chip and used by
14/41
STDVE003A
Functional description
several internal modules. The 10 mA current used by the transmitter block is also generated
using this reference current. It is important to ensure that the REXT value is within the ±1%
tolerance range of its typical value.
Table 6.
Bias parameter
Parameter
Min
Bandgap voltage
Typ
Max
1.2
Unit
V
The output voltage swing depends on 3 components: supply voltage (Vsupply), termination
resistor (RT) and current drive (Idrive). The supply voltage can vary from 3.3 V ±5%,
termination resistor can vary from 50 Ω ±10%.
The voltage on the output is given by:
Vsupply −Idrive x RT.
The variation on Idrive must be controlled to ensure that the voltage on HDMI output is within
the HDMI specification under all conditions.
This is achieved when:
400 mV ≤Idrive x RT ≤600 mV with typical value centered at 500 mV.
3.8
Timing between HPD and DDC
It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is
complete.
As soon as the discovery is finished by the HPD detection, the configuration data is
exchanged between a source and sink through the I2C DDC interface. The STDVE003 Afs
DDC interface is ready for communication as soon as the power supply to the chip is
present and stable. When the desired port is enabled and the chip is out of shutdown mode,
the I2C DDC lines can be used for communication.
Thus, as soon as the HPD detection sequence is complete, the DDC interface can be
readily used. There is no delay between the HPD detection and I2C DDC interface to be
ready.
15/41
Maximum rating
4
STDVE003A
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 7.
Absolute maximum ratings
Symbol
Parameter
VCC
VI
IO
TSTG
TL
VESD
Table 8.
16/41
Value
Unit
Supply voltage to ground
-0.5 to +4.0
V
DC input voltage (TMDS ports)
1.7 to +4.0
V
SEL (S1, S2, S3), OE_N
-0.5 to +4.0
V
A_DDC_SDA, A_DDC_SCL, B_DDC_SDA, B_DDC_SCL,
C_DDC_SDA, C_DDC_SCL,Y_DDC_SDA, Y_DDC_SCL,
Y_HPD, A_HPD, B_HPD, C_HPD
-0.5 to +6.0
V
120
mA
-65 to +150
°C
Lead temperature (10 sec)
300
°C
Contact discharge
Electrostatic discharge voltage on all IOs as per IEC610004-2 standard
±8
kV
DC output current
Storage temperature
Thermal data
Symbol
Parameter
TQFP-80
Unit
ΘJA
Thermal coefficient (junction-ambient)
48
°C/W
STDVE003A
Maximum rating
4.1
Recommended operating conditions
4.2
DC electrical characteristics
TA = -40 to +85 °C, VCC = 3.3 V ± 5% (a)
Table 9.
Power supply characteristics
Value
Symbol
VCC
ICC
Parameter
Test condition
Supply voltage
Supply current
Unit
Min
Typ
Max
3.135
3.3
3.465
All inputs/outputs
are enabled.
Inputs are
terminated with
280
50 Ω to VCC.
V
mA
VCC = 3.465 V
Data rate =
3.4 Gbps
Table 10.
DC specifications for TMDS differential inputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
0
150
VTH
Differential input high
threshold
(peak-to-peak)
VCC = 3.465 V
over the entire
VCMR
VTL
Differential input low
threshold
VCC = 3.465 V
over the entire
VCMR
-150
VID
Differential input
voltage
(peak-to-peak)(1)
VCC = 3.465 V
150
1560
mV
VCC - 0.3
VCC - 0.04
V
VCMR
CIN
Common mode
voltage range
Input capacitance
IN+ or IN- to
GND
F = 1 MHz
0
3.5
mV
mV
pF
1. Differential output voltage is defined as | (OUT+ - OUT-) |.
Differential input voltage is defined as | (IN+ - IN-) |.
a. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
17/41
Maximum rating
Table 11.
STDVE003A
DC specifications for TMDS differential ouputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VOH
Single-ended high level
output voltage
VCC-10
VCC+10
mV
VOL
Single-ended low level
output voltage
VCC-600
VCC-400
mV
Single ended output
swing voltage
VCC = 3.3 V
RTERM = 50 Ω
400
500
600
mV
VOD
Differential output
voltage
(peak-to-peak)(1)
VCC = 3.3 V
RTERM = 50 Ω
800
1000
1200
mV
IOH
Differential output high
level current
0
50
µA
IOL
Differential output low
level current
8
12
mA
|ISC|
Output driver shortcircuit current
(continuous)
OUT± = GND
through a 50 Ω
resistor.
See Figure 11
12
mA
Output capacitance
OUT+ or OUTto GND when tristate
F = 1 MHz
Vswing
COUT
10
5.5
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |
18/41
pF
STDVE003A
Table 12.
Maximum rating
DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIH
HIGH level input voltage
High level
guaranteed
2.0
VIL
LOW level input voltage
Low level
guaranteed
-0.5
VIK
Clamp diode voltage
VCC = 3.465 V
IIN = -18 mA
-1.2
IIH
Input high current
VCC = 3.465 V
VIN = VCC
-5
+5
µA
IIL
Input low current
VCC = 3.465 V
VIN = GND
-5
+5
µA
CIN
Input capacitance
Pin to GND
F = 1 MHz
Table 13.
Symbol
RTERM
Table 14.
V
0.8
-0.8
V
V
3.5
pF
Value
Unit
Input termination resistor
Parameter
Differential input
termination resistor on
IN± channels relative to
VCC
Test condition
IIN = -10 mA
45
50
55
Ω
External reference resistor
Value
Symbol
Parameter
Test condition
Unit
Min
REXT
Table 15.
Resistor for TMDS
compliant voltage swing
range
Tolerance for
R = ±1%
Typ
Max
4.7
KΩ
DDC I/O pins (switch)
Value
Symbol
Parameter
Test condition
Unit
Min
VI(DDC)
Input voltage
GND
Typ
Max
5.3
V
19/41
Maximum rating
Table 15.
STDVE003A
DDC I/O pins (switch)
Value
Symbol
Parameter
Test condition
Unit
Min
II(leak)
CI/O
20/41
Typ
Max
VCC = 3.465 V
A, B, C ports = 5.3 V
Y port = 0.0 V
Switch is isolated
6
µA
VCC = 3.465 V
A, B, C ports = 3.3 V
Y port = 0.0 V
Switch is isolated
2
µA
Input leakage current
VI=0 V
F = 1 MHz
Switch disabled
5
pF
VI=0 V
F = 1 MHz
Switch enabled
9
pF
Input/output capacitance
STDVE003A
Table 16.
Maximum rating
Status pins (Y_HPD)
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIH
High level input voltage
VCC = 3.3 V
High level guaranteed
2.0
5.3
V
VIL
Low level input voltage
VCC = 3.3 V
Low level guaranteed
GND
0.8
V
VCC = 3.465 V
Y = 5.3 V
4
µA
VCC = 3.465 V
Y = 3.3 V
2
µA
II(leak)
Table 17.
Input leakage current
Status pins (A_HPD, B_HPD, C_HPD)(1)
Value
Symbol
Parameter
Test condition
Unit
Min
V
CI/O
VOL
Voltage
Typ
GND
Max
5.3
V
VI = 0 V
F = 1 MHz
Switch disabled
5
pF
VI = 0 V
F = 1 MHz
Switch enabled
9
pF
Input/output capacitance
Output low voltage
(open drain I/Os)
VCC = 3.3 V
IOL = 8 mA
0.4
V
1. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
21/41
Maximum rating
STDVE003A
DC electrical characteristics (I2C repeater)
4.3
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%, GND = 0 V; unless otherwise specified)
Table 18.
Supplies
Value
Symbol
VCC
Table 19.
Parameter
Test condition
DC supply voltage
Unit
Min
Typ
Max
3.135
3.3
3.465
V
Input/output SDA, SCL
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIH
High level input
voltage
0.7 VCC
5.3
V
VIL
Low level input
voltage(1)
-0.5
0.3 VCC
V
VILc
Low level input voltage
contention(1)
-0.5
0.4
V
VIK
Input clamp voltage
II = -18 mA
−
−
-1.2
V
IIL
Input current low
(SDA, SCL)
Input current low
(SDA, SCL)
−
−
1
μA
VI = 3.465 V
(SDA, SCL)
−
−
10
μA
IIH
Input current high
(SDA, SCL)
VI = 5.3 V
(SDA, SCL)
−
−
10
μA
IOL = 3 mA
0.4
V
IOL = 6 mA
0.65
V
VOL
IOH
CI
LOW-level output
voltage
Output high level
leakage current
Input capacitance
VO = 3.6 V;
driver disabled
−
−
10
μA
VO = 5.3 V;
driver disabled
−
−
10
μA
VI = 3 V or 0 V
−
6
7(2)
pF
1. VIL specification is for the first low level seen by the SDA/SCL lines. VILc is for the second and subsequent low levels seen
by the SDA/SCL lines.
2. The SCL/SDA CI is about 200 pF when VCC = 0 V. The STDVE003A should be used in applications where power is
secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
22/41
STDVE003A
Maximum rating
Dynamic switching characteristics(b)
4.4
TA = -40 to +85 °C, VCC = 3.3 V ± 5%, RTERM = 50 Ω ± 5%, CL = 5 pF).
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 20.
Clock and data rate
Value
Symbol
Parameter
Test condition
Unit
Min
fCK
Drate
Table 21.
Clock frequency
(1/10th of the
differential data rate)
Typ
25
Signaling rate
Max
340
MHz
3.4
Gbps
Equalizer gain
Value
Symbol
Parameter
Test condition
Unit
Min
G_EQ
Table 22.
Typ
Max
At all frequencies
(EQ_BOOST = L) for short
cables
15
dB
At all frequencies
(EQ_BOOST = H) for long
cables
20
dB
Equalizer gain
Differential output timings
Value
Symbol
tr
tf
b.
Parameter
Differential data and
clock output rise/fall
times
tPLH
Differential low to high
propagation delay
tPHL
Differential high to low
propagation delay
Test condition
Unit
Min
Typ
Max
20% to 80% of VOD
75
150
240
ps
80% to 20% of VOD
75
150
240
ps
Alternating 1 and 0 pattern
at slow and fast data rates
Measure at 50% VOD
between input to output
250
800
ps
250
800
ps
The timing values in this section are tested during characterization and are guaranteed by
design and simulation. Not tested in production.
23/41
Maximum rating
Table 23.
STDVE003A
Skew times
Value
Symbol
Parameter
Test condition
Unit
Min
tSK(O)
Inter-pair channel-tochannel output skew
tSK(P)
Pulse skew
tSK(D)
Intra-pair differential
skew
tSK(CC)
Table 24.
Output channel to
channel skew
| tPLH - tPHL |
Typ
25
Difference in
propagation
delay
(tPLH or tPHL)
among all output
channels
50
Max
100
ps
80
ps
44
ps
125
ps
Turn-on and turn-off times
Value
Symbol
Parameter
Test condition
Unit
Min
tON
tOFF
Table 25.
Typ
Max
TMDS output enable
time
Time from
OE_N to OUT±
change from tristate to active
12
20
ns
TMDS output disable
time
Time from
OE_N to OUT±
change from
active to tristate
6
10
ns
DDC I/O pins
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Refer to Section 4.5
Table 26.
Status pins (Y_HPD, A_HPD, B_HPD, C_HPD, SEL)
Value
Symbol
Parameter
Test condition
Unit
Min
tPD(HPD)
Propagation delay
(from Y_HPD to the
active port of HPD)
TON/OFF
Switch time
(from port select to the
CL = 10 pF
latest valid status of
HPD)
24/41
CL = 10 pF,
RPU = 1 KΩ
Typ
Max
150
ns
50
ns
STDVE003A
Table 27.
Maximum rating
Jitter
Value
Symbol
Parameter
Test condition
Unit
Min
tJIT
Total jitter(1)
PRBS pattern
at 1.6 Gbps
(800 MHz)
Typ
35
Max
ps (p-p)
1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been
subtracted. Input differential voltage = VID = 500 mV, PRBS random pattern at 1.65 Gbps, tr=tf=50 ps (20% to 80%). Jitter
parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
25/41
Maximum rating
4.5
STDVE003A
Dynamic switching characteristics (I2C repeater)
TA = -40 to +85 °C, VCC = 3.3 V ± 5%.
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 28.
.
I2C repeater(1)
Value
Symbol
Parameter
Test condition
Unit
Min
fSCL
tLOW
tLOW
26/41
I2C clock frequency
Low duration on SCL pin
Typ
Max
Standard mode
100
kHz
Fast mode
400
kHz
100 KHz
See Figure 19
Voltage on line = 5V
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
4.7
μs
400 KHz
See Figure 19
Voltage on line = 5V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
1.3
μs
100 KHz
See Figure 19
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
4.7
μs
400 KHz
See Figure 19
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
1.3
μs
Low duration on SCL pin
STDVE003A
Table 28.
Maximum rating
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min
tHIGH
tHIGH
tPHL
tPLH
tPHL
Typ
Max
100 KHz
See Figure 19
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
4.0
μs
400 KHz
See Figure 19
Voltage on line = 5 V
Cmax = 400 pF, Rmax=2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
0.6
μs
100 KHz
Refer section 14.12,
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
4.0
μs
400 KHz
See Figure 19
Voltage on line = 3.3 V,
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
0.6
μs
High duration on SCL pin
High duration on SCL pin
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
250
μs
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
300
μs
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
250
ns
27/41
Maximum rating
Table 28.
STDVE003A
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min
tPLH
tPHL
tPLH
tPHL
tPLH
tf
tf
28/41
Typ
Max
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
450
ns
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
250
ns
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
300
ns
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
250
ns
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
450
ns
400 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
300
ns
400 KHz
Waveform 1(2)
Voltage on line = 3.3 V
Cmax = 400pF, Rmax = 2 K
300
ns
100 KHz
Waveform 1 (Figure 17) (2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
300
ns
100 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
300
ns
Output fall time
Output fall time
STDVE003A
Table 28.
Maximum rating
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min
tr
tr
Typ
Max
400 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
300
ns
400 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
300
ns
100 KHz
Waveform 1,(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
1000
ns
100 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
1000
ns
Output rise time
Output rise time
1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in
production.
2. The tr transition time is specified with maximum load of 2 kΩ pull-up resistance and 400 pF load capacitance. Different load
resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Refer to Figure 9.
Table 29.
ESD performance
Symbol
ESD
Parameter
All I/Os
Test conditions
Contact discharge
as per IEC61000-4-2 standard
Min
Typ
8
Max
Unit
kV
29/41
Maximum rating
Figure 7.
STDVE003A
Test circuit for electrical characteristics
VCC
CL
VOUT+
VIN+
Pulse
generator
VINRT
STDVE003A
VOUT-
100 Ω
RT
CL
CS00065
1. CL = load capacitance: include jig and probe capacitance.
2. RT = termination resistance; should be equal to ZOUT of the pulse generator.
Figure 8.
TMDS output driver
VCC
RT
RT
ZO = RT
TMDS
driver
ZO = RT
TMDS
receiver
CS00069
1. ZO = characteristic impedance of the cable.
2. RT = termination resistance: should be equal to ZO of the cable. Both are equal to 50W.
30/41
STDVE003A
Maximum rating
Figure 9.
Test circuit for HDMI receiver and driver
VCC
RT
RT
A
VA
RT
Y
VID
TMDS
receiver
TMDS
driver
CL =
0.5pF
VCC
VY
B
Z
VB
VID = VA - VB
VSwing = VY - VZ
VZ
RT
CS00071
1. RT = 50 Ω.
31/41
Maximum rating
STDVE003A
Figure 10. Test circuit for turn off and turn off times
10µF
0.1 µF 0.01µF
CL
1.15 V
VCC
VIN+
1.0 V
50 Ω
1.2 V
50 Ω
STDVE003A
1.15 V
VIN1.0 V
SHDN_N
CL
REXT
Pulse
generator
GND
4.7 KΩ±1%
50 Ω
CS00072
1. CL = 5 pF
Figure 11. Test circuit for short circuit output current
50 Ω
ISC
TMDS
driver
50 Ω
0V or 3.465 V
32/41
STDVE003A
Maximum rating
Figure 12. Propagation delays
VCC
VA
VCM
VID
VCM
VB
VCC – 0.4
0.4V
VID
VID
VID(p-p)
0V
-0.4V
VOD(O)
tpLH
tpHL
100%
80%
VOD(p-p)
80%
0V Differential
20%
20%
Output
0%
VOD(U)
tr
tf
Figure 13. Turn-on and turn-off times
SHDN_N
3.0 V
1.50 V
1.50 V
0V
tOFF
tON
VOH
VOUT+ when VID= +150mV
VOUT- when VID= -150mV
50%
50%
1.2 V
tON
tOFF
1.2 V
VOUT+ when VID= -150mV
VOUT- when VID= +150mV
50%
50%
VOL
33/41
Maximum rating
STDVE003A
Figure 14. TSK(O)
3.5V
2.5V
Data In
1.5V
tpLHX
tpHLX
VOH
2.5V
2.5V
Data Out at Port 0
VOL
tSK(o)
VOH
2.5V
Data Out at Port 1
VOL
tpLHY
tpHLY
tSK(o) = | tpLHy – tpLHx | or | tpHLy – tpHLx |
Figure 15. TSK(P)
Figure 16. TSK(D)
34/41
STDVE003A
Maximum rating
Figure 17. AC waveform 1 (I2C lines)
Figure 18. Test circuit for AC measurements (I2C lines)
Figure 19. I2C bus timing
35/41
Application information
5
Application information
5.1
Power supply sequencing
STDVE003A
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to
always apply VCC before applying any signals to the input/output or control pins.
5.2
Power supply requirements
Bypass each of the VCC pins with 0.1 μF and 1 nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as
possible.
All VCC pins can be tied to a single 3.3 V power source. A 0.01 μF capacitor is connected
from each VCC pin directly to ground to filter supply noise. The maximum power supply
variation can only be ±5% as per the HDMI specifications.
The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
5.3
Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several
considerations to minimize discontinuities on these transmission lines between the
connectors and the device.
(a) Maintain 100-Ω differential transmission line impedance into and out of the STDVE003A.
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
(d) Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STDVE003A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
36/41
STDVE003A
5.3.1
Application information
I2C lines application information
A typical application is shown in the figure below. In the example, the system master is
running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at
100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz.
Master devices can be placed on either bus.
Figure 20. Typical application of I2C bus system
The STDVE003A DDC lines are 5 V tolerant; so it does not require any extra circuitry to
translate between the different bus voltages.
37/41
Package mechanical data
6
STDVE003A
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 21. TQFP80 package outline
38/41
STDVE003A
Package mechanical data
Table 30.
TQFP-80 mechanical data
Millimeters
Symbol
Min
Typ
A
Max
1.200
A1
0.050
0.150
A2
0.950
1.000
1.050
b
0.170
0.220
0.270
c
0.090
0.200
D
14.000
D1
12.000
D2
9.500
e
0.500
E
14.000
E1
12.000
E2
9.500
L
0.450
L1
k
0.600
0.750
1.000
0°
ccc
7°
0.080
Figure 22. TQFP80 tape and reel information
39/41
Revision history
7
STDVE003A
Revision history
Table 31.
Document revision history
Date
Revision
23-Apr-2008
1
Initial release.
26-May-2008
2
Minor updates: Table 4,Table 7, Table 23 and Table 29.
3
Added: Fully automatic adaptive equalizer feature
Modified: title, features Chapter 3.1 and Figure 2
Removed: Table 21.: Equalizer gain
21-Jul-2008
40/41
Changes
STDVE003A
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41/41