GENLINX ™II GX9533 Serial Digital 8x9 Crosspoint DATA SHEET DESCRIPTION • operation beyond 622Mb/s The GX9533 is a high speed 8x9 serial digital crosspoint. An expansion input port eases the design of larger switching matrices by reducing PCB layers and eliminating the need for cascaded secondary switching. Decode logic and double level latching to configure the matrix are included on chip. Separate LOAD and CONFIGURE inputs allow for asynchronous configuration and synchronous switching. These latches can also be made transparent for asynchronous switching by pulling the LOAD and CONFIGURE pins high. • accepts SMPTE and PECL input levels • fully differential signal path • on-chip PECL current loads eliminate need for external pull-down resistors • capable of driving 100Ω differential loads • very low 500mW power consumption • additional expansion port input for construction of larger matrices • auxiliary monitoring output • easy to configure • double latched address inputs with separate load and configure • TTL/CMOS compatible control logic inputs • single 5V power supply APPLICATIONS Serial digital switching. video switching; datacom or telecom In the power saving (PS) mode, the GX9533 has a very low power consumption of 500mW. This is accomplished by driving a 400mV output swing into the on-chip 200Ω differential load termination in the expansion port of the next GX9533. This architecture provides a significant power savings and the elimination of external load resistors or impedance matching resistors. In applications where standard PECL levels are necessary, the GX9533 can be configured in "PECL Mode", to drive 800mV p-p into a 100Ω differential load. The power consumption in this mode increases to 860mW. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE GX9533-CQY 100 pin MQFP Tray 0°C to 70°C GX9533-CTY 100 pin MQFP Tape 0°C to 70°C STD/PECL2 STD/PECL1 2 2 VCCO AUX IN 16 EXP0..7 INPUT BUFFER 16 SWITCHING MATRIX 16 OUTPUT BUFFER OUT 0..7 16 AUX 2 IN0 .. 7 CONFIG CONFIG LATCH LOAD LOAD LATCH LOAD A VEE 3 OA0..2 IA0..3 4 DECODE LOGIC VCC BLOCK DIAGRAM Revision Date: August 1999 Document No. 521 - 41 - 03 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com GX9533 FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage (VS = VCC-VEE) 5.5V Input Voltage Range (any input) -0.3 to (VCC+0.3)V GX9533 Power Dissipation 975mW Operating Temperature Range 0°C to 70°C Storage Temperature Range -65°C to +150°C Lead Temperature Range (soldering, 10 sec) 260°C DC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0 to 70°C unless otherwise shown. PARAMETER CONDITION MIN TYP MAX UNITS Supply Voltage 4.75 5.0 5.25 V ECL Input Voltage Swing 200 800 1200 mV p-p 2500 - VCC-600 mV High 2.0 - VCC V Low 0 - 0.8 V MIN TYP MAX UNITS - 115 150 mA VCC-1200 - VCC-800 mV 300 450 600 mV High VCC-950 - VCC-600 mV Low VCC-1400 - VCC-1000 mV MIN TYP MAX UNITS - 100 130 mA VCC-1200 - VCC-800 mV 300 450 600 mV High VCC-950 - VCC-600 mV Low VCC-1400 - VCC-1000 mV ECL Common Mode Input Voltage Range Logic Input Voltage with 1200mV input signal swing POWER SAVE 1 MODE RSET = 4kΩ PARAMETER CONDITION Supply Current RL = 100Ω Output Common Mode Voltage Output Voltage Swing Output Voltage POWER SAVE 2 MODE RSET = 6kΩ PARAMETER CONDITION Supply Current RL = 200Ω Output Common Mode Voltage Output Voltage Swing Output Voltage 2 521 - 41 - 03 PECL MODE RSET = 2kΩ PARAMETER CONDITION TYP MAX UNITS - 170 185 mA VCC-1450 - VCC-1050 mV 700 800 900 mV High VCC-1200 - VCC-650 mV Low VCC-1850 - VCC-1450 mV Supply Current RL = 100Ω Output Common Mode Voltage Output Voltage Swing Output Voltage AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 0 to 70°C unless otherwise shown. PARAMETER SYMBOL MIN TYP MAX UNITS For 90% eye opening - 850 - Mb/s 143 to 622 Mb/s, all hostile crosstalk - 80 - ps p-p - 70 - ps p-p - 1.7 - ns Expansion Input - 1.1 - ns Standard Input - 350 - ps Expansion Input - 250 - ps - 10 - ns - 11 - ns Maximum Input Data Rate Additive Jitter Standard Input CONDITION Expansion Input Data In to Data Out Delay Propagation Delay Match CONFIGURE to Data Out Delay Standard Input Main Out tDLY Average of all channels tCD AUX Out LOAD/LOADA Pulse Width tLP 20 - - ns CONFIGURE Pulse Width tCP 20 - - ns IAN to LOAD/LOADA High Setup Time tILS 30 - - ns LOAD/LOADA to IAN Low Hold Time tILH 0 - - ns OAN to LOAD High Setup Time tOLS 30 - - ns LOAD to OAN Low Hold Time tOLH 0 - - ns LOAD High to CONFIGURE High tLC 0 - - ns - 700 - ps Output Rise/Fall Time NOTE 1. Use RMS addition to calculate additive jitter through cascaded devices. 3 521 - 41 - 03 GX9533 MIN STD/PECL2 AUX_IN AUX_IN EXP7 EXP7 EXP6 EXP6 EXP5 EXP5 EXP4 VCC EXP4 EXP3 EXP3 EXP2 EXP2 EXP1 EXP1 EXP0 EXP0 PIN CONNECTIONS STD/PECL1 GX9533 VCC IN0 NC IN0 NC VEE LOAD IN1 NC IN1 NC VEE LOADA IN2 NC IN2 NC VEE CNFG IN3 NC NC IN3 VEE IA0 GX9533 IN4 NC TOP VIEW IN4 NC VEE IA1 IN5 NC IN5 NC VEE IA2 IN6 NC IN6 NC VEE IA3 IN7 NC IN7 NC VEE OA0 VEE OA1 VCC OA2 VEE VEE OUT7 OUT7 VCCO OUT6 OUT6 VCCO OUT5 OUT5 VCCO OUT4 OUT4 VCCO OUT3 OUT3 VCCO OUT2 OUT2 VCCO AUX_OUT OUT1 AUX_OUT OUT0 OUT1 OUT0 PIN DESCRIPTIONS SYMBOL TYPE IN0 to IN7, IN0 to IN7 I Differential data inputs. OUT0 to OUT7, OUT0 to OUT7 O Differential data outputs. AUX_OUT, AUX_OUT O Auxiliary port output. AUX_IN, AUX_IN I Auxiliary port input. OA0 to OA2 I Output address select. IA0 to IA3 I Input address select. LOAD I Loads input & output address. LOADA I Loads auxiliary input address. STD/ECL1, STD/ECL2 DESCRIPTION Resistor connection for Power Save mode or PECL mode. Refer to Table 3. 4 521 - 41 - 03 PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CNFG I Switch configuration. EXP0 to EXP7, EXP0 to EXP7 I Expansion port inputs. Positive power supply. VCCO Positive power supply (PECL outputs). GX9533 VCC Negative power supply. VEE 8 Auxillia Inputry 0 IN PU T BU FF ER S Expan 7 s Inputsion 6 5 4 3 2 1 0 1 4 5 0 4 5 4x1 6Switch 7 6 7 0 1 1 2 6 7 3 3x Sw 1 itch 3x1 Switch 4 5 4x Sw 1 itch Standa Inputsrd 3 4x Sw 1 itch 0 1 4x1 2 Switch 3 2 Auxillia Outpury t 7 6 5 4 3 Main 2 Outputs Fig. 1 Data Flow Diagram 100 % OPENING 90 80 70 60 50 700 800 900 1000 1100 BIT RATE (Mb/s) Fig. 2 Typical Eye Opening vs. Bit Rate 5 521 - 41 - 03 DETAILED DESCRIPTION TABLE 1: Output Address Selection DIFFERENTIAL INPUTS GX9533 The inputs to the GX9533 will accept both SMPTE 259M as well as PECL input levels. The fully differential data path provides low jitter data rates of up to 700Mb/s. OA2 0A1 0A0 OUTPUT PORT 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 The main inputs (IN0..7) and expansion inputs (EXP0..7) are normally connected to a biased differential data source. The GX9533 inputs are not self biased, so unused inputs should be connected as shown in Figure 3 or Figure 4. VCC INx GX9533 INx 1k TABLE 2: Input Source Address Selection IA3 IA2 IA1 IA0 INPUT PORT 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 Fig. 4 Alternate Termination of Unused Inputs 0 1 0 0 4 Terminating the inputs as shown in Figure 3 will provide the highest noise immunity, since there is no possibility of noise coupling into the unconnected input pin. 0 1 0 1 5 0 1 1 0 6 Fig. 3 Preferred Termination Of Unused Inputs VCC INX GX9533 NC INX 0 1 1 1 7 I/O ADDRESS SELECTION 1 0 X X EXP The GX9533 has a versatile LOAD/CONFIGURE architecture which simplifies IN/OUT switch configuration. 1 1 X X Quiet Mode An output is normally connected to an input by a two stage process: Note that a QUIET mode is available as shown in Table 2. In QUIET mode, the outputs are latched in a DC state with OUTX = 1 and OUTX = 0. Stage One: Loading The Configuration Into Latches 1. The output address is selected on the OA pins as shown in Table 1. Stage Two: Configuring The Matrix A CONFIGURE strobe is applied to transfer the contents of the LOAD latch into the CONFIG latch. This action will cause the data flow through the GX9533 to be switched to the new configuration. Refer to Figure 6 for detailed timing information. 2. The input address is selected on the IA pins as shown in Table 2. 3. A LOAD pulse then transfers the output and input addresses into the GX9533 LOAD latch. The above three steps can be repeated up to eight times in order to configure the latch for all eight outputs. Note that any single output can be asynchronously switched by having LOAD (or LOADA if desired) held high while CONFIG is strobed. During step 3 above, if the LOADA pulse is also strobed, the latch is configured to connect the selected input to the ninth, auxiliary output. 6 521 - 41 - 03 OUTPUT LEVEL SELECT USING THE GX9533 TO EXPAND LARGER MATRICES A single resistor, RSET, is used to set the amplitude of all differential outputs. Table 3 shows the value of RSET vs output drive capability. The GX9533 pin-out and architecture provides a number of advantages over other crosspoint switches in the area of switching matrix board layout. VOUT (mV) OUTPUT RL MODE 2k 800 100 PECL 4k 450 100 Power Save 1 6k 450 200 Power Save 2 INPUTS 0-7 to IN7 to IN7 tDLY OUT0 to OUT7 GX9533 GX9533 IN0 IN0 RSET INPUTS 8-15 TABLE 3: RSET vs VOUT GX9533 GX9533 GX9533 OUTPUTS 0-7 OUTPUTS 8-15 OUT0 to OUT7 Fig. 5 GX9533 Data Latency Fig. 9 Crosspoint Matrix Expansion - 16x16 Crosspoint Matrix OAN, IAN tLP BUS THROUGH™ PIN CONNECTIONS To easily facilitate a switching matrix design where inputs can be bussed across a matrix of crosspoint devices, Gennum's crosspoint device has "NC" pins opposite the input pins as shown by the dotted lines in the pin-out diagram above. This design allows bussing of inputs without having to use "vias" to get below the top layer of the printed circuit board. LOAD/LOADA tILS tILH tOLS tOCH tCP CONFIGURE tLC EXPANSION PORT INPUT Fig. 6 LOAD/LOADA and Configure Timing The expansion inputs provide the following benefits: • by not having to run traces from the outputs of the crosspoint switch to a common output bus, crosstalk between output channels can be greatly reduced. • fewer circuit board layers are required because the outputs of each device simply line up • there are no transmission line effects caused by connecting High-Z outputs to an output bus • because the output signal is being routed from the top of the switching matrix to the bottom through the devices, inputs can be simply bussed across the board without having to worry about input/output crosstalk. CONFIGURE tCD OUT 0 TO OUT 7 OUT 0 TO OUT 7 Fig. 7 Configure to Data Out Delay RSET STD/ECL2 STD/ECL1 GX9533 Fig. 8 GX9533 RSET Connection 7 521 - 41 - 03 PACKAGE DIMENSIONS 23.90 ±0.25 20.0 ±0.10 GX9533 18.85 REF 12˚ TYP 17.90 12.35 REF 14.0 ±0.10 ±0.25 0.75 MIN 0˚-7˚ 0.30 MAX RADIUS 0˚- 7˚ 0.13 MIN. RADIUS 0.80 ±0.10 1.95 REF 3.30 MAX 100 pin MQFP Dimensions in millimeters 0.65 BSC 0.30 ±0.08 2.80 ±0.25 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION REVISION NOTES: DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. Changes to document format. GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright April 1995 Gennum Corporation. All rights reserved. Printed in Canada. 521 - 41 - 03 8