STMICROELECTRONICS STULPI01BTBR

STULPI01A
STULPI01B
High speed USB On-The-Go ULPI transceiver
Features
■
USB-IF high speed certified to the Universal
Serial Bus specification Rev 2.0.
■
Meets the requirements of the Universal Serial
Bus specification revision 2.0, On-The-Go
supplement to the USB 2.0 specification 1.0a
and ULPI transceiver specification 1.1.
■
Standard ULPI (UTMI+ low pin interface) 1.1
digital interface.
■
Fully compliant with ULPI 1.1 register set.
■
External square wave clock with 1V8VIO
amplitude must be applied to oscillator input XI.
■
Supports 480 Mbit/s high speed, 12 Mbit/s fullspeed and 1.5 Mbit/s low speed modes of
operation.
■
Supports 2.7 V UART mode.
■
Supports session request protocol (SRP) and
host negotiation protocol (HNP) for dual-role
device features.
µTFBGA36
Applications
■
Mobile phones
■
PDAs
■
MP3 players
■
Digital still cameras
■
Set top box
Portable navigation devices
■
Ability to control external charge pump for
higher VBUS currents.
■
■
Single supply, +3 V to +4.5 V voltage range.
Description
■
Integrated dual voltage regulator to supply
internal circuits with stable 3.3 V and 1.2 V.
■
Integrated over current detector.
■
Integrated HS termination and FS/LS/OTG
pull-up/pull-down resistors.
■
Integrated USB 2.0 “short-circuit withstand”
protection.
■
Power down mode with very low power
consumption for battery-powered devices.
■
Ideal for system ASICs with built-in USB host,
device or OTG cores.
■
Available in µTFBGA36 RoHS package.
■
-40 °C to 85 °C operating temperature range.
June 2008
The STULPI01 is a high speed USB 2.0
transceiver compliant with ULPI (UTMI+ low pin
interface) and OTG (On-The-Go) specifications,
providing a complete physical layer solution for
any high speed USB host, device or OTG dual
role core. It allows USB ASICs to interface with
the physical layer of the USB through a 12-pin
interface. It contains VBUS comparators, ID line
detector, USB differential driver and receivers and
complete ULPI register map and interrupt
generator. The STULPI01 transceiver is suitable
for mobile applications and battery powered
devices because of its low power consumption,
power down operating mode and minimal
die/package dimensions.
Rev 1
1/44
www.st.com
44
Contents
STULPI01A - STULPI01B
Contents
1
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3
Power-on-reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
UTMI + CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5
ULPI wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6
External charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7
VBUS comparators and VBUS over current (OC) detector . . . . . . . . . . . 19
6.8
VB_REF_FAULT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.9
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.10
ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.11
USB 2.0 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.12
Power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13.1
ULPI synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13.2
6 pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13.3
3 pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.14
Car kit (UART) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.15
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.16
Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.17
VIO OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18
Start-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18.1
2/44
ULPI device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STULPI01A - STULPI01B
Contents
6.18.2
SDR mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18.3
External clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.4
Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.5
Interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.6
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.7
High speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
State transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
ULPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10
Order codes
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3/44
List of tables
STULPI01A - STULPI01B
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
4/44
Bill of materials - external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pinout and bump description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VB_REF_FAULT configuration bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Car kit signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
USB state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ULPI register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register access legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Vendor and product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power control registe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
OTG control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
USB interrupt enable rising register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
USB interrupt enable falling register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USB interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USB interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Setting rules for interrupt latch register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Scratch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Carkit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STULPI01A - STULPI01B
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Peripheral only. Configuration with external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VB_REF_FAULT pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USB 2.0 PHY block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RESETn behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High speed mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UART mode entry (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UART mode exit (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5/44
Application diagrams
STULPI01A - STULPI01B
1
Application diagrams
Figure 1.
Peripheral only. Configuration with external clock
Table 1.
Bill of materials - external components
Q.ty
1
2
6/44
Symbol
CF1
CF4
Value
Description
0.1 - 1 µF
Filtering capacitor. Suggested components:
muRata 10 V X5R (GRM188R61A105KA61) or
muRata 10 V Y5V (GRM188F51A105ZA01) or
Taiyo Yuden 25V X5R (TMK107BJ105KA)
0.1 - 1 µF
Filtering capacitor. Suggested components:
muRata 10 V X5R (GRM188R61A105KA61) or
muRata 10 V Y5V (GRM188F51A105ZA01) or
Taiyo Yuden 25V X5R (TMK107BJ105KA)
1
CF2
1µF - 1.5 µF
Filtering capacitor. Suggested components:
muRata 10 V X5R (GRM188R61A105KA61) or
muRata 10 V Y5V (GRM188F51A105ZA01) or
Taiyo Yuden 25V X5R (TMK107BJ105KA)
1
CF3
1 - 4.7 µF
Filtering capacitor. Suggested components:
muRata 10 V Y5V (GRM188F51A475ZE20) or
Taiyo Yuden 6.3 V X5R (JMK107BJ475KA)
1
CT
4.7 µF
Tank capacitor
1
RREF
12 kΩ
Reference resistor ±1%
1
E1
USBULC6-2F3
1
E2
ESDA14V2-2BF3
1
RBUS
2.2 kΩ
Series over-voltage protection resistor
STULPI01A - STULPI01B
Bump configuration
2
Bump configuration
Figure 2.
Pin connections
1
2
3
4
5
6
F
NC
NC
A
E
GND
VB_REF
_FAULT
3V3V
B
D
DP
GND
ID
C
C
DM
RREF
D
B
D0
1V8
VIO
1V8
VIO
E
A
D1
D2
D3
1
2
F
µTFBGA36 (through top side view)
Table 2.
VBAT VBUS
XI
XO
GND
DIR
1V2V
PSWn
NXT
STP
GND
D7
GND
1V8
VIO
D6
CLK
D4
D5
4
5
6
CSn/
RESETn
PWRDN
3
µTFBGA36 (bottom view)
Pinout and bump description
Bump
Symbol
Type
Description
B1
D0
I/O
Data bit[0] (1V8VIO referred). UART TXD signal.
A1
D1
I/O
Data bit[1] (1V8VIO referred). UART RXD signal.
A2
D2
I/O
Data bit[2] (1V8VIO referred). UART reserved pin.
A3
D3
I/O
Data bit[3] (1V8VIO referred). UART active high interrupt indication.
A4
CLK
O
Clock out (1V8VIO referred).
A5
D4
I/O
Data bit[4] (1V8VIO referred).
A6
D5
I/O
Data bit[5] (1V8VIO referred).
B6
D6
I/O
Data bit[6] (1V8VIO referred).
C6
D7
I/O
Data bit[7] (1V8VIO referred).
D6
STP
I
ULPI stop signal (1V8VIO referred).
D5
NXT
O
ULPI next signal (1V8VIO referred).
E5
DIR
O
ULPI direction signal (1V8VIO referred).
C3
CSn/PWRDN
I
Chipselect active low, power down active high.
C4
RESETn
I
Active low asynchronous reset.
D1
DP
I/O
Positive data line of the USB. 5V tolerant.
C1
DM
I/O
Negative data line of the USB. 5V tolerant.
D3
ID
I
ID pin of the USB connector for initial device role selection. 5V tolerant.
F4
VBUS
I/O
VBUS line of the USB interface, requires an external capacitor of 4.7µF.
F1
NC
Not connected.
7/44
Bump configuration
Table 2.
STULPI01A - STULPI01B
Pinout and bump description (continued)
Bump
Symbol
F2
NC
E2
VB_REF_FAULT
I
Voltage reference for internal OC detector input or digital input from
external OC detector (V3V3V referred). 5V tolerant.
D4
PSWn
O
External charge pump control, active low. 5V tolerant, open drain.
F5
XI
I
External clock input (1V8VIO referred). Crystal terminal (on request).
F6
XO
O
Left floating or connect to GND when external clock signal is used.
Crystal terminal on request.
F3
VBAT
PWR
E3
3V3V
PWR 3.3V LDO output. Bypass 3V3V to GND with a 1.5µF capacitor.
E6
1V2V
PWR 1.2V LDO output. Bypass 1V2V to GND with a 1.5µF capacitor.
C2
RREF
I/O
B2/B3/B5
1V8VIO
PWR
C5/D2
GND
PWR Ground.
B4/E4/E1
GND
PWR Ground.
8/44
Type
Description
Not connected.
Battery power input for the LDO (3 V – 4.5 V). Bypass VBAT to GND with
a 1µF capacitor.
Reference resistor (12kΩ ±1%).
Digital I/O supply voltage 1.8V. Bypass each 1V8VIO to GND with a
100nF-1uF capacitor. Balls B2-B5 can share common capacitor.
STULPI01A - STULPI01B
Maximum ratings
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Value
Unit
Digital I/O supply voltage
-0.3 to +2.0
V
V1V2
Digital core supply voltage (provided internally by LDO)
-0.3 to +1.4
V
V3V3
Analog supply voltage (provided internally by LDO)
-0.3 to +4.0
V
VBAT
Battery supply voltage
-0.3 to +7.0
V
VDCDIG
DC voltage on digital pins (CLK, DIR, STP, NXT, D[0-7], RESETn)
-0.3 to +2.0
V
VDCANA
DC voltage on analog pins (XI, XO, PSWn)
-0.3 to +4.0
V
VDCVBUS
DC voltage on 5V tolerant pins (VBUS,VB_REF_FAULT, DP, DM, ID)
-0.3 to +5.5
V
Storage temperature range
-40 to +125
°C
±2.0
kV
V1V8VIO
TSTG
VESD-HBM
Parameter
Electrostatic discharge voltage on all pins (according to JESD22A114-B)
Note:
Absolute maximum ratings are those values above which damage to the device may occur.
Functional operation under these conditions is not implied. All voltages are referenced to
GND.
Table 4.
Thermal data
Symbol
Parameter
Value
Unit
113.8
°C/W
RthJA
Thermal resistance junction-ambient (simulated value as per JEDEC JSD51)
RthJC
Thermal resistance junction-case (simulated value as per JEDEC JSD51)
47
°C/W
RthJB
Thermal resistance junction-base (simulated value as per JEDEC JSD51)
66.2
°C/W
Table 5.
Recommended operating conditions
Symbol
VBAT
Parameter
Battery supply voltage
V1V8VIO Digital I/O supply voltage
TA
Operating temperature range
CT
Tank capacitor
RREF
External reference resistor
External square wave (01A, 01B versions)
Min.
Typ.
Max.
Unit
3.0
3.6
4.5
V
1.65
1.80
1.95
V
+85
°C
-40
1
4.7
6.5
µF
11.88
12
12.12
kΩ
19.2 or 26
MHz
4
ns
XTAL
Recommended rise/fall time
9/44
Electrical characteristics
STULPI01A - STULPI01B
4
Electrical characteristics
Table 6.
Electrical characteristics
(Characteristics measured over recommended operating conditions unless otherwise noted.
All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V,
RREF = 12 kΩ; CT = 4.7 µF)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Power consumption
Active mode (USB bus idle)
IBAT
I1V8VIO
Supply current
ULPI bus supply current
1V8VIO
15
mA
Active mode (FS
transmission, 12Mb/s
traffic)
30
mA
Active mode (HS
transmission)
50
mA
Suspend mode (not
including DP pull-up
current, external clock
stopped)
120
µA
UART mode (no
transmission)
15
mA
Power down mode
0.4
2
µA
VIO OFF mode
(1V8VIO=0)
0.4
2
µA
Power down mode
0.1
10
µA
Active mode, 4pF load
1.8
mA
Logic inputs and outputs
CULPIIN
2.4
ULPI port I/O capacitance
3.5
pF
VOH
High level output voltage
(ULPI bus)
IOH = -2 mA
VOL
Low level output voltage
(ULPI bus)
IOL = +2 mA
0.15
V
IOZH_PSWn
High level output leakage
(PSWn)
VOH_PSWn = 3.3V power
switch disabled
1.0
µA
VOL_PSWn
Low level output voltage
(PSWn)
IOL = +2 mA power switch
enabled
0.15
V
VIH
High level input voltage
(ULPI port and RESETn)
VIL
Low level input voltage
(ULPI port and RESETn)
IIH
High level input leakage
current
10/44
V1V8VIO-0.15
V
0.65xV1V8VIO
VIH = V1V8VIO-0.2V
V
0.35xV1V8VIO
V
±1.0
µA
STULPI01A - STULPI01B
Table 6.
Electrical characteristics
Electrical characteristics (continued)
(Characteristics measured over recommended operating conditions unless otherwise noted.
All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V,
RREF = 12 kΩ; CT = 4.7 µF)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
±1.0
µA
IIL
Low level input leakage
current
VIL = 0.2V
VPDH
High level input voltage
(CSn/PWRDN pin)
VBAT=3.0V to 4.5V
VPDL
Low level input voltage
(CSn/PWRDN pin)
VBAT=3.0V to 4.5V
0.4
V
IPDH
High level input leakage
current (CSn/PWRDN
pin)
VPD = 1.4V, VBAT = 4.5V
±1.0
µA
IPDL
Low level input leakage
current (CSn/PWRDN
pin)
VPD = 0.4V, VBAT = 4.5V
±1.0
µA
VFAULTH
High level input voltage
(VB_REF_FAULT pin)
Overcurrent_PD bit is set
VFAULTL
Low level input voltage
(VB_REF_FAULT pin)
Overcurrent_PD bit is set
RIN_VB_REF
VB_REF_FAULT pin input
resistance
XO = ‘0’ @ reset
VXIH
High level input voltage
(XI pin)
XO = ‘0’ @ reset
VXIL
Low level input voltage (XI
XO = ‘0’ @ reset
pin)
V
V
0.65xV3V3
112
External clock input
hysteresis
VXI_HYST_EXT
1.4
148
0.15xV3V3
V
168
kΩ
500
mV
V
0.65xV1V8VIO
0.15xV1V8VIO
V
200
mV
100
kΩ
VBUS
VBUS_LKG
VBUS leakage voltage
RVBUS
VBUS input impedance
VBUS_VLD
VBUS valid comparator
threshold
VSESS_VLD
Session valid comparator Low to high transition
threshold for both A and B
High to low transition
device
VSESS_END
Session end comparator
threshold
0.2
RVBUS_PU
VBUS charge pull-up
resistance
650
RVBUS_PD
VBUS discharge pull-down
resistance
800
No load
40
1kΩ series resistors
4.4
4.75
0.8
1.45
V
2.0
1.25
V
V
0.8
V
950
1150
Ω
1250
1500
Ω
11/44
Electrical characteristics
Table 6.
STULPI01A - STULPI01B
Electrical characteristics (continued)
(Characteristics measured over recommended operating conditions unless otherwise noted.
All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V,
RREF = 12 kΩ; CT = 4.7 µF)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
20
45
95
mV
Overcurrent detector
VOC
Over current trip threshold VOC = VB_REF_FAULT –
VB_REF_FAULT – VBUS VBUS
ID
IID_PU
ID pin pull-up current
RID_GND
ID line short resistance to
detect ID GND state
RID_FLOAT
ID line short resistance to
detect ID FLOAT state
VID = 0V
70
µA
1
kΩ
100
kΩ
V1V8VIO-0.15
V
UART mode (2.7 V ± 5 %)
VOH_UART
High level output voltage
(D1,D3)
IOH = -2mA
VOL_UART
Low level output voltage
(D1,D3)
IOL = +2mA
VIH_UART_D0
High level input voltage
(D0)
VIL_UART_D0
Low level input voltage
(D0)
0.15
V
V
0.65xV1V8VIO
0.35xV1V8VIO
V
VOH_DFMS
High level output voltage
(DP)
IOH = -2mA
2.16
2.85
V
VOL_DFMS
Low level output voltage
(DP)
IOL = +2mA, Pull-up=10kΩ
-0.10
0.37
V
VIH_DTMS
High level input voltage
(DM)
2.0
3.0
V
VIL_DTMS
Low level input voltage
(DM)
-0.3
0.81
V
40.5
49.5
Ω
Full-speed/Low-speed driver
ZDRV
Output impedance (acting
also as high-speed
termination)
VOH_DRV
High level output voltage
RLH = 14.25kΩ
2.8
3.6
V
VOL_DRV
Low level output voltage
RLL = 1.425kΩ
0.0
0.3
V
VCRS
Driver crossover voltage
CLOAD=50 to 600pF (1)
1.3
2.0
V
-10
10
mV
380
440
mV
-10
10
mV
1.67
High-speed driver
VHSOI
HS idle level
VHSDPJ
HS data DP J state level
VHSDK
HS data DP K state level
12/44
(1)
STULPI01A - STULPI01B
Table 6.
Electrical characteristics
Electrical characteristics (continued)
(Characteristics measured over recommended operating conditions unless otherwise noted.
All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V,
RREF = 12 kΩ; CT = 4.7 µF)
Symbol
Parameter
VHSDNJ
HS data DN J state level
VHSDNK
HS data DN K state level
VCHIRPJ
Chirp J level (differential
voltage)
VCHIRPK
Chirp K level (differential
voltage
Test conditions
(1)
(1)
Min.
Typ.
Max.
Unit
380
440
mV
-10
10
mV
700
1100
mV
-900
-500
mV
Full-speed/Low-speed receivers
VDI
VSE_TH
Diff. receiver input
sensitivity (VDP-VDM)
SE receivers switching
threshold
VCM = 0.8 to 2.5V
200
Low to high transition
0.8
1.6
2.0
V
High to low transition
0.8
1.1
2.0
V
300
RINP
Input resistance
PU/PD resistors
deactivated
CIN
Input capacitance
(1)
ΔCIN
Difference in capacitance
between DP and DM input
VDT_LKG
Data line leakage voltage
mV
kΩ
RPU_EXT = 300kΩ
5
pF
10
%
342
mV
High-speed receiver
VHSSQ
HS squelch detector
threshold
100
150
mV
VHSDSC
HS disconnect detection
threshold
525
625
mV
VHSCM
HS data signaling
(1)
common mode volt. range
-50
500
mV
VHSTERM
Termination voltage in HS (1)
-10
10
mV
Data pull-up/Pull-down resistors
RPU
Data line pull-up
resistance (DP, DM)
VIHZ
FS idle high level voltage
RPD
Data line pull-down
resistance (DP, DM)
1.425
kΩ
2.7
V
14.25
24.8
kΩ
Voltage regulator
3V3V
3.3V internal power
supply voltage
VBAT = 3.6V, active mode
3.26
3.4
3.54
V
1V2V
1.2V internal power
supply voltage
VBAT = 3.6V, active mode
1.187
1.25
1.31
V
1. Guaranteed by design.
13/44
Electrical characteristics
Table 7.
STULPI01A - STULPI01B
Switching characteristics
(Over recommended operating conditions unless otherwise noted. All the typical values are
referred to TA = 25 °C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 µF)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Reset
tRESETEXT
Width of reset pulse on RESETn pin
10
µs
UART mode
tRISE
Switching time (max low to min high) CLOAD=185pF
215
ns
tFALL
Switching time (min high to max low) CLOAD=185pF
215
ns
tPD_RX
Delay time (50% DM to 50% D1)
60
ns
tPD_TX
Delay time (50% D0 to 50% DP)
60
ns
2.5
ms
CL=10pF
tUARTON2V7 Turn-on time for TXD line (2V7)
UART_2V7 = 1 measured
from DIR assertion
tUARTOFF2V7 Turn-off time for TXD line (2V7)
UART_2V7 = 1 measured
from STP assertion
1
µs
2
tUARTON
Turn-on time for TXD line
UART_2V7 = 0 measured
from DIR assertion
60
ns
tUARTOFF
Turn-off time for TXD line
UART_2V7 = 0 measured
from DIR de-assertion
60
ns
Low-speed driver
tLR
Data signal rise time
CLOAD = 600pF
75
100
300
ns
tLF
Data signal fall time
CLOAD = 600pF
75
100
300
ns
20
%
RFMLS
Rise and fall time matching
-20
DRLS
Low-speed data rate
tDDJ1
Data jitter to next transition
Includes freq. tolerances
-25
25
ns
tDDJ2
Data jitter for paired transitions
Includes freq. tolerances
-14
14
ns
1250
1500
ns
tLEOPT
1.49925
SE0 interval of EOP
1.50075 Mb/s
Full-speed driver
tFR
Data signal rise time
CLOAD = 50pF
4
20
ns
tFF
Data signal fall time
CLOAD = 50pF
4
20
ns
-10
+10
%
11.994
12.006
Mb/s
RFMFS
DRHS
Rise and fall time matching
Full-speed data rate
tDJ1
Data jitter to next transition
Includes freq. tolerances
-3.5
3.5
ns
tDJ2
Data jitter for paired transitions
Includes freq. tolerances
-4
4
ns
160
175
ns
tFEOPT
SE0 interval of EOP
Clock generation constants
tPLL
tDLL
14/44
PLL lock time
(1)
200
µs
DLL lock time
(1)
280
µs
STULPI01A - STULPI01B
Table 7.
Electrical characteristics
Switching characteristics (continued)
(Over recommended operating conditions unless otherwise noted. All the typical values are
referred to TA = 25 °C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 µF)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
High-speed driver
tHSR
Data rise time
500
ps
tHSF
Data fall time
500
ps
Waveform requirements including
jitter
DRHS
Specified by eye pattern
(Figure 3)
High-speed data rate
479.76
480.24
Mb/s
ULPI interface
CLOCK (measured on CLK pin)
fSTART_U
Frequency (first transition)
fSTEADY_U
Frequency (steady state)
DSTART_U
Duty cycle (first transition)
(1)
DSTEADY_U
Duty cycle (steady state)
(1)
TSTEADY_U
Time to reach steady state
frequency and duty cycle after first
transition
(1)
TJITTER_U
Jitter
tSCLK60OUT Clock start up time
54
60
66
MHz
59.97
60
60.03
MHz
40
50
60
%
45
50
55
%
1.4
ms
400
Measured from assertion
of STP during suspend, or
after release of RESETn
pin
250
ps
900
µs
ULPI control signals (SDR mode) (1)
TSC_U
Control in setup time
THC_U
Control in hold time
TDC_U
Control output delay
CLOAD = 15pF
V1V8VIO = 1.65 - 1.95V
6.0
ns
0.0
ns
9.0
ns
ULPI data signals (SDR mode) (1)
TSD_U
Data in setup time
THD_U
Data in hold time
TDD_U
Data output delay
CLOAD = 15pF
V1V8VIO = 1.65 - 1.95V
6.0
ns
3.0
ns
9.0
ns
1. Guaranteed by design.
15/44
Electrical characteristics
Figure 3.
STULPI01A - STULPI01B
High-speed driver eye pattern
Level 1
Point 3
+400mV
differential
Point 4
Point 1
0V
differential
Point 2
Point 5
Point 6
-400mV
differential
Level 2
0%
Table 8.
Unit Interval
100%
High-speed driver eye pattern
Level 1
Voltage Level
(DP – DM)
Time
(% of Unit Interval)
Level 2
525mV (1) -525mV (1)
475mV
-475mV
Point 1
Point 2
Point 3
Point 4
Point 5
Point 6
0V
0V
300mV
300mV
-300mV
-300mV
5%
95%
35%
65%
35%
65%
1. This value is valid for unit intervals following a transition. For all other intervals the other value is valid.
16/44
STULPI01A - STULPI01B
Timing diagram
5
Timing diagram
Figure 4.
Rise and fall time
Figure 5.
Simplified block diagram
ID
VBUS
VB_REF_FAULT
PSWn
RESETn
XI
XO
Oscillator
&
PLL
OTG Block
Over
Current
Fault
Detector
Charge Pump,
VBUS Comparators
ID Detector
1V8VIO
Power
On Reset
GND
CLK
STP
NXT
D0 - D7
ULPI Wrapper
DIR
UTMI +
UTMI +
Interface
Core
USB 2.0
PHY
Dual
Voltage
Regulator
Voltage
Reference
DP
VBAT
GND
RREF
DM
17/44
Block description
6
STULPI01A - STULPI01B
Block description
The STULPI01 integrates a comparator for the VBUS, ID line detector, differential HS data
driver, differential and single-ended receivers, low dropout voltage regulators, and control
logic.
The STULPI01 provides a complete solution for connection of a digital USB
host/device/OTG controller to a USB bus.
6.1
Oscillator and PLL
An external clock (digital square wave 1V8VIO referred) driven into XI must be used (version
STULPI01A or STULPI01B).
The PLL internally produces all frequencies needed for operation:
6.2
●
60 MHz clock for the UTMI core and ULPI interface controller
●
1.5 MHz for low speed USB data
●
12 MHz for full speed USB data
●
480 MHz for high speed USB data
●
Other internal frequencies for data conversion and data recovery
Voltage reference
This block provides the precise reference voltage needed by internal circuit.
It requires a 12 kΩ +/- 1% resistor connected to the RREF pin.
6.3
Power-on-reset (POR)
The power-on-reset circuit generates a reset pulse upon power-up which is used to initialize
the entire digital logic. Power-on-reset senses the V3V3V and V1V2V voltage.
During power-on-reset pulse, the ULPI pins are in a high impedance state with pulldown/pull-up resistors disabled.
6.4
UTMI + CORE
This is the digital heart of the chip and performs the bit-stuffing, NRZI decoding and serialto-parallel conversion during receive and the reverse operation during transmit for HS and
FS/LS.
6.5
ULPI wrapper
This implements the ULPI related protocol and conversion from UTMI+ to ULPI interface.
This block also implements the interrupt logic and complete ULPI register set.
18/44
STULPI01A - STULPI01B
6.6
Block description
External charge pump
It is possible to use an external charge pump or power switch controlled by the PSWn pin
(active low open drain). This functionality is controlled by DrvVbus and DrvVbusExternal
ULPI OTG Control register bits.
6.7
VBUS comparators and VBUS over current (OC) detector
These comparators monitor the VBUS voltage.
VBUS valid status signalizes that the voltage is above the VBUS_VLD level (4.4 V). Session
valid status signalizes that the VBUS voltage is above the VSESS_VLD level (0.8 to 2.0 V).
Session end detector signalizes VBUS voltage is below VSESS_END level.
STULPI01 also implements embedded VBUS over current detector which compares VBUS
voltage to external analog 5 V reference signal applied to VB_REF_FAULT pin.
6.8
VB_REF_FAULT pin
VBUS over-current conditions can be monitored by either internal or an external OC detector.
The internal OC detector is enabled when over-current_PD bit in the Power Control register
(Vendor-specific area) is set to 0b and Use External VBUS Indicator is set to 1b. In this
mode, the VB_REF_FAULT pin functions as the input of the analog reference for internal
over-current detector.
If the external charge pump is already equipped with an over-current detector, its output can
be also monitored through VB_REF_FAULT pin, but over-current_PD bit must be set to 1b.
In this mode VB_REF_FAULT will function as standard digital input pin with 5 V tolerance.
Functionality of VB_REF_FAULT pin can be seen in more detail (on Figure 6).
Note:
After reset, over-current_PD bit is 1b, internal over-current detector is disabled.
Figure 6.
VB_REF_FAULT pin functionality
VBUS
VBUS
+
VBUSVLD
Internal VBUS Valid
[0,X]
REF
VBREF_FAULT
-
+
VBREF
RX CMD VBUS Valid
[1,0]
VBUS
VBOC
0
[1,1]
/EN
1
2
EN
RIN_VBREF
FAULT
[UseExternalVbusIndicator, IndicatorPassthru]
SCHMIT
(5 V TOLERANT)
OverCurrent_PD or neg (UseExternalVbusIndicator)
IndicatorComplement
19/44
Block description
Table 9.
STULPI01A - STULPI01B
VB_REF_FAULT configuration bit settings
RX CMD VBUS Valid
Use External
Vbus Indicator
Over-current_PD
Indicator Pass-true
Indicator
Complement
VBUSVLD
0
1
X
X
VBOC
1
0
1
X
VBOC and VBUSVLD
1
0
0
X
neg (FAULT)
1
1
1
0
FAULT
1
1
1
1
VBUSVLD and FAULT
1
1
0
1
VBUS_VLD and neg (FAULT)
1
1
0
0
6.9
Voltage regulator
Dual output ultra low dropout voltage regulator provides power supply for analog and digital
internal circuits. An external capacitor on both 3V3V and 1V2V pins is needed for proper
operation.
6.10
ID detector
This block provides sensing of status of the ID line. It is capable of detecting whether the pin
is floating or tied to the ground.
6.11
USB 2.0 PHY
The USB 2.0 PHY block provides complete physical layer transceiver for low-speed, fullspeed, and high-speed USB operating modes. Analog part of this block deals with
impedances adaptation, controlled voltage swing, and common mode voltage generation
and sensing. Digital part consists of serializer and deserializer, transforming serial bit
stream to 8-bit parallel port, and finite state machine implementing the PHY protocol layer,
bit stuffing, unstuffing etc.
20/44
STULPI01A - STULPI01B
Figure 7.
Block description
USB 2.0 PHY block diagram
3.3V
1.5kΩ
HS
Ser-Des
DP
19.25kΩ
45 Ω
LS/FS
Ser-Des
3.3V
1.5kΩ
DN
HS Disconnect Det.
Squelch Detector
LS/FS SE Receivers
6.12
19.25kΩ
Power saving features
To reduce power consumption STULPI01 implements 2 low power modes of operation.
1. Low power mode, which is defined in ULPI specification.
2. Power-down mode to save more power in case USB function is not needed.
More information on these modes can be found in following paragraph:
6.13
Modes of operation
6.13.1
ULPI synchronous mode
STULPI01 transceiver supports SDR mode operation (12 pin interface). The selection of
SDR mode is performed during startup reset procedure.
6.13.2
6 pin FS/LS serial mode
This mode is entered by writing to corresponding bit in the Interface Control register.
6.13.3
3 pin FS/LS serial mode
This mode is entered by writing to corresponding bit in the Interface Control register.
21/44
Block description
6.14
STULPI01A - STULPI01B
Car kit (UART) mode
This mode is entered by writing to the car kit mode bit in the interface control register.
STULPI01 does not implement all features of car kit mode, only the UART functionality is
preserved.
Table 10.
Car kit signals mapping
Default car kit signals mapping (UART_DIR = 0)
Signal
ULPI lines
TXD
DATA[0] (input)
RXD
DATA[1] (output) <-
reserved
INT
USB lines
->
DM (output)
DP (input)
DATA[2] (input)
DATA[3] (output)
Car kit signals mapping (UART_DIR = 1)
Signal
ULPI lines
TXD
DATA[0] (input)
RXD
DATA[1] (output) <-
reserved
INT
->
USB lines
DP (output)
DM (input)
DATA[2] (input)
DATA[3] (output)
TXD or RXD paths are activated only when corresponding bits TXD_EN/RXD_EN in car kit
Control Register bits (Table 23) are set.
UART_2V7 bit controls the voltage level of UART signaling. In case 2V7 volt signaling is
used, after the UART mode is entered, PLL is disabled and the voltage on the regulator
output starts to decrease to 2.7 V. After time marked as tUARTON2V7 the TXD output on USB
bus is enabled.
When leaving car kit mode, TXD is disabled immediately when STP pin is asserted. The
time required to exit car kit mode is equivalent to the time needed for PLL startup.
When 3.3 volt UART signaling is selected, TXD line is enabled immediately after entering
car kit mode, and disabled after exit from this mode.
Note:
When car kit mode is used with 2V7 signaling, PLL and output clock is always stopped
regardless on the setting of ClockSuspendM bit.
6.15
Low power mode
STULPI01 enters low power mode when SuspendM bit in interface control register is set to
0b. Most of the references are turned off, PLL and clock are turned off, but the full wake-up
capability as defined in the ULPI specification is still maintained.
When in low power mode, the PHY drives D3-D0 with the signals listed in table below. Line
state is driven combinatorially from the SE receivers. The INT signal is asserted whenever
any unmasked interrupt occurs. The PHY latches interrupt events directly from analog
circuitry because the clock is powered down.
22/44
STULPI01A - STULPI01B
Table 11.
Block description
Low power mode
Signal
Map to
Dir
Description
linestate (0)
D0
out
Driven combinatorially from SE receivers
linestate (1)
D1
out
Driven combinatorially from SE receivers
reserved
D2
out
Reserved
INT
D3
out
Active high interrupt indication. Asserted whenever
any unmasked interrupt occurs.
Low power mode is exited by asserting STP pin high. PLL is started immediately, and when
the clock becomes stable, it is passed on the output of CLK pin. Then after minimum of 5
clock cycles DIR is deasserted and low power mode is exited. SuspendM bit is reset to 1b.
Note:
STP signal must be kept high until the DIR is deasserted, otherwise low power mode will not
be exited.
6.16
Power down mode
Power down mode is entered by asserting the CSn/PWRDN pin high. Internal voltage
regulators are disabled, and the device has minimum possible power consumption.
STULPI01 has no wake-up capability or USB functionality during power down mode. This
mode can be exited by deasserting CSn/PWRDN pin. Voltage regulators will be turned on
and internal power-on-reset circuit will reset the chip to initial state. ULPI interface pins are
in high impedance state during power down mode.
6.17
VIO OFF mode
In case 1V8VIO voltage is below the minimum value, the VIO OFF mode is entered. The
behavior of the device in VIO OFF mode is the same as in power down mode.
6.18
Start-up procedure
6.18.1
ULPI device detection
Link detects ULPI device presence by sampling the DIR signal at the reset time (Figure 8).
The NXT signal is '0' after reset to signalize 8-bit device to link controller. CLK is '1' to
signalize a DDR capable device.
6.18.2
SDR mode selection
The STULPI01 samples the D0 line on the first rising edge of the output clock on the CLK
pin. When the sampled value is '0', the STULPI01 remains in SDR mode.
SDR mode can be selected again only after hardware reset. During software reset mode,
selection is not performed.
Note:
IMPORTANT: The controller must not drive the DATA lines to a value other than 0x00 or
0x01 during the first rising edge of ULPI CLK, otherwise the behavior of the device may be
undefined.
23/44
Block description
6.18.3
STULPI01A - STULPI01B
External clock detection
The square wave clock can be applied to the oscillator input. The input square wave clock
amplitude is referenced to the 1V8VIO voltage.
The XO pin can be left floating or grounded.
6.18.4
Reset behavior
Typical startup sequence is shown in Figure 9.
STULPI01 contains internal power-on-reset generator which senses the V3V3V and V1V2V
voltage. Assertion of RESETn is not necessary for proper initialization. However, if required,
this pin can be also used. The internal reset signal is the combination of the signal from
RESETn pin and the signal from the internal power-on-reset circuit.
When RESETn is asserted, all internal registers are reset to their default values, the output
DIR signal is driven to '1', and data lines pulled low by weak pull-downs.
During reset the STP pin can be driven low, high, or can be left floating. It will be pulled up
by internal pull-up and the ULPI interface enters a holding state.
During the reset state the NXT signal is driven low and the CLK is driven high.
When the PLL is stabilized, the clock on the CLK pin is enabled, and DIR is deasserted.
Note:
NOTE: The minimum duration of the external reset signal is TRESETEXT. (See chapter
Crystal or external clock detection).
When internal POR reset is asserted, the reset procedure is equivalent to the RESETn
signal, with the only exception being that the ULPI lines are in high impedance state. All pulldowns and pull-ups on the ULPI signals are also disabled.
6.18.5
Interface protection
The STULPI01 activates weak pull-downs on data lines and pull-up on the STP during reset
and holding state. These are to provide interface protection during startup and anytime the
link is not able to drive the ULPI lines properly.
The holding state is entered when the controller drives the STP for more than 1 clock cycle.
Any command on the ULPI bus is ignored in this state. For more information, see ULPI
specification 1.1, section 3.12 (Safeguarding PHY input signals).
Interface protection can be switched off at any time after startup in order to save power, by
writing the Interface Protect Disable bit in the Interface Control register to 1b.
6.18.6
Software reset
The STULPI01 supports software reset by writing the RESET bit in the function control
register to 1b.
During the software reset, DIR is asserted and the pull down resistors on data lines are
enabled, but the ULPI registers remain unaffected. Software reset initializes UTMI core logic
only. Also, during software reset, external clock detection, SDR mode selection is not
performed, and clock is not turned off (PLL is not re-started).
Note:
24/44
NOTE: Software reset is not required in the startup procedure for the STULPI. The chip is
ready for operation after the hardware reset procedure.
STULPI01A - STULPI01B
6.18.7
Block description
High speed mode entry
In high speed mode, the internal 480 MHz clock is generated by the DLL, which must be
calibrated any time device enters high speed mode by writing '00' to the XcvrSel field in the
Function Control register. During the DLL calibration it is not possible to accept any
commands, therefore to avoid any communication problems with the controller the clock on
the ULPI interface is stopped. See Figure 10 for more information.
Figure 8.
Start-up sequence
Figure 9.
RESETn behavior
25/44
Block description
Figure 10. High speed mode entry
Figure 11. UART mode entry (2.7 V)
26/44
STULPI01A - STULPI01B
STULPI01A - STULPI01B
Block description
Figure 12. UART mode exit (2.7 V)
27/44
State transitions
7
State transitions
Table 12.
USB state transitions
STULPI01A - STULPI01B
TermSelect
OpMode
DpPulldown
DmPulldown
rpu_dp_en
rpu_dm_en
rpd_dp_en
rpd_dm_en
hsterm_en
Resistor settings
XcvrSelect
Register settings
XXb
Xb
01b
0b
0b
0b
0b
0b
0b
0b
XXb
Xb
01b
1b
1b
0b
0b
1b
1b
0b
01b
0b
00b
1b
1b
0b
0b
1b
1b
0b
Host chirp
00b
0b
10b
1b
1b
0b
0b
1b
1b
1b
Host hi-speed
00b
0b
00b
1b
1b
0b
0b
1b
1b
1b
Host full speed
X1b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host HS/FS suspend
01b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host HS/FS resume
01b
1b
10b
1b
1b
0b
0b
1b
1b
0b
Host low speed
10b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host low speed suspend
10b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host low speed resume
10b
1b
10b
1b
1b
0b
0b
1b
1b
0b
Host test_J/Test_K
00b
0b
10b
1b
1b
0b
0b
1b
1b
1b
Peripheral chirp
00b
1b
10b
0b
0b
1b
0b
0b
0b
0b
Peripheral hi-speed
00b
0b
00b
0b
0b
0b
0b
0b
0b
1b
Peripheral full speed
01b
1b
00b
0b
0b
1b
0b
0b
0b
0b
Peripheral HS/FS suspend
01b
1b
00b
0b
0b
1b
0b
0b
0b
0b
Peripheral HS/FS resume
01b
1b
10b
0b
0b
1b
0b
0b
0b
0b
Peripheral low speed
10b
1b
00b
0b
0b
0b
1b
0b
0b
0b
Peripheral low speed suspend
10b
1b
00b
0b
0b
0b
1b
0b
0b
0b
Peripheral low speed resume
10b
1b
10b
0b
0b
0b
1b
0b
0b
0b
Peripheral test_J/Test_K
00b
0b
10b
0b
0b
0b
0b
0b
0b
1b
Signaling mode
General settings
3-state drivers
Power-up or Vbus < Vth(SESSEND)
Host settings
Peripheral settings
28/44
STULPI01A - STULPI01B
Table 12.
State transitions
USB state transitions (continued)
TermSelect
OpMode
DpPulldown
DmPulldown
rpu_dp_en
rpu_dm_en
rpd_dp_en
rpd_dm_en
hsterm_en
Resistor settings
XcvrSelect
Register settings
OTG device, peripheral chirp
00b
1b
10b
0b
1b
1b
0b
0b
1b
0b
OTG device, peripheral hi-speed
00b
0b
00b
0b
1b
0b
0b
0b
1b
1b
OTG device, peripheral full speed
01b
1b
00b
0b
1b
1b
0b
0b
1b
0b
OTG device, peripheral HS/FS suspend
01b
1b
00b
0b
1b
1b
0b
0b
1b
0b
OTG device peripheral, HS/FS resume
01b
1b
10b
0b
1b
1b
0b
0b
1b
0b
OTG device peripheral, Test_J/Test_K
00b
0b
10b
0b
1b
0b
0b
0b
1b
1b
Signaling mode
29/44
ULPI registers
STULPI01A - STULPI01B
8
ULPI registers
Table 13.
ULPI register map overview
Address (6 bits)
Field name
Size (bits)
Rd
Wr
Set
Clr
Immediate register set
Vendor ID Low
8
00h
-
-
-
Vendor ID High
8
01h
-
-
-
Product ID Low
8
02h
-
-
-
Product ID High
8
03h
-
-
-
Function Control
8
04-06h
04h
05h
06h
Interface Control
8
07-09h
07h
08h
09h
OTG Control
8
0A-0Ch
0Ah
0Bh
0Ch
USB Interrupt Enable Rising
8
0D-0Fh
0Dh
0Eh
0Fh
USB Interrupt Enable Falling
8
10-12h
10h
11h
12h
USB Interrupt Status Register
8
13h
-
-
-
USB Interrupt Latch Register
8
14h
-
-
-
Debug
8
15h
-
-
-
Scratch
8
16-18h
16h
17h
18h
Car kit control register
8
16-1Bh
19h
1Ah
1Bh
Reserved
8
Access Extended Register Set (see Table 14)
8
-
-
Reserved
8
1C-2Eh
-
2Fh
30-3Ch
Power control
3D-3Fh
Extended register set
Address (8 bits)
Maps to Immediate Register Set above
8
00-3Fh
Reserved
8
40-FFh
Table 14.
Register access legend
Access code
Expanded name
rd
Read
Register can be read. Read-only if this is the only mode given.
wr
Write
Pattern on the data bus will be written over all bits of the register.
s
Set
Pattern on the data bus is OR’d with and written into the register.
c
Clear
30/44
Meaning
Pattern on the data bus is a mask. If a bit in the mask is set, then the
corresponding register bit will be set to zero (cleared).
STULPI01A - STULPI01B
Table 15.
ULPI registers
Vendor and product ID
Register
Bits
Access
Address
Value
Description
VENDOR_ID_LOW
7:0
rd
00h
83 h
Lower byte of vendor ID.
VENDOR_ID_HIGH
7:0
rd
01h
04 h
Upper byte of vendor ID.
PRODUCT_ID_LOW
7:0
rd
02h
4b h
Lower byte of product ID number.
PRODUCT_ID_HIGH
7:0
rd
03h
4f h
Upper byte of product ID number.
Table 16.
Power control register
(3Dh-3Fh Read, 3Dh Write, 3Eh Set, 3Fh Clear)
(Controls various power aspects of the USB trans)
Field name
Bits
Access
Reset
Reserved
0
rd/wr/s/c
0b
Reserved. The link must never write a 1b to this bit.
Over-current_PD
1
rd/wr/s/c
1b
Power control of the internal over-current circuit.
0b: Enables the over-current circuit.
1b: Disables the over-current circuit.
UART_DIR
2
rd/wr/s/c
0b
0b: Txd on DM and Rxd on DP
1b: Txd on DP and Rxd on DM
UART_2V7
3
rd/wr/s/c
1b
0b: UART signaling at 3V3
1b: UART signaling at 2V7
7:4
rd/wr/s/c
0b
Reserved. The link must never write a 1b to these bits.
Reserved
Description
31/44
ULPI registers
Table 17.
Field name
XcvrSelect
TermSelect
OpMode
Reset
STULPI01A - STULPI01B
Function control register
04h-06h(Read), 04h(Write), 05h(Set), 06h(Clear)
(Controls UTMI function setting of the USB transceiver PHY)
Bits
1:0
2
4:3
5
Access
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
Reset
Description
01b
Selects the required transceiver speed.
00b: Enable HS transceiver
01b: Enable FS transceiver
10b: Enable LS transceiver
11b: Enable FS transceiver for LS packets (FS preamble
is automatically pre-pended)
IMPORTANT NOTE: Every time the XcvrSelect is
changed to ‘00’, the output ULPI clock is stopped for the
time needed for internal DLL calibration.
0b
Controls the internal pull-up resistors or HS terminations.
Control over these resistors changes depending on
XcvrSelect, OpMode, DpPulldown and DmPulldown, as
shown in Table 24.
00b
Selects the required bit encoding style during transmit.
00b: Normal operation
01b: Non-driving
10b: Disables bit-stuff and NRZI encoding
11b: Do not automatically add SYNC and EOP when
transmitting. Must be used only for HS packets.
0b
Active high transceiver reset. After the Link sets this bit,
STULPI01 asserts DIR and reset the UTMI+ core. When
the reset is completed, STULPI01 de-asserts DIR and
automatically clears this bit. After de-asserting DIR,
STULPI01 re-asserts DIR and sends an RX CMD update
to the Link.
Note: If Reset bit is set to ‘1’ and SuspendM bit is set to ‘0’
in the same register access, SuspendM bit takes higher
priority and chip will enter low power mode. Reset bit will
be cleared.
SuspendM
6
rd/wr/s/c
1b
Active low PHY suspend. Puts PHY into Low Power
Mode. STULPI01 automatically sets this bit to ‘1’ when
Low Power Mode is exited.
0b: Low Power Mode
1b: Powered
Note: If Reset bit is set to ‘1’ and SuspendM bit is set to ‘0’
in the same register access, SuspendM bit takes higher
priority and chip will enter low power mode. Reset bit will
be cleared.
Reserved
7
rd/wr/s/c
0b
Reserved
32/44
STULPI01A - STULPI01B
Table 18.
ULPI registers
Interface control register
07h-09h(Read), 07h(Write), 08h(Set), 09h(Clear)
(Enables alternative interface and STULPI01 features.)
Field name
6-pin
FsLsSerialMode
3-pin
FsLsSerialMode
Carkit mode
Bits
0
1
2
Access
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
Reset
Description
0b
Changes the ULPI interface to 6-pin serial mode. The
STULPI01 automatically clears this bit when serial mode is
exited.
0b: FS/LS packets are sent using parallel interface.
1b: FS/LS packets are sent 6-pin using serial interface.
0b
Changes the ULPI interface to 3-pin serial mode. STULPI01
automatically clears this bit when serial mode is exited.
0b: FS/LS packets are sent using parallel interface.
1b: FS/LS packets are sent using 4-pin serial interface.
0b
STULPI01 does not support all the features of car kit mode.
Only the UART functionality is implemented.
0b: Disables serial car kit mode.
1b: Enables serial car kit mode.
ClockSuspendM
3
rd/wr/s/c
0b
Active low clock suspend. Valid only in serial mode and car
kit mode. Powers down the internal clock circuitry. Valid only
when SuspendM = 1b. STULPI01 ignores ClockSuspend
when SuspendM = 0b. By default, the clock will not be
powered in Serial and car kit modes.
0b: Clock will not be powered in serial and car kit modes.
1b: Clock will be powered in Serial and car kit modes.
Reserved
4
rd/wr/s/c
0b
STULPI01 do not implement autoresume feature, because
the clock can be restarted in less than 1ms.
0b
Tells to invert the ExternalVbusIndicator signal, generating
the complement output.
0b: STULPI01 will not invert ExternalVbusIndicator signal
1b: STULPI01 will invert ExternalVbusIndicator signal.
0b
Controls whether the complement output is qualified with the
Internal VbusValid comparator before being used in the
Vbus State in the RX CMD.
0b: complement output signal is qualified with the Internal
VbusValid comparator.
1b: complement output signal is not qualified with the
Internal VbusValid comparator.
0b
Controls circuitry for protecting the ULPI interface when the
link 3-states STP and DATA. This bit is not intended to affect
the operation of the holding state. Refer to section 3.12 of
ULPI specification 1.1 for more details.
0b: Enables the interface protect circuit (default).
1b: Disables the interface protect circuit.
Interface protection circuit consists of pull-down resistors on
DATA and pull-up resistor on STP.
Indicator
complement
Indicator
PassThru
Interface protect
disable
5
6
7
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
33/44
ULPI registers
Table 19.
STULPI01A - STULPI01B
OTG control register
0Ah-0Ch(Read), 0Ah(Write), 0Bh(Set), 0Ch(Clear)
(Controls UTMI + OTG functions of the PHY)
Field name
Bits
Access
Reset
Description
IdPullup
0
rd/wr/s/c
0b
Connects a pull-up to the ID line and enables sampling of the
signal level.
0b: Disables sampling of ID line.
1b: Enables sampling of ID line.
DpPulldown
1
rd/wr/s/c
1b
Enables the 15kOhm pull-down resistor on DP.
0b: Pull-down resistor not connected to DP.
1b: Pull-down resistor connected to DP.
DmPulldown
2
rd/wr/s/c
1b
Enables the 15kOhm pull-down resistor on DM.
0b: Pull-down resistor not connected to DM.
1b: Pull-down resistor connected to DM.
DischrgVbus
3
rd/wr/s/c
0b
Discharges VBUS through a resistor. If the link sets this bit to 1,
it waits for an RX CMD indicating SessEnd has transition from 0
to 1, and then resets this bit to 0 to stop the discharge.
0b: Do not discharge VBUS
1b: Discharge VBUS
ChrgVbus
4
rd/wr/s/c
0b
Charge VBUS through a resistor. Used for VBUS pulsing SRP.
0b: Do not charge VBUS
1b: Charge VBUS
DrvVbus
5
rd/wr/s/c
0b
Signals the internal charge pump or external supply to drive 5V
on VBUS.
0b: Do not drive VBUS (default)
1b: Drive 5V on VBUS
DrvVbus External
6
rd/wr/s/c
0b
Selects between the internal and the external 5V VBUS supply.
0b: Drive VBUS using the internal charge pump (default).
1b: Drive VBUS using external supply.
0b
Tells STULPI01 to use an external VBUS over-current indicator.
0b: Use the internal OTG comparator or internal
VBUS valid indicator (default)
1b: Use external VBUS valid indicator signal
UseExternal
VbusIndicator
34/44
7
rd/wr/s/c
STULPI01A - STULPI01B
Table 20.
ULPI registers
USB interrupt enable rising register
0Dh-0Fh(Read), 0Dh(Write), 0Eh(Set), 0Fh(Clear)
(If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from low to high. By default, all transitions are enabled. RxActive and
RxError must always be communicated immediately and so are not included in this register. Interrupt
circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To
ensure interrupts are detectable when clock is powered down, the link should enable both rising and
falling edges.)
Field name
Bits
Access
Reset
Description
Host disconnect rise
0
rd/wr/s/c
1b
Generates an interrupt event notification when host
disconnect changes from low to high. Applicable only in
host mode (DpPulldown and DmPulldown both set to
1b).
VbusValid rise
1
rd/wr/s/c
1b
Generates an interrupt event notification when
VbusValid changes from low to high.
SessValid rise
2
rd/wr/s/c
1b
Generate an interrupt event notification when SessValid
changes from low to high. SessValid is the same as
UTMI+ Avalid.
SessEnd rise
3
rd/wr/s/c
1b
Generates an interrupt event notification when SessEnd
changes from low to high.
ID rise
Reserved
4
rd/wr/s/c
1b
Generates an interrupt event notification when ID
changes from low to high. ID is valid 50ms after IdPullup
is set to 1b, otherwise ID is undefined and should be
ignored.
7:5
rd/wr/s/c
0b
Reserved.
35/44
ULPI registers
Table 21.
STULPI01A - STULPI01B
USB interrupt enable falling register
Address: 10h-12h (Read), 10h (Write), 11h (Set), 12h (Clear)
(If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from high to low. By default, all transitions are enabled. RxActive and
RxError must always be communicated immediately and so are not included in this register. Interrupt
circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To
ensure interrupts are detectable when clock is powered down, the link should enable both rising and
falling edges.)
Field name
Bits
Access
Reset
Description
Host disconnect fall
0
rd/wr/s/c
1b
Generates an interrupt event notification when the host
disconnect changes from high to low. Applicable only in
host mode.
VbusValid fall
1
rd/wr/s/c
1b
Generates an interrupt event notification when
VbusValid changes from high to low.
SessValid fall
2
rd/wr/s/c
1b
Generates an interrupt event notification when
SessValid changes from high to low. SessValid is the
same as UTMI+ AValid.
SessEnd fall
3
rd/wr/s/c
1b
Generates an interrupt event notification when SessEnd
changes from high to low.
ID fall
Reserved
Table 22.
4
rd/wr/s/c
1b
Generates an interrupt event notification when ID
changes from high to low. ID is valid 50ms after IdPullup
is set to 1b, otherwise ID is undefined and should be
ignored.
7:5
rd/wr/s/c
0b
Reserved
USB interrupt status register
Address: 13h (Read-only)
(Indicates the current value of the interrupt source signal. Interrupt circuitry can be powered down in any
mode when both rising and falling edge enables are disabled. To ensure interrupts are detectable when
clock is powered down, the link should enable both rising and falling edges.)
Field name
Bits
Access
Reset
Host disconnect
0
rd
0b
Current value of UTMI+ Host disconnect output.
Applicable only in host mode. Automatically reset to 0b
when Low Power Mode is entered.
VbusValid
1
rd
0b
Current value of UTMI+VbusValid output.
SessValid
2
rd
0b
Current value of UTMI+SessValid output. SessValid is the
same as UTMI+ AValid.
SessEnd
3
rd
0b
Current value of UTMI+SessEnd output.
ID
4
rd
0b
Current value of UTMI+ID output. ID is valid 50ms after
IdPullup is set to 1b, otherwise ID is undefined and should
be ignored.
7:5
rd
0b
Reserved
Reserved
36/44
Description
STULPI01A - STULPI01B
Table 23.
ULPI registers
USB interrupt latch register
Address: 14h (Read-only with auto clear)
(These bits are set by the STULPI01 when an unmasked change occurs on the corresponding internal
signal. The STULPI01 will automatically clear all bits when the link reads this register, or when low power
mode is entered. The STULPI01 also clears this register when serial mode or car kit mode is entered
regardless of the value of ClockSuspendM. The interrupt circuitry is powered down in any mode when
both rising and falling edge enables are disabled. To ensure the interrupts are detectable when the clock
is powered down, the link should enable both rising and falling edges.
The STULPI01 follows the rules in Table 20 for setting any latch register bit. It is important to note that if
the register read data is returned to the Link in the same cycle that a USB interrupt latch bit is to be set,
the interrupt condition is given immediately in the register read data and the latch bit is not set.
Note that it is optional for the link to read the USB interrupt latch register in synchronous mode because
the RX CMD byte already indicates the interrupt source directly.)
Field name
Bits
Access
Reset
Host disconnect
latch
0
rd
0b
Set to 1b by the STULPI01 when an unmasked event
occurs on host disconnect. Cleared when this register is
read. Applicable only in host mode.
VbusValid latch
1
rd
0b
Set to 1b by the STULPI01 when an unmasked event
occurs on VbusValid. Cleared when this register is read.
SessValid latch
2
rd
0b
Set to 1b by the STULPI01 when an unmasked event
occurs on SessValid. Cleared when this register is read.
SessValid is the same as UTMI+Avalid.
SessEnd latch
3
rd
0b
Set to 1b by the STULPI01 when an unmasked event
occurs on SessEnd. Cleared when this register is read.
ID latch
Reserved
Table 24.
Description
4
rd
0b
Set to 1b by the STULPI01 when an unmasked event
occurs on ID. Cleared when this register is read. ID is valid
50ms after ID is set to 1b, otherwise ID is undefined and
should be ignored.
7:5
rd
0b
Reserved
Setting rules for interrupt latch register
Input conditions
Resultant value of latch register bit
Register read data returned in
current clock cycle
Interrupt latch bit is to be set in
current clock cycle
No
No
0
No
Yes
1
Yes
No
0
Yes
Yes
0
37/44
ULPI registers
Table 25.
STULPI01A - STULPI01B
Debug register
Address: 15h (Read-only)
(Indicates the current value of various signals useful for debugging)
Field name
Bits
Access
Reset
LineState0
0
rd
0b
Contains the current value of LineState(0)
LineState1
1
rd
0b
Contains the current value of LineState(1)
Reserved
7:2
rd
0b
Reserved
Table 26.
Description
Scratch register
Address: 16h-18h (Read), 16h (Write), 17h (Set), 18h (Clear).
Field name
Bits
Access
Reset
Description
Scratch
7:0
rd/wr/s/c
00b
Empty register byte for testing purposes. The software can read,
write, set, and clear this register and the STULPI01 functionality
will not be affected.
Table 27.
Field name
Carkit control register
Address: 19h-1Bh (Read), 19h (Write), 1Ah (Set), 1Bh (Clear).
Bits
Access
Reset
reserved
0
rd/wr/s/c
0b
reserved
1
rd/wr/s/c
0b
TxdEn
2
rd/wr/s/c
0b
Enables TXD signal in car kit mode
RxdEn
3
rd/wr/s/c
0b
Enables RXD signal in car kit mode
reserved
4
rd/wr/s/c
0b
reserved
5
rd/wr/s/c
0b
reserved
6
rd/wr/s/c
0b
reserved
7
rd/wr/s/c
0b
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Description
STULPI01A - STULPI01B
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
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Package mechanical data
STULPI01A - STULPI01B
TFBGA36 mechanical data
mm.
mils.
Dim.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
1.0
1.1
1.16
39.4
43.3
45.7
A1
0.25
A2
0.78
b
0.25
D
3.5
D1
E
9.8
0.86
30.7
0.30
0.35
9.8
11.8
13.8
3.6
3.7
137.8
141.7
145.7
2.5
3.5
3.6
33.9
98.4
3.7
137.8
141.7
E1
2.5
98.4
e
0.5
19.7
F
0.55
21.7
145.7
7941410/B
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STULPI01A - STULPI01B
Package mechanical data
Tape & reel TFBGA36 mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
330
13.2
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
Max.
0.504
0.519
14.4
0.567
Ao
3.9
0.154
Bo
3.9
0.154
Ko
1.50
0.059
Po
3.9
4.1
0.154
0.161
P
7.9
8.1
0.311
0.319
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Order codes
STULPI01A - STULPI01B
10
Order codes
Table 28.
Order codes
Order code
Key differences
STULPI01ATBR (1) fOSC=19.2MHz, CSn/PWRDN=0 “ON”
STULPI01BTBR
(1)
fOSC=26MHz, CSn/PWRDN=0 “ON”
Package
Packaging
µTFBGA36 (3.6x3.6mm Typ)
3000 parts per reel
µTFBGA36 (3.6x3.6mm Typ)
3000 parts per reel
1. All these versions need digital external clock on XI pin; XO pin must be left floating or grounded (Crystal is not supported).
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STULPI01A - STULPI01B
Revision history
11
Revision history
Table 29.
Document revision history
Date
Revision
20-Jun-2008
1
Changes
First release.
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STULPI01A - STULPI01B
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