CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER GND GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND GND GND GND VCXO or VCC I_REF_CP E VCXO_IN GND VCC VCC VCC VCC VCC VCC F Y0A GND GND GND GND GND VCC Y4B G Y0B VCC VCC VCC VCC VCC VCC Y4A H PD Y1A Y1B Y2A Y2B Y3A Y3B RESET or HOLD SEC_REF CTRL_DATA PLL_LOCK CTRL_CLK AVCC AVCC CTRL_LE AVCC P0022-01 36 35 34 33 32 31 30 29 28 27 26 25 24 37 GND AVCC 38 23 AVCC 39 22 STATUS_REF or PRI_SEC_CLK STATUS_VCXO or I_REF_CP VBB 40 21 VCC VCC 41 20 VCC VCXO_IN 42 19 VCC VCXO_IN 43 18 VCC VCC 44 17 Y4B VCC 45 16 Y4A Y0A 46 15 VCC Y0B 47 14 VCC 48 1 2 3 4 5 6 7 8 9 13 10 11 12 RESET or HOLD VCC Y3A Thermal Pad must be soldered to GND Y3B • • • SEC_REF VCC • B VCC • CTRL_ DATA PLL_LOCK Y2A • • 8 Y2B • 7 PRI_REF REF_SEL VCC_CP CP_OUT CTRL_LE CTRL_CLK CP_OUT • 6 VCC • 5 VCC • • 4 A NC • 3 VCC_CP • 2 Y1A • 1 Y1B • PIN ASSIGNMENTS (TOP VIEW) PRI_REF • or 48-Pin QFN (RGZ) Industrial Temperature Range –40°C to 85°C REF_SEL • • PD • High Performance LVPECL and LVCMOS PLL Clock Synchronizer Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection Accepts LVCMOS Input Frequencies Up to 200 MHz VCXO_IN Clock is Synchronized to One of the Two Reference Clocks VCXO_IN Frequencies Up to 2.2 GHz (LVPECL) Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or Up to 10 LVCMOS Outputs) Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on Each Output Individually Efficient Jitter Cleaning From Low PLL Loop Bandwidth Low Phase Noise PLL Core Programmable Phase Offset (PRI_REF and SEC_REF to Outputs) Wide Charge Pump Current Range From 200 µA to 3 mA Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O Analog and Digital PLL Lock Indication Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN) Frequency Hold-Over Mode Improves Fail-Safe Operation Power-Up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V SPI Controllable Device Setting 3.3-V Power Supply Packaged in 64-Pin BGA (0,8 mm Pitch – ZVA) VCC FEATURES • P0023-01 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 DESCRIPTION The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O: • VC(X)O_IN / PRI_REF = (N x P) / M or • VC(X)O_IN / SEC_REF = (N x P) / M VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, …), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C. 2 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 FUNCTIONAL BLOCK DIAGRAM VCC AVCC VCC_CP Selected REF Signal REF_SEL Manual & Automatic CLK Select STATUS_REF/ PRI_SEC_CLK STATUS_VCXO/ I_REF_CP freq. Detect > 2 Mhz PLL_LOCK freq. Detect > 2 Mhz LVCMOS SEC_REF R EF_M UX PRI_REF Reference Clock Feedback Clock Progr. Delay M Progr. Divider Progr. Delay N Progr. Divider LOCK HOLD PFD Charge Pump 10 M 2 N 2 Current Reference SPI LOGIC CTRL_LE CP_OUT 12 CTRL_DATA CTRL_CLK PECL to LVCMOS LV CMOS RESET or HOLD FB_MUX Y0_MUX Y0A PD LV PECL Y0B LV CMOS LV CMOS Y1_MUX Y1A ÷1 LV PECL Y1B ÷2 LV CMOS ÷3 LV CMOS ÷4 VCXO_IN PECL INPUT Y2A Y2_MUX VCXO_IN ÷6 LV PECL Y2B /8 ÷8 LV CMOS ÷ 16 LV CMOS 90o 90o Y3A Y3_MUX ÷4 ÷8 P16-Div LV PECL P Divider Y3B LV CMOS LV CMOS Bias Generator VCC – 1.3V Y4A Y4_MUX VBB LV PECL Y4B LV CMOS GND B0057-01 3 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Table 1. PIN ASSINGMENT TERMINAL NAME I/O DESCRIPTION BGA QFN VCC D7, E3, E4, E5, E6, E7, E8, F7, G2, G3, G4, G5, G6, G7 2, 5, 6, 9, 10, 13, 15, 18, 19, 20, 21, 41, 44, 45; 48 Power 3.3-V supply. There is no internal connection between VCC and AVCC. It is recommended that AVCC use its own supply filter. GND B2, B3, B4, B5, B6, B7, B8, C2, D2, D3, D4, D5, D6, E2, F2, F3, F4, F5, F6 Thermal pad and pin 24 Ground Ground AVCC C3, C4, C5, C6, C7 27, 30, 32, 38, 39 Analog Power 3.3-V analog power supply. There is no internal connection between AVCC and VCC. It is recommended that AVCC use its own supply filter. VCC_CP A3 33 Power This is the charge pump power supply pin used to have the same supply as the external VCO. It can be set from 2.3 V to 3.6 V. CTRL_LE A5 29 I LVCMOS input, control latch enable for serial programmable Interface (SPI), with hysteresis CTRL_CLK A6 28 I LVCMOS input, serial control clock input for SPI, with hysteresis CTRL_DATA A7 26 I LVCMOS input, serial control data input for SPI, with hysteresis I LVCMOS input, asynchronous power down (PD) signal. This pin is low active and can be activated external or by the corresponding bit in the SPI register (in case of logic high, the SPI setting is valid). Switches the device into power-down mode. Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin and all Yx outputs. Sets the SPI register to default value; has internal 150-kΩ pullup resistor. PD H1 1 This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the default function. This pin is low active and can be activated external or via the corresponding bit in the SPI register. In case of RESET, the charge pump (CP) is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider settings are maintained in SPI registers). The LVPECL outputs are static low and high respectively and the LVCMOS outputs are all low or high if inverted. RESET is not edge triggered and should have a pulse duration of at least 5 ns. RESET or HOLD H8 VCXO_IN E1 43 I VCXO LVPECL input VCXO_IN D1 42 I Complementary VCXO LVPECL input PRI_REF A1 36 I LVCMOS input for the primary reference clock, with an internal 150-kΩ pullup resistor and input hysteresis. SEC_REF B1 37 I LVCMOS input for the secondary reference clock, with an internal 150-kΩ pullup resistor and input hysteresis. 14 I In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is released and with the next valid reference clock cycle the charge pump is switched back in to normal operation (CP stays in 3-state as long as no reference clock is valid). During HOLD, the P divider and all outputs Yx are at normal operation. This mode allows an external control of the frequency hold-over mode. The input has an internal 150-kΩ pullup resistor. REF_SEL A2 35 I LVCMOS reference clock selection input. In the manual mode the REF_SEL signal selects one of the two input clocks: REF_SEL [1]: PRI_REF is selected; REF_SEL [0]: SEC_REF is selected; The input has an internal 150-kΩ pullup resistor. CP_OUT A4 31 O Charge pump output 4 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Table 1. PIN ASSINGMENT (continued) TERMINAL NAME VBB BGA QFN C1 40 I/O DESCRIPTION Bias voltage output to be used to bias unused complementary input VCXO_IN for single ended signals. The output of VBB is VCC– 1.3 V. The output current is limited to about 1.5 mA. O This output can be programmed (SPI) to provide either the STATUS_REF or PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid. STATUS_REF is the default setting. STATUS_REF or PRI_SEC_CLK C8 23 In case of STATUS_REF, the LVCMOS output provides the Status of the Reference Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or SEC_REF STATUS_REF will be set high. O In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock [high] or the secondary clock [low] is selected. This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO information or serve as current path for the charge pump (CP). STATUS_VCXO is the default setting. STATUS_VCXO or I_REF_CP D8 22 In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO input (frequencies above 2 MHz are interpreted as valid clock; active high). O In case of I_REF_CP, it provides the current path for the external reference resistor (12 kΩ± 1%) to support an accurate charge pump current, optional. Do not use any capacitor across this resistor to prevent noise coupling via this node. If the internal 12 kΩ is selected (default setting), this pin can be left open. LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock (see feature description). This output can be programmed to be digital lock detect or analog lock detect (see feature description). PLL_LOCK A8 25 The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the lock detect window for a predetermined number of successive clock cycles. I/O The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect window or if a cycle-slip occurs. Both, the lock detect window and the number of successive clock cycles are user definable (via SPI). Y0A:Y0B Y1A:Y1B Y2A:Y2B Y3A:Y3B Y4A:Y4B F1, G1, H2, H3, H4, H5, H6, H7, G8, F8 46, 47, 3, 4, 7, 8, 11,12, 16, 17 The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are LVPECL. O ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT (2) VCC, AVCC, VCC_CP Supply voltage range VI Input voltage range VO Output voltage range (3) –0.5 V to VCC + 0.5 V IOUT Output current for LVPECL/LVCMOS outputs (0 < VO < VCC) ±50 mA IIN Input current (VI < 0, VI > VCC) Tstg Storage temperature range TJ Maximum junction temperature (1) (2) (3) (3) –0.5 V to 4.6 V –0.5 V to VCC + 0.5 V ±20 mA –65°C to 150°C 125°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All supply voltages have to be supplied at the same time. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 5 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Package Thermal Resistance for RGZ (QFN) Package (1) (2) (1) (2) (3) Airflow (lfm) θJA (°C/W) θJC (°C/W) 22.4 θJP (°C/W) ψJT (°C/W) (3) 0 29.9 150 24.7 1.5 0.2 0.2 250 23.2 0.2 500 21.5 0.3 The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). Connected to GND with nine thermal vias (0,3 mm diameter). θJP (junction pad) is used for the QFN package, because the main heat flow is from the junction to the GND pad of the QFN. Package Thermal Resistance for ZVA (BGA) Package (1) (1) (2) Airflow (m/s) θJA (°C/W) θJC (°C/W) θJB (°C/W) 0 m/s 53.9 28.3 ψJT (°C/W) 1 m/s 49.8 0.7 2 m/s 48.5 0.8 (2) 38.6 0.7 The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). θJB (junction board) is used for the BGA package, because the main heat flow is from junction to the board. RECOMMENDED OPERATING CONDITIONS VCC, AVCC VCC_CP Supply voltage MIN NOM MAX 3 3.3 3.6 2.3 VIL Low-level input voltage LVCMOS, see (1) VIH High-level input voltage LVCMOS, see (1) IOH High-level output current LVCMOS (includes all status pins) IOL Low-level output current LVCMOS (includes all status pins) VI Input voltage range LVCMOS VIL UNIT V VCC 0.3 VCC V 0.7 VCC V –8 mA 8 mA 0 3.6 V Low-level input voltage LVPECL VCC–1.81 VCC–1.475 V VIH High-level input voltage LVPECL VCC–1.26 VCC–0.88 V VINPP Input amplitude LVPECL (VVCXO_IN– VVCXO_IN) (2) 0.5 1.3 V VIC Common-mode input voltage LVPECL 1 VCC–0.3 V TA Operating free-air temperature –40 85 °C (1) (2) VIL and VIH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling to VCC/2 is provided. VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of 150 mV. TIMING REQUIREMENTS over recommended ranges of supply voltage, load and operating free air temperature PARAMETER MIN TYP MAX UNIT 200 MHz PRI_REF/SEC_REF_IN REQUIREMENTS fREF_IN LVCMOS primary or secondary reference clock frequency (1) (2) tr/ tf Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of VCC dutyREF Duty cycle of PRI_REF or SEC_REF at VCC/2 0 4 40% 60% 0 2200 ns VCXO_IN, VCXO_IN REQUIREMENTS fVCXO_IN (1) (2) (3) 6 VCXO clock frequency (3) MHz At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant. fREF_IN can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC). If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid! CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 TIMING REQUIREMENTS (continued) over recommended ranges of supply voltage, load and operating free air temperature PARAMETER MIN tr/ tf Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz (4) dutyVCXO Duty cycle of VCXO clock TYP MAX 3 40% UNIT ns 60% SPI/CONTROL REQUIREMENTS (see Figure 14) fCTRL_CLK CTRL_CLK frequency tsu1 CTRL_DATA to CTRL_CLK setup time 10 20 MHz ns th2 CTRL_DATA to CTRL_CLK hold time 10 ns t3 CTRL_CLK high duration 25 ns t4 CTRL_CLK low duration 25 ns tsu5 CTRL_LE to CTRL_CLK setup time 10 ns tsu6 CTRL_CLK to CTRL_LE setup time 10 ns t7 CTRL_LE pulse width 20 tr/ tf Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC ns 4 ns 4 ns PD, RESET, HOLD, REF_SEL REQUIREMENTS tr / tf (4) Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of VCC Use a square wave for lower frequencies (< 80 MHz). DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TYP (1) MAX UNIT fVCXO = 245.76 MHz, fREF_IN = 30.72 MHz, PFD = 240 kHz, ICP = 2 mA, all outputs are LVPECL and Div-by-8 (load, see Figure 13) 210 260 mA fVCXO = 245.76 MHz, fREF_IN = 30.72 MHz, PFD = 240 kHz, ICP = 2 mA, All outputs are LVCMOS and Div-by-8 (load, 10 pF) 120 150 mA fIN = 0 MHz, VCC = 3.6 V, AVCC = 3.6 V, VCC_CP = 3.6 V, VI = 0 V or VCC 100 300 µA ±40 µA ±100 µA TEST CONDITIONS MIN OVERALL ICC_LVPECL Supply current (ICC over frequency see Figure 1 through Figure 4) ICC_LVCMOS ICCPD Power-down current IOZ High-impedance state output current for Yx outputs VO = 0 V or VCC– 0.8 V VI_REF_CP Voltage on I_REF_CP (external current path for accurate charge pump current) 12 kΩ to GND at pin D8 (BGA), pin 22 (QFN) VBB Output reference voltage VCC = 3 V – 3.6 V; IBB = –0.2 mA CO Output capacitance for Yx VCC = 3.3 V, VO = 0 V or VCC Input capacitance at PRI_REF and SEC_REF VI = 0 V or VCC, VI = 0 V or VCC Input capacitance at CTRL_LE, CTRL_CLOCK, CTRL_DATA VI = 0 V or VCC CI VO = 0 V or VCC 1.21 V VCC–1.3 V 2 pF 2.7 pF 2 LVCMOS fclk Output frequency, see and Figure 7 VIK II (1) (2) (3) (2), (3), Figure 6, Load = 5 pF to GND, 1 kΩ to VCC, 1 kΩ to GND 250 MHz LVCMOS input clamp voltage VCC = 3 V, II = –18 mA –1.2 V LVCMOS input current for CTRL_LE, CTRL_CLK, CTRL_DATA VI = 0 V or VCC, VCC = 3.6 V ±5 µA All typical values are at VCC = 3.3 V, temperature = 25°C. fclk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4). Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. 7 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IIH LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF, (see (4)) VI = VCC, VCC = 3.6 V IIL LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF, (see (4)) VI = 0 V, VCC = 3.6 V VOH High-level output voltage for LVCMOS outputs VCC = min to max, IOH = –100 µA VCC = 3 V, IOH = –6 mA VCC = 3 V, IOH = –12 mA MIN TYP (1) –15 MAX UNIT 5 µA –35 µA VCC–0.1 V 2.4 2 VCC = min to max, IOL = 100 µA 0.1 VCC = 3 V, IOL = 6 mA 0.5 VOL Low-level output voltage for LVCMOS outputs IOH High-level output current VCC = 3.3 V, VO = 1.65 V –30 mA IOL Low-level output current VCC = 3.3 V, VO = 1.65 V 33 mA tpho Phase offset (REF_IN to Y output) (5) VREF_IN = VCC/2, Y = VCC/2, see Figure 11, Load = 10 pF 1.8 ns tsk(p) LVCMOS pulse skew, see Figure 10 Crosspoint to VCC/2 load, see Figure 12 tpd(HL) Propagation delay from VCXO_IN to Yx, see Figure 10 Crosspoint to VCC/2, Load = 10 pF, see Figure 12 (PLL bypass mode) tsk(o) LVCMOS single-ended output skew, see (6) and Figure 10 All outputs have the same divider ratio 55 Outputs have different divider ratios 70 Duty cycle LVCMOS VCC/2 to VCC/2 Output rise/fall slew rate 20% to 80% of swing (load see Figure 12) VCC = 3 V, IOL = 12 mA tpd(LH) tslew-rate V 0.8 2 2.5 49% 2.4 150 ps 3 ns ps 51% 3.5 V/ns LVPECL (7) fclk Output frequency, see II LVPECL input current and Figure 5 VI = 0 V or VCC VOH LVPECL high-level output voltage Load, See Figure 13 VOL LVPECL low-level output voltage Load, See Figure 13 |VOD| Differential output voltage See Figure 9 and load, see Figure 13 500 tpho Phase offset (REF_IN to Y output) (6) VREF_IN = VCC/2 to cross point of Y, see Figure 11 –200 tpd(LH) tpd(HL) Propagation delay time, VCXO_IN to Yx, see Figure 10 Cross point-to-cross point, load see Figure 13 tsk(p) LVPECL pulse skew, see Figure 10 tsk(o) LVPECL output skew (6) tr / tf Rise and fall time CI Input capacitance at VCXO_IN, VCXO_IN Load, see Figure 13 0 1500 MHz ±20 µA VCC–1.18 VCC–0.81 V VCC–2 VCC–1.55 V mV 100 ps 640 ps Cross point-to-cross point, load see Figure 13 10 ps Load see Figure 13, all outputs have the same divider ratio 20 Load see Figure 13, outputs have different divider ratios 50 20% to 80% of VOUTPP, see Figure 9 340 490 ps 120 170 220 1.5 ps pF LVCMOS-TO-LVPECL tsk(P_C) (4) (5) (6) (7) (8) 8 Output skew between LVCMOS and LVPECL outputs, see (8) and Figure 10 Cross point to VCC/2; load, see Figure 12 and Figure 13 1.7 2 2.4 ns These inputs have an internal 150-kΩ pullup resistor. This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). The tsk(o) specification is only valid for equal loading of all outputs. Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVPECL. CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) MIN MAX UNIT PLL ANALOG LOCK IOH High-level output current VCC = 3.6 V, VO = 1.8 V –110 µA IOL Low-level output current VCC = 3.6 V, VO = 1.8 V 110 µA IOZH LOCK High-impedance state output current for PLL LOCK output (9) VO = 3.6 V (PD is set low) IOZL LOCK High-impedance state output current for PLL LOCK output (9) VO = 0 V (PD is set low) VIT+ Positive input threshold voltage VCC = min to max VCC×0.55 V VIT– Negative input threshold voltage VCC = min to max VCC×0.35 V 45 65 µA ±5 µA PHASE DETECTOR fCPmax Maximum charge pump frequency Default PFD pulse width delay ICP Charge pump sink/source current range (10) VCP = 0.5 VCC_CP ICP3St Charge pump 3-state current 0.5 V < VCP < VCC_CP– 0.5 V 100 MHz ±3 mA 10 nA CHARGE PUMP ±0.2 VCP = 0.5 VCC_CP, internal reference resistor, SPI default settings ICPA ICP absolute accuracy 10% VCP = 0.5 VCC_CP, external reference resistor 12 kΩ (1%) at I_REF_CP, SPI default settings 5% ICPM Sink/source current matching 0.5 V < VCP < VCC_CP– 0.5 V, SPI default settings IVCPM ICP vs VCP matching 0.5 V < VCP < VCC_CP– 0.5 V 2.5% 5% (9) Lock output has an 80-kΩ pulldown resistor. (10) Defined by SPI settings. TYPICAL CHARACTERISTICS LVPECL SUPPLY CURRENT vs NUMBER OF ACTIVE OUTPUTS 250 All Output Pairs Active (4 div-by-8 / 1 div-by-3) 230 ∆ For div-by-3/6 ICC − Supply Current − mA 210 190 All Output Pairs Active (div-by-8) 170 All Output Pairs Active (div-by-1) 150 VCC = 3.3 V TA = 25°C ∆ for div-by-2/4/8/16 130 One Output Pair Active (div-by-8) 110 90 ∆ For 1 Output Pair No Output Active 70 50 50 250 450 650 850 1050 1250 1450 1650 1850 2050 VCXO_IN Input Frequency − MHz G001 A. If div-by-2/4/8/16 is activated for one or more outputs, '∆ for div-by-2/4/8/16' has to be added to ICC of div-by-1. If div-by-3 or div-by-6 is activated, '∆ for div-by-2/4/8/16' and '∆ for div-by3/6' has to be added to ICC of div-by-1. Figure 1. 9 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) LVPECL DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS PDEV − Device Power Consumption − mW 750 VCC = 3.3 V TA = 25°C 650 All Output Pairs Active (4 div-by-8 / 1 div-by-3) 550 All Output Pairs Active (div-by-8) 450 All Output Pairs Active (div-by-1) One Output Pair Active (div-by-8) 350 250 150 No Output Active 50 50 250 450 650 850 1050 1250 1450 1650 1850 2050 VCXO_IN Input Frequency − MHz G002 Figure 2. LVCMOS SUPPLY CURRENT / DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS (Load = 5 pF) Icc − Supply Current − mA 200 all outputs active div−by−3 700 600 for div−by−3/6 150 all outputs active div−by−1 one output pair active div−by−1 100 500 400 300 for 1 output 50 for 1 output pair 200 100 one output active div−by−1 no output active 0 50 100 150 200 250 Output Frequency − MHz 10 A. To estimate ICC with different P-divider settings use '∆ for div-by-2/4/8/16' and '∆ for div-by-3/6' of Figure 1. B. It is not recommended to exceed power dissipation of 700 mW for the BGA package at TA 85°C. Figure 3. 0 300 PDEV − Power Device Consumption − mW 800 Vcc = 3.3V TA = 25C load = 5 pF CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) LVCMOS SUPPLY CURRENT / DEVICE POWER CONSUMPTION vs NUMBER OF ACTIVE OUTPUTS (Load = 10 pF) 900 VCC = 3.3 V TA = 25C Load = 10 pF all outputs active div−by−3 800 700 200 600 for div−by−3/6 500 150 all outputs active div−by−1 400 one output pair active div−by−1 100 300 for 1 output 50 for 1 output pair PDEV − Device Power Consumption − mW Icc − Supply Current − mA 250 200 100 one output active div−by−1 no output active 0 40 60 80 100 120 140 160 180 200 220 240 260 280 0 300 Output Frequency − MHz A. To estimate ICC with different P-divider settings use '∆ for div-by-2/4/8/16' and '∆ for div-by-3/6' of Figure 1. B. It is not recommended to exceed power dissipation of 700 mW for the BGA package at TA 85°C. Figure 4. DIFFERENTIAL LVPECL OUTPUT VOLTAGE vs OUTPUT FREQUENCY VOD − Differential Output Voltage − V 0.90 VCC = 3.3 V TA = 25°C Termination = 50 to VCC − 2 V 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 50 250 450 650 850 1050 1250 fOut − Output Frequency − MHz 1450 1650 1850 G005 Figure 5. 11 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) LVCMOS OUTPUT SWING vs FREQUENCY 3.6 VCC = 3.6 V 3.4 LVCMOS Output Swing − V 3.2 3.0 2.8 2.6 VCC = 3.3 V 2.4 VCC = 3 V 2.2 2.0 1.8 TA = 25°C Load = 5 pF (See Figure 12) 1.6 1.4 50 100 150 200 250 300 350 400 450 500 f − Frequency − MHz G006 Figure 6. LVCMOS OUTPUT SWING vs FREQUENCY 3.6 3.4 VCC = 3.6 V LVCMOS Output Swing − V 3.2 3.0 2.8 2.6 2.4 VCC = 3.3 V 2.2 VCC = 3 V 2.0 1.8 TA = 25°C Load = 10 pF (See Figure 12) 1.6 1.4 50 100 150 200 250 300 350 400 450 500 f − Frequency − MHz G007 Figure 7. 12 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) OUTPUT REFERENCE VOLTAGE (VBB) vs LOAD 4.0 VCC = 3.3 V TA = 25°C VBB − Output Reference Voltage − V 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 −5 0 5 10 15 20 25 30 35 I − Load − mA G008 Figure 8. PARAMETER MEASUREMENT INFORMATION Yx VOH VOD Yx VOL 80% 20% 0V tr VOUTpp tf T0058-01 Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time 13 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION (continued) LVPECL VCXO_IN /VCXO_IN tpd(LH) / tpd(HL); tsk(p) = | tpd(HL) − tpd(LH) | YxA LVPECL YxB YxA LVPECL YxB tsk(o)LVPECL YxA LVPECL YxB YxA LVCMOS tsk p_c LVCMOS VCXO_IN /VCXO_IN tpd(LH); tsk(p) = | tpd(HL) − tpd(LH) | YxA/B LVCMOS tsk(o)LVCMOS YxA/B LVCMOS A. Output skew, tsk(o), is calculated as the greater of: The difference between the fastest and the slowest tpd(LH)n (n = 0...4) The difference between the fastest and the slowest tpd(HL)n (n = 0...4) B. Pluse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL)) and the low-to-high (tpd(LH)) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = |tpd(HL) – tpd(LH) |. Pulse skew is sometimes refered to as pulse width distortion or duty cycle skew. Figure 10. Output Skew 14 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION (continued) VIH 50% VCC VIL REF_IN tpho LVPECL VOH YxB LVPECL VOL YxA tpho LVCMOS VOH LVCMOS VOL T0060-01 Figure 11. Phase Offset CDCM7005 1kW LVCMOS Y3 1kW 10pF S0079-01 Figure 12. LVCMOS Output Loading During Device Test 15 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION (continued) VCC ZO = 50W Yx CDCM7005 Driver LVPECL Receiver ZO = 50W Yx 50W 50W VEE VT = VCC – 2V S0078-01 Figure 13. LVPECL Output Loading During Device Test SPI CONTROL INTERFACE The serial interface of the CDCM7005 is a simple SPI-compatible interface for writing to the registers of the device and consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32-bit wide registers, which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted word must have 32 bits, starting with MSB first. Each word can be written separately. Bit 7, 8, 10, and Bit 12 to 31 of Word 3 are reserved for factory test purposes and must be filled with zeros. The transfer is initiated with the falling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE, low data can be written. The data has to be applied at CTRL_DATA and has to be stable before the rising edge of CTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, the new word is asynchronously transferred to the internal register (e.g., N, M, P, ...). Each word has to be separately transmitted by this procedure. 16 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION (continued) t4 t3 CTRL_CLK th2 tsu1 CTRL_DATA Bit31 (MSB) Bit30 Bit2 Bit1 Bit0 t7 CTRL_LE tsu5 tsu6 T0061-01 Figure 14. Timing Diagram SPI Control Interface The SPI serial protocol accepts word Write operation only. There is neither a read, acknowledge, nor a handshake operation. The following four words include the register settings of the programmable functions of the CDCM7005. It can be modified to the customer application by changing one or more bits. It comes up with a default register setting after power up or if the power down (PD) control signal is applied. The default setting is shown in column five of the following words. A low active function is shown as [0] and a high active function is shown as [1]. 17 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION (continued) Word 0 BIT (1) 18 BIT NAME DESCRIPTION/FUNCTION POWER UP CONDITION 0 C0 Register Selection 0 1 C1 Register Selection 0 2 M0 Reference Divider M Bit 0 1 3 M1 Reference Divider M Bit 1 1 4 M2 Reference Divider M Bit 2 1 5 M3 Reference Divider M Bit 3 1 6 M4 Reference Divider M Bit 4 1 7 M5 Reference Divider M Bit 5 1 8 M6 Reference Divider M Bit 6 1 Reference Divider M PIN AFFECTED BGA QFN 9 M7 Reference Divider M Bit 7 0 10 M8 Reference Divider M Bit 8 0 11 M9 Reference Divider M Bit 9 0 12 N0 VCXO Divider N Bit 0 1 13 N1 VCXO Divider N Bit 1 1 14 N2 VCXO Divider N Bit 2 1 15 N3 VCXO Divider N Bit 3 1 16 N4 VCXO Divider N Bit 4 1 17 N5 VCXO Divider N Bit 5 1 18 N6 VCXO Divider N Bit 6 1 19 N7 VCXO Divider N Bit 7 0 20 N8 VCXO Divider N Bit 8 0 21 N9 VCXO Divider N Bit 9 0 22 N10 VCXO Divider N Bit 10 0 23 N11 VCXO Divider N Bit 11 0 24 DLYM0 Reference Phase Delay M Bit 0 0 25 DLYM1 Reference Phase Delay M Bit 1 0 26 DLYM2 Reference Phase Delay M Bit 2 0 27 DLYN0 Feedback Phase Delay N Bit 0 0 28 DLYN1 Feedback Phase Delay N Bit 1 0 29 DLYN2 Feedback Phase Delay N Bit 2 0 30 MANAUT Manual or Auto Ref. Manual Reference Clock Selection [0] Automatic Reference Clock Selection [1] 0 A1, B1 36, 37 31 REFDEC Freq. Detect Reference Frequency Detection on [0], off [1] 0 C8 23 VC(X)O Divider N Progr. Delay M Progr. Delay N (1) If set to low, STATUS_REF will be in normal operation. If set to high, STATUS_REF will be high, even if no valid clock is detected (<2 MHz). This is useful for reference inputs frequencies less than 2 MHz where the frequency detection circuitry normally resets the STATUS_REF signal to low. CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Word 1 BIT BIT NAME DESCRIPTION/FUNCTION POWER UP CONDITION PIN AFFECTED BGA QFN 1 F1, G1 46, 47 For Outputs Y1A, Y1B: LVPECL = enabled [1]; LVCMOS = enabled [0]; 1 H2, H3 3, 4 OUTSEL2 For Outputs Y2A, Y2B: LVPECL = enabled [1]; LVCMOS = enabled [0]; 1 H4, H5 7, 8 5 OUTSEL3 For Outputs Y3A, Y3B: LVPECL = enabled [1]; LVCMOS = enabled [0]; 1 H6, H7 11, 12 6 OUTSEL4 For Outputs Y4A, Y4B: LVPECL = enabled [1]; LVCMOS = enabled [0]; 1 G8, F8 16,17 7 OUT0A0 Output Y0A Mode Bit 0 0 F1 46 8 OUT0A1 Output Y0A Mode Bit 1 0 F1 46 0 C0 Register Selection 1 1 C1 2 OUTSEL0 Register Selection 0 For Output Y0A, Y0B: LVPECL = enabled [1]; LVCMOS = enabled [0]; 3 OUTSEL1 4 Output (Yx) Signaling Selection Output Y0 Mode 9 OUT0B0 Output Y0B Mode Bit 0 0 G1 47 10 OUT0B1 Output Y0B Mode Bit 1 0 G1 47 11 OUT1A0 Output Y1A Mode Bit 0 0 H2 3 12 OUT1A1 Output Y1A Mode Bit 1 0 H2 3 13 OUT1B0 Output Y1B Mode Bit 0 0 H3 4 14 OUT1B1 Output Y1B Mode Bit 1 0 H3 4 15 OUT2A0 Output Y2A Mode Bit 0 0 H4 7 16 OUT2A1 Output Y2A Mode Bit 1 0 H4 7 17 OUT2B0 Output Y2B Mode Bit 0 0 H5 8 18 OUT2B1 Output Y2B Mode Bit 1 0 H5 8 19 OUT3A0 Output Y3A Mode Bit 0 0 H6 11 20 OUT3A1 Output Y3A Mode Bit 1 0 H6 11 21 OUT3B0 Output Y3B Mode Bit 0 0 H7 12 22 OUT3B1 Output Y3B Mode Bit 1 0 H7 12 23 OUT4A0 Output Y4A Mode Bit 0 0 G8 16 24 OUT4A1 Output Y4A Mode Bit 1 0 G8 16 25 OUT4B0 Output Y4B Mode Bit 0 0 F8 17 26 OUT4B1 Output Y4B Mode Bit 1 0 F8 17 27 SREF Displays the status of the reference clock at the STATUS_REF output [0] 0 C8 23 0 D8, A8 22, 25 Output Y1 Mode Output Y2 Mode Output Y3 Mode Output Y4 Mode Status Ref. Displays the selected clock (high for PRI_REF and low for SEC_REF clock) at the STATUS_REF output [1] 28 (1) SXOIREF Status VCXO or I_REF_CP Selects STATUS_VCXO [0] Selects I_REF_CP [1] which enable external reference resistor used for charge pump current and analog PLL lock detect output current. 29 ADLOCK Analog or Digital Lock Selects Digital PLL_LOCK [0] Selects Analog PLL_LOCK [1] 0 A8 25 30 90DIV4 90 degree shift div-4 90 degree output phase shift in div-4 mode on [1]; off [0] (1) 0 Yx Yx 31 90DIV8 90 degree shift div-8 90 degree output phase shift in div-8 mode on [1]; off [0] (1) 0 Yx Yx The P 16-Div has to be selected to obtain the 90 degree phase shift. If bit 30 or bit 31 is set, the Div-by-16 mode is no longer available. The outputs are switched in pairs. Only one bit can be set at a time. If both bits set to [1] at the same time, no 90 degree phase shift mode is selected (equal to off-mode setting). 19 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Word 2 BIT BIT NAME DESCRIPTION/FUNCTION POWER UP CONDITION PIN AFFECTED BGA QFN 0 C0 Register Selection 0 1 C1 Register Selection 1 2 CP_DIR Determines in which direction CP current regulates (Reference Clock leads to Feedback Clock – see Figure 23) 0 A4 31 Preset charge pump output voltage to VCC_CP/2, on [1], off [0] 0 A4 31 CP Current Setting Bit 0 0 A4 31 CP Direction – positive CP output current [0]; – negative CP output current [1]; 20 3 PRECP 4 CP0 5 CP1 CP Current Setting Bit 1 1 A4 31 6 CP2 CP Current Setting Bit 2 0 A4 31 7 CP3 CP Current Setting Bit 3 1 A4 31 8 PFD0 PFD Pulse Width PFD Pulse Width PFD Bit 0 0 A4 31 PFD Pulse Width PFD Bit 1 0 A4 31 FB_MUX Feedback MUX Select Bit 0 1 CP Current 9 PFD1 10 FBMUX0 11 FBMUX1 Feedback MUX Select Bit 1 0 12 FBMUX2 Feedback MUX Select Bit 2 1 13 Y0MUX0 Output Y0x Select Bit 0 1 F1, G1 46, 47 14 Y0MUX1 Output Y0x Select Bit 1 0 F1, G1 46, 47 15 Y0MUX2 Output Y0x Select Bit 2 1 F1, G1 46, 47 16 Y1MUX0 Output Y1x Select Bit 0 1 H2, H3 3, 4 17 Y1MUX1 Output Y1x Select Bit 1 0 H2, H3 3, 4 18 Y1MUX2 Output Y1x Select Bit 2 1 H2, H3 3, 4 19 Y2MUX0 Output Y2x Select Bit 0 1 H4, H5 7, 8 20 Y2MUX1 Output Y2x Select Bit 1 0 H4, H5 7, 8 21 Y2MUX2 Output Y2x Select Bit 2 1 H4, H5 7, 8 22 Y3MUX0 Output Y3x Select Bit 0 1 H6, H7 11, 12 23 Y3MUX1 Output Y3x Select Bit 1 0 H6, H7 11, 12 24 Y3MUX2 Output Y3x Select Bit 2 1 H6, H7 11, 12 25 Y4MUX0 Output Y4x Select Bit 0 1 G8, F8 16, 17 26 Y4MUX1 Output Y4x Select Bit 1 0 G8, F8 16, 17 27 Y4MUX2 Output Y4x Select Bit 2 1 G8, F8 16, 17 28 PD Power Down mode on [0], off [1] 1 Yx Yx 29 RESHOL RESET or HOLD Pin definition: RESET [0] or HOLD [1] 0 H8 14 30 RESET Resets all dividers [0] - (equal to RESET pin function) 1 31 HOLD 3-state charge pump [0] - (equal to HOLD pin function) 1 A4 31 Y0_MUX Y1_MUX Y2_MUX Y3_MUX Y4_MUX CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Word 3 BIT BIT NAME DESCRIPTION/FUNCTION 0 1 Lock Window (2) PIN AFFECTED BGA QFN 1 A8 25 Lock-detect window Bit 1 0 A8 25 Number of coherent lock events Bit 0 0 A8 25 Number of coherent lock events Bit 1 1 A8 25 Cycle slip mode only for out-of-lock detection on [1] or off [0] (1) 0 A8 25 Register selection 1 Register selection 1 Lock-detect window Bit 0 2 LOCKW 0 3 LOCKW 1 4 LOCKC0 5 LOCKC1 6 CSLIP 7 RES RESERVED 0 RES RES 8 RES RESERVED 0 RES RES 9 HOLDF Enables the frequency hold-over function on [1], off [0] 0 RESERVED 0 RES RES HOLD function always activated [1]; (2) Triggered by analog PLL lock detect outputs [0] (if analog PLL Lock signal is set then HOLD is activated; if analog PLL lock signal is reset then HOLD is de-activated). 0 Lock Cycles Cycle Slip HOLD Function 10 (1) POWER UP CONDITION 11 HOLDTR HOLD Trigger Condition 12 RES RESERVED 0 RES RES 13 RES RESERVED 0 RES RES 14 RES RESERVED 0 RES RES 15 RES RESERVED 0 RES RES 16 RES RESERVED 0 RES RES 17 RES RESERVED 0 RES RES 18 RES RESERVED 0 RES RES 19 RES RESERVED 0 RES RES 20 RES RESERVED 0 RES RES 21 RES RESERVED 0 RES RES 22 RES RESERVED 0 RES RES 23 RES RESERVED 0 RES RES 24 RES RESERVED 0 RES RES 25 RES RESERVED 0 RES RES 26 RES RESERVED 0 RES RES 27 RES RESERVED 0 RES RES 28 RES RESERVED 0 RES RES 29 RES RESERVED 0 RES RES 30 RES RESERVED 0 RES RES 31 RES RESERVED 0 RES RES If Cycle Slip mode only for out-of-lock detection is on, the selected lock detect window is valid for lock detect. Independent from this, out of lock is detected if a cycle slip occurs. HOLD function always activated is recommended for test purposes only. 21 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 FUNCTIONAL DESCRIPTION OF THE LOGIC Reference Divider M (Word 0) (3) M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Div by 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 1 1 4 1 1 1 1 128 Default • • • 0 0 0 1 1 1 Yes • • • (3) 1 1 1 1 1 1 1 1 0 1 1022 1 1 1 1 1 1 1 1 1 0 1023 1 1 1 1 1 1 1 1 1 1 1024 If the divider value is Q, then the code will be the binary value of (Q–1). VC(X)O Feedback Divider N (Word 0) (1) N11 N10 N0 N8 N7 N6 N5 N4 N3 N2 N1 N0 Div by 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 2 0 0 0 0 0 0 0 0 1 0 1 0 3 0 0 0 0 0 0 0 0 1 1 1 1 4 1 1 1 1 1 128 Default • • • 0 0 0 0 0 1 1 • • • (1) 22 1 1 1 1 1 1 1 1 1 1 0 1 4094 1 1 1 1 1 1 1 1 1 1 1 0 4095 1 1 1 1 1 1 1 1 1 1 1 1 4096 If the divider value is Q, then the code will be the binary value of (Q–1). Yes CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Output Mode Selection for LVCMOS and LVPECL Outputs: Y0A, Y0B, Y1A …Y4B (Word 1) (1) OUTSELx OUTxB1 OUTxB0 LVCMOS [YxB] OUTxA1 OUTxA0 0 0 0 0 0 Active 0 0 Active 1 3-state 0 1 3-state 0 1 0 Inverting 1 0 Inverting 0 1 1 Low 1 1 Low OUTSELx OUTxB1 OUTxB0 OUTxA1 OUTxA0 LVCMOS [YxA] Default 1 x x x 0 Active Yx 1 x x x 1 3-state LVCMOS LVPECL (1) LVCMOS [YxA] Default If the differential LVPECL output e.g. Y0A:Y0B is selected (bit 2 of word 1), then only bit 7 of word 1 defines the output mode for Y0A:Y0B. The settings of bit 8, bit 9, and bit 10 of word 1 are therefore not relevant to the Y0A:Y0B. This applies for the other LVPECL outputs as well. Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment (Word 0) (1) (1) DLYM2 / DLYN2 DLYM1 / DLYN1 DLYM0 / DLYN0 Phase Offset Default 0 0 0 0 ps Yes 0 0 1 ±160 ps 0 1 0 ±320 ps 0 1 1 ±480 ps 1 0 0 ±830 ps 1 0 1 ±1130 ps 1 1 0 ±1450 ps 1 1 1 ±1750 ps If Progr. Delay M is set, all Yx outputs are lagging to the reference clock according to the value set. If Progr. If Delay N is set; all Yx outputs are leading to the reference clock according to the value set. Above are typical values at VCC = 3.3 V, Temp = 25°C, PECL-output relate to Div4 mode. PFD Pulse Width Delay (Word 2) (1) (2) PFD1 (1) PFD0 (1) PFD Pulse Width (1) (2) Default (1) 0 0 1.5 ns Yes 0 1 3 ns 1 0 4.5 ns 1 1 6 ns The PFD pulse width delay gets around the dead zone of the PFD transfer function and reduces phase noise and reference spurs. Typical values at V = 3.3 VCC, Temp = 25°C . Lock-Detect Window (Word 3) (1) (2) LOCKW1 LOCKW0 Phase-Offset at PFD Input (1) Default 0 0 3.5 ns Yes 0 1 8.5 ns 1 0 18.5 ns 1 1 Cycle slip (2) Typical Values at VCC = 3.3 V, Temp = 25°C. Cycle slip occurs when the phase shift at the PFD is greater than one period of the frequency. It is a complete (integer number) cycle jump, i.e., cause by a loss-of-lock of the PLL. 23 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Number of Successive Lock Events Inside the Lock Detect Window (Word 3) (1) LOCKC1 (1) LOCKC0 (1) No. of Successive Lock Events (1) 0 0 1 0 1 16 1 0 64 1 1 256 Default (1) Yes This does not apply to Out-of-Lock condition. Charge Pump Current (Word 2) CP3 CP2 CP1 CP0 Typical Charge Pump Current 0 0 0 0 0 µA (3-state) 0 0 0 1 200 µA 0 0 1 0 400 µA 0 0 1 1 600 µA 0 1 0 0 800 µA 0 1 0 1 1 mA 0 1 1 0 1.2 mA 0 1 1 1 1.4 mA 1 0 0 0 1.6 mA 1 0 0 1 1.8 mA 1 0 1 0 2.0 mA 1 0 1 1 2.2 mA 1 1 0 0 2.4 mA 1 1 0 1 2.6 mA 1 1 1 0 2.8 mA 1 1 1 1 3 mA Default Yes FB_MUX Selection (Word 2) FBMUX2 FBMUX1 FBMUX0 Selected VC(X)O Signal for the Phase Discriminator 0 0 0 Div by 1 0 0 1 Div by 2 0 1 0 Div by 3 0 1 1 Div by 4 1 0 0 Div by 6 1 0 1 Div by 8 1 1 0 Div by 16 (1) 1 1 1 Div by 8 (1) Default Yes This divider setting depends on the selected P-divider mode for the “Div-by-16” divider. In the default mode (after power up), Div-by-16 is selected. But if bit 30 or bit 31 of word 1 is set to [1], then the Div-by-4 and 90 degree phase shift or Div-by-8 and 90 degree phase shift is selected. Yx_MUX – Output Divider Selection for Y0, Y1, Y2, Y3, Y4 (Word 2) 24 YxMUX2 YxMUX1 YxMUX0 Selected Divided V(C)XO Signal for the Yx Outputs 0 0 0 Div by 1 0 0 1 Div by 2 0 1 0 Div by 3 0 1 1 Div by 4 1 0 0 Div by 6 1 0 1 Div by 8 Default all Yx CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 YxMUX2 YxMUX1 YxMUX0 Selected Divided V(C)XO Signal for the Yx Outputs 1 1 0 Div by 16 (1) 1 1 1 Div by 8 (1) Default This divider setting depends on the selected P-divider mode for the “Div-by-16” divider. In the default mode (after power up), Div-by-16 is selected. But if bit 30 or bit 31 of word 1 is set to [1], then the Div-by-4 and 90 degree phase shift or Div-by-8 and 90 degree phase shift is selected. FEATURE DESCRIPTION Automatic/Manual Reference Clock Switching The CDCM7005 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by the dedicated SPI register bit (Word 0, Bit 30). In the manual mode, the external REF_SEL signal selects one of the two input clocks: REF_SEL [1] -> primary clock is selected REF_SEL [0] -> secondary clock is selected In the automatic mode, the primary clock is selected by default even if both clocks are available. In case the primary clock is not available or fails, then the input switches to the secondary clock as long until the primary clock is back. Figure 15 shows the automatic clock selection. 1 PRI_REF SEC_REF 1 2 3 4 2 Internal Reference Clock STATUS_REF PRI_SEC_CLK Primary Clock Secondary Clock Primary Clock T0062-01 NOTE: PRI_REF is the preferred clock input. Figure 15. Behavior of STATUS_REF and PRI_SEC_CLK In the automatic mode, the frequencies of both clock signals have to be similar, but may differ by up to 20%. The phase of the clock signal can be any. The clock input circuitry is design to suppress glitches during switching between the primary and secondary clock in the manual and automatic mode. This avoids an undefined switching of the following circuitries. The phase of the output clock slowly follows the new input phase. There will be no phase-jump at the output. How quick the phase adjustment is done depends on the selected loop parameter, i.e., at a loop bandwidth of <100 Hz; the phase adjustment can take several ms. There is no phase build-out function supported (like in SONET/SDH applications). 25 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 1 PRI_REF 1 SEC_REF 2 3 4 2 Internal Reference Clock PRI_SEC_CLK Secondary Clock Primary Clock Primary Clock Yx Output T0063-01 Figure 16. Phase Approach of Output to New Reference Clock PLL Lock for Analog and Digital Detect The CDCM7005 supports two PLL lock indications: the digital lock signal or the analog lock signal. Both signals indicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition. PLL Lock/Out-of-Lock Definition The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD (phase frequency detect) are inside a predefined lock detect window, or if no cycle-slip appears, for a pre-defined number of successive clock cycles. The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window or if a cycle-slip appears. Both, the lock detect window and the number of successive clock cycles are user definable (Word 3, Bit 2-6). Selected REF at PFD (clock fed through M Divider and M Delay) t(lockdetect) VCXO_IN at PFD (clock fed through N Divider and N Delay) T0064-01 Figure 17. Lock Detect Window The lock detect window describes the maximum allowed time difference for lock detect between the rising edge of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock detect window if there is a phase displacement of more than +0.5 × t(lockdetect) or -0.5 x t(lockdetect). Digital vs Analog Lock Figure 18 and Figure 19 show the circuit for the digital and analog lock. The analog lock operates with an external load capacitor. 26 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of lock until a stable lock is detected. A single low-to-high step can be reached with a wide lock detect window and high number of successive clock cycles. PLL_LOCK returns to out of lock if just one cycle is outside the lock detect window or a cycle slip occurs. VOut CDCM7005 Power_Down PLL_LOCK Output Lock_Out Digital Lock Detection Lock 80kW 5pF Out-of-Lock t Lock_In Vhigh = 0.55 VCC Vlow = 0.35 VCC S0080-01 Figure 18. Digital Lock-Detect When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110-µA current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but jittering of PLL_LOCK will be suppressed in case of digital lock. The time PLL_LOCK needs to return to out of lock depends on the level of VOut, when the current source starts to unload the external capacitor. VCC 100mA (Lock) Out-of-Lock PLL_LOCK Output Power_Down CDCM7005 Lock VOut Lock_Out 80kW 100mA (Out-of-Lock) C 5pF VOut = 1/C ´ I ´ t t Lock_In Vhigh = 0.55 VCC Example: for I = 110mA, C = 10nF, VCC = 3.3 V, and Vhigh = Vout = 0.55 ´ Vcc = 1.8V ³ t = 164ms Vlow = 0.35 VCC S0081-01 Figure 19. Analog Lock-Detect Differential LVPECL Outputs and Single-Ended LVCMOS Outputs The CDCM7005 supports up to 5 × LVPECL outputs or 10 × LVCMOS/LVTTL outputs or any combination of these. The single-ended LVCMOS outputs are arranged in pairs which mean both outputs of a LVCMOS pair have the same frequency but can separately be disabled or inverted. The power up output arrangement is five LVPECL (default setting). 27 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 The LVPECL outputs are designed to terminate in to a 50-Ω load to VCC– 2 V. The LVCMOS outputs supports the standard LVCMOS load (see Figure 12). The LVPECL and LVCMOS outputs can be enabled (normal operation) or disabled (3-state). In addition, the output phase can be shifted by 90 degrees when using the additional div-by-4 or div-by-8 mode of the P16-Div (see Figure 20). In the default mode (after power up), the div-by-16 mode of the P16-Div is active. To change it to a 90 degree phase shift, bit 30 or bit 31 of word 1 has to be programmed accordingly. The P 16-Div has to be selected via the dedicated YxMUX to obtain the 90 degree phase shift. The outputs are switched in pairs. When selecting the 90 degree phase shift mode, the div-by-16 functions will no longer be available. The 90 degree phase shifted signal is lagging to the non-shifted signal. ÷1 ÷2 ÷3 ÷4 VCXO_IN VCXO_IN PECL Input ÷6 ÷ /88 ÷4 90o ÷8 90o ÷ 16 P16-Div P Divider B0058-01 Figure 20. 90 Degree Phase Shift Option of P-Divider The following diagram shows the LVCMOS and LVPECL output signal when 90 degree phase shift is on. Reference Clock VCXO Clock Y-Output div4 90 deg 90 deg Y-Output div4 (90 deg shift) Y-Output div8 90 deg 90 deg Y-Output div8 (90 deg shift) LVCMOS Outputs LVPECL Outputs T0065-01 Figure 21. Output Switching Diagram In addition, the LVCMOS supports disabled-to-low and 180 degree output phase shift for each output individually. When selecting the 180 degree phase shift together with the 90 degree phase shift, the respective outputs has a total phase shift of 270 degree (see Table 2). 28 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Table 2. LVCMOS Phase Shift Options Phase P-Divider 180°Phase-Shift P16-Div - Function 0° Any P-Divider No div-by-16 90° P16-Div No div-by-4 or div-by-8 180° Any P-Divider Yes div-by-16 270° P16-Div Yes div-by-4 or div-by-8 If the P16-Div is selected by the FB_MUX and div-by-4 or div-by-8 is active, the 90 degree phase shifted clock will be synchronized to PRI_REF or SEC_REF. This means all outputs Yxx, which are switched to div-by-4 or div-by-8, are in phase to PRI_REF or SEC_REF. All other outputs are 90 degree phase shifted with leading phase. Frequency Hold-Over Mode The HOLD function is a useful feature which helps the designer to improve the system reliability. The HOLD function holds the output frequency in case the input reference clock fails or is disrupted. During HOLD, the charge pump is switched off (3-state) freezing the last valid output frequency. The hold function will be released after a valid reference clock is back. For proper HOLD function, the analog PLL lock detect mode has to be active. The following register settings are involved with the HOLD function: • Lock Detect Window (Word 3, Bit 2, 3, 6): Defines the window in ns inside the lock is valid. The size is 3.5 ns, 8.5 ns, 18.5 ns, or a complete cycle-slip. Lock is set if reference clock and the feedback clock are inside this predefined lock-detect window for a pre-selected number of successive cycles or if a cycle-slip no longer occurs. • Out-of-Lock: Defines the out-of-lock condition: If the reference clock and the feedback clock at the PFD are outside the predefined Lock Detect Window or if a cycle-slip occurs. • Cycle-Slip (Word 3, Bit 6): Cycle-slip occurs when the phase shift at the PFD is greater than one period of the frequency. It is a complete (integer number) cycle jump, i.e. caused by an out-of-lock of the PLL. Cycle-slip is equivalent to the PLL pull-in time. • Number of Clock Cycles (Word 3, Bit 4, 5): Defines the number of successive PFD cycles which have to occur inside the lock window to set Lock detect. This applies not for out-of-lock condition. • Hold-Function (Word 3, Bit 9): Selects HOLD function (see more details below). • Hold-Trigger (Word 3, Bit 11): Defines whether the HOLD function is always activated (Bit 11 = [1]) or whether it is dependent on the state of the analog PLL lock detect output (Bit 11 = [0]). In the latter case, HOLD is activated, if lock is set (high) and de-activated if Lock is reset (low). • Analog PLL Lock Detect (Word 1, Bit 29): Analog lock output charges or discharges an external capacitor with every valid lock cycle. The time constant for Lock detect can be set by the value of the capacitor. The CDCM7005 supports two types of HOLD functions, one external controllable HOLD mode and one internal mode, HOLD. With the external HOLD function the charge pump can directly be switched into 3-state (pin H8 [BGA] or pin 14 [QFN] can be programmed for HOLD [Word 2, Bit 29]). This function is also available via SPI register (Word 2, Bit 31). If logic low is applied to the HOLD pin, the charge pump will be switched to 3-state. After the HOLD pin is released, the charge pump is switched back in to normal operation with the next valid reference clock cycle at PRI_REF or SEC_REF and the next valid feedback clock cycle at the PFD. During HOLD, the P divider and all outputs Yx are at normal operation. HOLD-Over-Function: The PLL has to be in lock to start the HOLD function. It switches the charge pump in to 3-State when an out-of-lock event occurs. It leaves the 3-state charge pump state when the reference clock is back. Then it starts a locking sequence of 64 cycles before it goes back to the beginning of the HOLD-over loop. The dedicated looking sequence and a digital phase alignment enable a fast lock. 29 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Start PLL Out-of-Lock? Frequency Hold-Over Function works in combination with the Analog Lock-Detect function only! No PLL is out-of-lock if the phase difference of Reference Clock and Feedback Clock at PFD are outside the predefined Lock-Detect-Window or if a Cycle-Slip occurs. Yes PLL-Lock Output Set? No (The ‘PLL-Lock Output Set?’ enquiry can be bypassed by setting the HOLDTR bit to [1] (Word 3, Bit 11) Yes 3-State Charge-Pump Reference Clock Back? PLL has to be in LOCK to start HOLD-Function. (The Analog Lock output is not reset by the first Out-ofLock event. It stays ‘High’ depending on the analog time delay (output C-load). The time delay must be long enough to assure proper HOLD function) Charge-Pump is switched into 3-State. P-divider and Yx output are at normal operation. No The Charge-Pump remains in 3-State until the Reference Clock is back. The 1st valid Reference Clock at the PFD releases the Charge-Pump. Yes 64 PFD Lock-Cycles The PLL acquire 64 lock cycles to phase align to the input clock. F0004-01 Figure 22. Frequency HOLD-Over Function Charge Pump Preset to VCC_CP/2 The preset charge pump to VCC_CP/2 is a useful feature to quickly set the center frequency of the VC(X)O after powerup or reset. The adequate control voltage for the VC(X)O will be provided to the charge-pump output by an internal voltage divider of 1 kΩ/1 kΩ to VCC_CP and GND (VCC_CP/2). This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) or OBSAI (Open Base Station Architecture Initiative). The preset charge pump to VCC_CP/2 can be set and reset by SPI register (word 2, bit 3). This feature must be disabled for PLL locking. 30 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 Charge Pump Current Direction The direction of the charge pump (CP) current pulse can be changed by the SPI register (word 2, bit 2). It determines in which direction the CP current regulates (reference clock leads to feedback clock). Most applications use the positive CP output current (power-up condition) because of the use of a passive loop filter. The negative CP current is useful when using an active loop filter concept with inverting operational amplifier. Figure 23 shows the internal PFD signal and the corresponding CP current. PRI_REF or SEC_REF Clock Fed Through the M Divider and Delay VCXO_IN Clock Fed Through the N Divider and Delay V(PFD1) (Internal Signal) 0V PFD Pulse Width Delay PFD Pulse Width Delay V(PFD2) (Internal Signal) VCC CP_DIR (Bit 2 of Word 2 = 0, Default State) CP_DIR (Bit 2 of Word 2 = 1) T0076-01 NOTE: The purpose of the PFD pluse width delay is to improve spurious suppression. Figure 23. Charge Pump Current Direction (VCXO and VCO Support) 31 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 APPLICATION INFORMATION Phase Noise Reference Circuit Phase Noise Reference Circuit (See the EVM) VCXO Low-Pass Filter 245.76MHz Gain = 21.3kHz/V R2 160W V_CTRL PECL_OUT_B PECL_OUT C3 100nF CDCM7005 PRI_REF R1 4.7kW CTRL_LE CTRL_DATA CTRL_CLK SPI VOC R 130W VOC R 130W C2 100nF CP_OUT C1 22mF PLL_LOCK Measurement Equipment STATUS_REF 10nF STATUS_VCXO VCXO_IN YnA VCXO_IN YnB 10nF R 82W R 82W R 150W R 150W R 50W R 50W S0082-01 Figure 24. Typical Applications Diagram With Passive Loop Filter 32 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 APPLICATION INFORMATION (continued) Phase Noise Performance PARAMETER (1) REF_IN PHASE NOISE AT 30.72 MHz TEST CONDITIONS VCXO PHASE NOISE AT 245.76 MHz Yx PHASE NOISE AT 30.72 MHz LVCMOS LVPECL TYP (2) TYP (2) UNIT phn10 Phase noise at 10 Hz –109 –75 –104 –100 dBc/Hz phn100 Phase noise at 100 Hz –125 –97 –116 –116 dBc/Hz phn1k Phase noise at 1 kHz –134 –117 –140 –140 dBc/Hz phn10k Phase noise at 10 kHz –136 –138 –153 –152 dBc/Hz phn100k Phase noise at 100 kHz –138 –148 –156 –153 dBc/Hz phn1Mk Phase noise at 1 MHz –144 –148 –156 –153 dBc/Hz phn10M Phase noise at 10 MHz –144 –148 –156 –153 dBc/Hz Y = 30.72 MHz; fPFD = 200 kHz, Loop BW = 20 Hz, Feedback Divider = 8 x 128 (N x P), fREF_IN = 30.72 MHz, M-Divider = 128, ICP = 2 mA PLL Stabilization Time tstabi (2) (3) Y = 30.72 MHz, fPFD = 200 kHz, Loop BW = 20 Hz, Feedback Divider = 8 x 128 (N x P), fREF_IN = 30.72 MHz, M-Divider = 128, ICP = 2 mA 400 ms Output phase noise is dependent on the noise of the REF_IN clock and VCXO clock noise floor. The phase noise performance of the BGA and the QFN package is equal. The phase noise measurements were taken with the CDCM7005 EVM and CDCM7005 SPI default settings. The typical stabilization time is based on the above application example. The stabilization criterion was a stable high level of PLL_LOCK. For further explanations, as well as phase noise/jitter test results using various VCXOs, see application note SCAA067. −70 Ref_Clk −80 VCXO −90 LPF CDCM7005 Phase-Noise Analyzer E5052A VXCO 245.76MHz (581fs) −100 L(f) − dB (1) PLL stabilization time (3) CDCM7005 in PLL−Closed Loop CDCM7005 EVM REF_IN: AgilentE8257C−61.44MHz VCXO: Toyocom TCO−2111 245.76MHz CDCM7005 Out is Y0A: 61.44MHz Loop bandwidth ~ 30Hz Date: 30. Mar 2005 −110 Phase Jitter (rms) − 1kHz − 10MHz −120 −140 LVCMOS 61.44MHz (230fs) LVPECL 61.44MHz (282fs) −130 Input−Clk 61.44MHz (769fs) −150 −160 10 100 1k 10k 100k 1M 10M f − Frequency − Hz G009 Figure 25. Phase Noise (61.44-MHz REF_IN and 61.44-MHz Output Frequency) 33 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 In-Band Noise Performance PARAMETER TEST CONDITIONS pnin-band In-band phase noise test conditions pnf400 Phase noise floor at 400 kHz fPFD, in-band noise – 20log(feedback div) (1) pnf1 Phase noise floor at 1 Hz fPFD, in-band noise – 20log(feedback div) – 10log(fPFD) (2) (1) (2) MIN Y = 900 MHz, fPFD = 400 kHz, Loop BW = 27 kHz, Feedback Divider = 8 x 282 (N x P), fREF_IN = 10 MHz; M-Divider = 25, ICP = 3 mA TYP MAX UNIT –95 dBc/Hz –162 dBc/Hz –218 dBc/Hz The synthesizer phase noise floor can be estimated by measuring the in-band noise at the output of the CDCM7005 and subtracting 20log(Feedback Divider) N (in case of CDCM7005 it is the N+P divider). The calculated phase noise floor still based on the PFD update frequency, in the above specification, is 400 kHz. The in-band noise can also be normalized to a comparison frequency of 1 Hz. The resulting phase noise floor is: pnfloor = PNmeasured - 20log(N+P) - 10log(fPFD) where: pnNfloor = normalized phase noise floor in dBc/Hz PNmeasured = in-band phase noise measurement in dBc/Hz 20log(N+P) = divider ratio of feedback loop 10log(fPFD) = PFD update frequency in Hz APPLICATION INFORMATION ON THE CLOCK GENERATION FOR INTERPOLATING DACS WITH THE CDCM7005 The CDCM7005, with its specified phase noise performance, is an ideal sampling clock generator for high speed ADCs and DACs. The CDCM7005 is especially of interest for the new high speed DACs, which have integrated interpolation filter. Such DACs achieve sampling rates up to 500 MSPS. This high data rate can typically not be supported from the digital side driving the DAC (e.g., DUC, digital up-converter). Therefore, one approach to interface the DUC to the DAC is the integration of an interpolation filter within the DAC to reduce the data rate at the digital input of the DAC. In 3G systems, for example, a common sampling rate of a high speed DAC is 491.52 MSPS. With a four times interpolation of the digital data, the required input data rate results into 122.88 MSPS, which can be supported easily from the digital side. The DUC GC5016, which supports up to four WCDMA carriers, provides a maximum output data rate of 150 MSPS. An example is shown in Figure 26, where the CDCM7005 supplies the clock signal for the DUC/DDC and ADC/DAC. GC5016 RF To BB I ADS5423 DDC THS4509 LNA 14-Bit ADC Duplexer IF1 Q TRF3750 (PLL) 61.44MHz 3.84 MHz LO1 CDCM7005 VCXO 491.52 MHz 122.88 MHz From BB I 122.88 MHz FIR FIR 491.52 MHz 16-Bit DAC PA DUC FIR Q FIR S 16-Bit DAC 0 GC5016 DAC5687 90 TRF3702 LO1 (PLL) B0064-01 Figure 26. CDCM7005 as a Clock Generator for High Speed ADCs and DACs 34 CDCM7005 www.ti.com SCAS793A – JUNE 2005 – REVISED JUNE 2005 The generation of the two required clock signals (data input clock, clock for DAC) for such an interpolating DAC can be done in different ways. The recommended way is to use the CDCM7005, which generates the fast sampling clock for the DAC from the data input clock signal. The DAC5687 demands that the edges of the two input clocks must be phase aligned within ±500 ps for latching the data properly. This phase alignment is well achieved with the CDCM7005, which assures a maximum skew of 70 ps of the different different outputs to each other. AC-Coupled Interface to ADC/DAC Another advantage of this clock solution is that the ADC or DAC can be driven directly in an ac-coupling interface as shown in Figure 27, with an external termination in a differential configuration. There is no need for a transformer to generate a differential signal from a single-ended clock source. 83 VCC CDCM7005 LVPECL Driver 130 150 YxA VCC 83 DAC 130 150 YxB Figure 27. Driving DAC or ADC With PECL Output of the CDCM7005 35 PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCM7005RGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCM7005RGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCM7005ZVA ACTIVE BGA ZVA 64 348 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR CDCM7005ZVAR ACTIVE BGA ZVA 64 1000 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR CDCM7005ZVAT ACTIVE BGA ZVA 64 250 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPBG281 – MAY 2002 ZVA (S–PBGA–N64) PLASTIC BALL GRID ARRAY 8,10 SQ 7,90 5,60 TYP 0,80 0,40 H G 0,80 F E D C 0,40 B A1 Corner A 1 2 3 4 5 6 7 8 Bottom View 0,75 0,65 1,40 MAX Seating Plane 0,53 0,43 0,08 0,41 0,31 0,12 4204388/A 04/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Mico Star BGA configuration. D. This package is lead–free. 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