STMICROELECTRONICS TDA7501TR

TDA7501
Line driver for digital car radio
Signal processor (DSPLD)
Features
■
■
■
Inputs:
– Quasi differential stereo input for CD
– Differential stereo inputs for phone,
navigation, FM, AM
– Single-ended input for cassette- four
independent input multiplexer and gain
stages
– Envelope-detector for AM noise-blanking
– Mixing of phone and navigation
– DC connection to DSP
– Dual MPX inputs
Outputs:
– 6 Output channels with independent
volume control
– 4 Main output channels with additional
input selector for phone and/or navigation
or CD
– Outputs level up to 4V rms
– AC connection from DSP
Digital control:
– SPI bus or I2C bus interface (selectable)
– Direct mute for the output stages and/or
high impedance mpx mute
LQFP44
Description
The line driver handles all analog input and output
signals for the digital car radio signal processor
TDA7501. The device contains four independent
input multiplexers to select the sources for the
DSP's four AD converters. Four additional gain
stages allow an adaptation to run the ADCs in
best S/N condition.
The six outputs have independent volume stages
with a large dynamic range. Using a 12V supply
the outputs are able to drive up to 4Vrms .
Order codes
Part number
Package
Packing
TDA7501
LQFP44 (10 x 10 x 1.4 mm)
Tray
TDA7501TR
LQFP44 (10 x 10 x 1.4 mm)
Tape and Reel
January 2007
Rev 5
1/29
www.st.com
1
Contents
TDA7501
Contents
1
Block diagram and pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Description of the input part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
3.1
Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Dual MPX mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3
Additional quasi differential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4
Transfer function of the AM/FM level inputs . . . . . . . . . . . . . . . . . . . . . . . 12
Description of the output part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
Overall gain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Speaker (linedriver) outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reference concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
Dual supply mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Single supply mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
SPI bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1
8
I2C bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1
9
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Software specification for both modes . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.1
Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.2
Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.3
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
TDA7501
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Switching characteristics (SPI mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input selector 1L..3R, bits D7 ..D3 (subaddresses 0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input selector 1L, bits D2 ..D0 (subaddresses 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input selector 1R, bits D2 ..D0 (subaddresses 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input selector 2L, bits D2 ..D0 (subaddresses 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input selector 2R, bits D2 ..D0 (subaddresses 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Phone navigation (subaddress 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Mode select (subaddress 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Configuration (subaddress 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output selector (subaddress 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Volume speaker outputs (subaddresses 8...13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FM level range (subaddress 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures
TDA7501
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
4/29
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Input part. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Quasi differential input-stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mono differential input-stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Differential input-stage for AM/FM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram Dual MPX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Additional quasi differential input simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AM/FM level inputs transfer function (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output part. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Level diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Speaker (Linedriver) outputs simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reference voltage generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing diagram for the SPI bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timing diagram for switching characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Test board diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LQFP44 (10x10) mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 27
TDA7501
Block diagram and pin connections
OUT2R
ADCVDDREF
IN1L
IN1R
IN2L
IN2R
IN3L
IN3R
44
43
42
41
40
39
38
37
36
35
34
30
SEL
CDL+
5
29
SPKR1L
CD-
6
28
SPKR1R
CDR+
7
27
SPKR2L
PHONE+
8
26
SPKR2R
PHONE-
9
25
SPKR3L
NAVI-
10
24
SPKR3R
NAVI+
11
23
OUTPUTREF
12
13
14
15
16
17
18
19
20
21
22
PGND
4
VCC
SCL
CassR
VDD
31
GND
3
AM-IF
SDA
CassL
MPX-RDS
32
AM
MUTE
2
TUNER-
33
SIGGND
FM
1
IAM-LEVEL
V33
PHFM-LEVEL
QUASI DIFFERENTIAL
OUT2L
Pin connection (top view)
OUT1R
Figure 2.
OUT1L
Block diagram
IC MONO
DIFFERENTIAL *
Figure 1.
STEREO FULL DIFFERENTIAL *
1
Block diagram and pin connections
D00AU1200/A
5/29
Electrical specifications
2
TDA7501
Electrical specifications
Table 1.
Symbol
Supply
Parameter
Vdd
Supply voltage
VP
Output supply voltage
IS8
Supply current Vdd
IS12
Supply current VP
SVRR
Table 2.
Test condition
Min.
Typ.
Max.
Unit
7.5
8.3
10
V
12
V
Vdd = 8.3V
27
mA
VP = 12V
5
mA
60
dB
Value
Unit
Ripple rejection @ 1kHz
Absolute maximum ratings
Symbol
Parameter
VDDmax
Operating supply voltage VDD
10.5
V
VSmax
Operating supply voltage Vs
13.0
V
Tamb
Operating temperature range
-40 to 85
°C
Tstg
Storage temperature range
-55 to +150
°C
Value
Unit
65
°C/W
Table 3.
Thermal data
Symbol
Rth j-pins
Parameter
Thermal Resistance Junction-pins Max.
ESD:
All pins are protected against ESD according to the MIL883 standard.
Table 4.
Symbol
Electrical characteristcs
(VDD = VS = 8.3V; V33 = 3.3V Tamb = 25°C; RL = 10kΩ; all gains = 0dB;
f = 1kHz; unless otherwise specified)
Parameter
Test condition
Min.
Typ.
Max.
Unit
General
VCL
Input clipping level
SIN
Input separation
GIN MIN
GIN MAX
GSTEP
2.3
VRMS
100
dB
Min. input gain - input part
0
dB
Max. input gain - input part
15
dB
12
dB
1
dB
0.5
mV
5
mV
Max. input gain - output part
80
Volume 0dB
Step resolution
Adjacent gain steps
6/29
VDC
DC steps
dIN
Distortion
GMIN to GMAX
VOUT = 0.7VRMS all stages
0dB
0.00
2
0.08
%
TDA7501
Electrical specifications
Table 4.
Electrical characteristcs (continued)
(VDD = VS = 8.3V; V33 = 3.3V Tamb = 25°C; RL = 10kΩ; all gains = 0dB;
f = 1kHz; unless otherwise specified)
Symbol
VDCout
Rout
Parameter
Test condition
Min.
Typ.
Max.
Unit
Output DC-voltage
pins 41..44
1.65
V
Output impedance OUT1L,
1R
pins 43..44
300
W
Output impedance OUT2L,
2R
pins 41..42
3
kΩ
Quasi differential CD stereo input (non inverting)
Rin
CMRR
VN
Input resistance (see Fig. 2)
Differential
70
100
Common mode rejection
ratio
VCM = 1VRMS @ 1kHz
45
70
dB
VCM = 1VRMS @ 10kHz
45
60
dB
2.0
μV
Output noise
20Hz - 20kHz; unweighted
130
kΩ
Differential phone/navigation/FM/AM input (inverting)
Rin
CMRR
VN
Input resistance (see Fig. 3)
Common mode rejection
ratio
Output noise
35
50
VCM = 1VRMS @ 1kHz
40
70
dB
VCM = 1VRMS @ 10kHz
40
60
dB
2.0
μV
20Hz - 20kHz; unweighted
65
kΩ
AM IF input
Rin
Input resistance
35
50
65
kΩ
70
100
130
kΩ
Cassette input (non inverting)
Rin
Input resistance
VN
Output noise
20Hz - 20kHz; unweighted
μV
2.0
AM/FM level input
Rin
Input resistance
70
Vmin
Minimum input voltage
-0.4
Vmax
Maximum input voltage
100
130
kΩ
V
7.0
V
Dual MPX control (pin tuner-)
VCTRLMPX1 Control voltage for MPX 1+2
MPX1 -> MPX1 + MPX2
1.5
V
VCTRLMPX2 Control voltage for MPX2
MPX1 + MPX1 -> MPX2
4.0
V
VCTRLMPX3 Control voltage for MPX 1+2
MPX2 -> MPX1 + MPX2
3.5
V
VCTRLMPX4 Control voltage for MPX1
MPX1 + MPX2 -> MPX2
1.0
V
Speaker outputs RLOAD = 10KW (AC)
Rin
GMAX
Input impedance
Max. gain
35
external reference mode
50
33
65
kΩ
dB
7/29
Electrical specifications
Table 4.
Electrical characteristcs (continued)
(VDD = VS = 8.3V; V33 = 3.3V Tamb = 25°C; RL = 10kΩ; all gains = 0dB;
f = 1kHz; unless otherwise specified)
Symbol
ATTMAX
TDA7501
Parameter
Max. attenuation
Test condition
Min.
internal reference mode
ATTSTEP Step resolution
ATTMUTE Output mute attenuation
80
Typ.
Max.
Unit
-73
dB
1
dB
100
dB
EE
Attenuation set error
from +15 to -40dB
VDC
DC steps
Adjacent attenuation steps
0.3
internal reference mode
4.15
V
external reference mode
outre
f
V
2.3
2.8
VRMS
VRMS
4
VRMS
VDCOUT
VCLIP
Output DC voltage
Output clipping level
d = 0.3%, VCC = VDD = 8.3V
gain = 0dB
gain = 6dB
d = 0.3%, VCC = 12V
VDD = 8.3V gain = 6dB
RL
Output load resistance
CL
Output load capacitance
ROUT
AC coupled
2
dB
3
mV
5
Output impedance
kΩ
40
10
nF
120
W
3.0
7.5
10
13
μV
μV
μV
μV
dB
dB
VN
Output noise
BW = 20Hz-20kHz muted0dB
muted 6dB
gain = 0dB
gain = 6dB
S/N
Signal to noise ratio
BW = 20Hz-20kHz VO =
2VRMS
VO = 4VRMS
106
110
dout
Distortion
VOUT = 1VRMS; all stages 0dB
0.00
5
SC
Channel separation left/right
80
100
dB
X
Crosstalk
80
100
dB
0.08
%
ADCVDDREF (CODEC reference)
Imaxadc
Max. output current
pin 40
5
mA
0.8
V
BUS INPUTS
Vlow
Voltage for logic "0
"inputs SEL, SCL,SDA,MUTE
Vhigh
Voltage for logic "1
"inputs SEL, SCL,SDA,MUTE
SPI_mode threshold voltage
i
Vth_SPI
8/29
2.4
0
V
VDD1.8
V
TDA7501
3
Description of the input part
Description of the input part
On the input side, the TDA7501 (see Figure 3) connects the external audio and tuner
signals to the four AD converters of the digital car radio signal processor TDA7500. The
audio signals are adjusted by the input gain stage to the internal reference signal with 2V
rms referred to 4.15V (=V33 ·1.2575). The following CODEC interface attenuates the 2VRMS
to 0.8Vrms referred to the CODEC's reference voltage of 1.65V which allows a DC coupling
to the TDA7500.
Figure 3.
Input part.
CDL
CDR
BYPASS (2Vrms)
TO OUTPUT PART
INGAIN BYP
PHONE/NAVI-MIX
CDL
INSELECT 1L
0..15dB
1dB STEP
PHONE/FDL
NAVI/FDR
CASSL
PHONE/NAVI-MIX
CASSR
CDL+
CD-
CDL
QDIFFSTEREO
CDR
CDR+
PHONE+
FULL
DIFFERENTIAL
STEREO
PHONE-
NAVIAM-LEVEL
INGAIN 1L
CODEC-IF
2Vrms
VIN:
2Vrms
VIN:
2Vrms
VIN:
2Vrms
VIN:
0..15dB
1dB STEP
MPX-RDS
AM
4.15Vdc
2Vrms
VOUT: 1.65Vdc
0.8Vrms
0.8Vrms
OUT1L
AM-LEVEL
DIFF-MONO
CDR
PHONE/NAVI
MIX
NAVI+
MUTE
CASSL
INSELECT 1R
PHONE/FDL
NAVI/FDR
DIFF-MONO
PHONE/NAVI-MIX
(QDiff-Stereo)
CASSR
LEVEL-SHIFT
MPX-RDS
MUTE
INGAIN 1R
CODEC-IF
0..15dB
1dB STEP
FM/DUAL-MPX
4.15Vdc
2Vrms
VOUT: 1.65Vdc
0.8Vrms
0.8Vrms
OUT1R
AM-SPIKES
FM-LEVEL
LEVEL-SHIFT
FM
FM
TUNER-
FM/AM-DIFF
DUAL-MPX
AM
AM
CDL
INSELECT 2L
PHONE/FDL
NAVI/FDR
PHONE/NAVI-MIX
MUTE
CASSL
ENVELOPE DETECTOR
AM-IF
MPX-RDS
CODEC-IF
0..15dB
1dB STEP
AM
AM-SPIKES
INGAIN 2L
FM-LEVEL
4.15Vdc
2Vrms
VOUT: 1.65Vdc
0.8Vrms
0.8Vrms
OUT2L
AM-LEVEL
CDR
INSELECT 2R
PHONE/FDL
NAVI/FDR
PHONE/NAVI-MIX
CASSR
MPX-RDS
FM/DUAL-MPX
MUTE
INGAIN 2R
0..15dB
1dB STEP
CODEC-IF
4.15Vdc
2Vrms
VOUT: 1.65Vdc
0.8Vrms
0.8Vrms
OUT2R
AM-SPIKES
D00AU1201
9/29
Description of the input part
3.1
TDA7501
Input Stages
The device offers several input stages for the different signals which have to be handled by
the system. A quasi differential input (see Figure 4) can be used for (external) CD changer.
The two mono differential inputs allow the connection of phone & navigation (see Figure 5)
or it could be used as fully differential stereo input. Additionally a single-ended stereo input
is available for Cassette applications. The lower part of the input section is dedicated to the
tuner signals. Another quasi differential input (see Figure 6) is used to connect AM and FM
referred to the tuner reference (Tuner). This concept supports also double tuner systems.
Also two seperate level inputs are present which are followed by level-shifters to allow the
use of the TDA7500's ADCs. For AM noise blanking an envelope detector driven by the AM
IF is also available.
10/29
Figure 4.
Quasi differential input-stage.
Figure 5.
Mono differential input-stage.
Figure 6.
Differential input-stage for AM/FM.
TDA7501
3.2
Description of the input part
Dual MPX mode
The TDA7501 is able to support a twin tuner concept via the Dual MPX Mode. In this
configuration the FM pin and the AM-pin are acting as MPX1 and MPX2 inputs. The DC
Voltage at the TUNER pin controls whether MPX1, both MPX signals or MXX2 is used to
decode the stereo FM signal (see Figure 6 Please note that the thresholds have a
hysteresis of 500mV. During this mode the high ohmic mute acts on both inputs in parallel.
Furthermore, a background tuner on the internal AM path can be selected by software
aswtching to one of the two MPX inputs.
For the programming of the Dual MPX Mode see the programming section.
Figure 7.
Block diagram Dual MPX.
MPX2
(AM+)
HIZ-MUTE
15K
15K
(D4/5)
1
-
50K
AM
+
(D5/5)
15K
15K
1
CTRL
(TUNER-)
FM
50K
+
-
MPX1
(FM+)
HIZ-MUTE
15K
15K
1
50K
WINDOWCOMPARATOR
& LOGIC
3.3
D00AU1202
Additional quasi differential Input
The TDA7501 can be programmed to additional quasi-differential input by rearranging the
configuration of the navigation and AM level inputs. Since the AM level input becomes the
2nd differential input, the level shift function is not available.
For the programming of the navigation/AM level input configuration see the programming
section.
Figure 8.
Additional quasi differential input simplified
15K
NAVI-/QDIFF1-
15K
1
100K
NAVI/QDIFF1
+
15K
NAVI+/COM+
15K
1
33K
100K
D3/4
68K
+
-
D3/4
AMLEVEL/QDIFF2-
1
15K
LEVEL/QDIFF2
15K
D00AU1203
11/29
Description of the input part
3.4
TDA7501
Transfer function of the AM/FM level inputs
In the TDA7501 two level shift stages convert a tuner level (DC) signal to a unipolar output
signal with respect to the Codec Interface reference, that is 1.65V.
The FM level input can be programmed to a signal range of either 0 to 5V (Lo range) which
is the default, or 0 to 6V (Hi range). The AM level input is fixed to the lower 0 to 5V input
range.
For the programming of the FM level input range see the programming section.
Figure 9.
AM/FM level inputs transfer function (DC)
Vout
(V)
D00AU1204
2.65
2.30
LO RANGE
2.15
HI RANGE
1.90
1.65
0
12/29
1
2
3
4
5 Vin(V)
TDA7501
4
Description of the output part
Description of the output part
The TDA7501 has 6 independent outputstage with volume control. The first 4 (main) outputs
have an input selector which allows to select besides the DAC outputs CD direct or
Phone/Navigation-mix. In addition one can mix the SPKR1 with Phone/Navigation so that
traffic or navigation announcements can bypass the DSP (see figure 8).
The TDA7500 CODEC outputs have a maximum output voltage of 0.5Vrms . To obtain
4Vrms , (in the dual supply mode only) the signal is first amplified to have a reference
amplitude of 2V rms. The following volume stage offers up to 15dB gain which gives along
with the programmable 6dB gain in the output-stage enough overdrive capability. To achieve
the maximum output swing of 4Vrms the device must be supplied with an additional supply
of 12V. With a single supply (Vdd = VCC = 8.3V) 2.8Vrms are obtained at the output at
maximum.
Figure 10. Output part.
4.1
Overall gain structure
The overall gain structure of the TDA7501 can be shown in its target application together
with the V225.
The output part in level select (D6/4) offers an additional adaption to the DSP's output level
13/29
Description of the output part
TDA7501
Figure 11. Level diagram.
TDA7501
INPUT PART
OUTPUT PART
LEVEL
SELECT
INPUT GAIN
CODEC
INTERFACE
IN
0..15dB
1dB STEP
2Vrms
4.15Vdc
TDA7500
GAIN
+6dB or
+12dB
2Vrms
4.15Vdc
0.8Vrms
1.65Vdc
0.9Vrms
1.65Vdc
2Vrms
4.15Vdc
VOLUME
+15
..
-79dB
OUTPUT
LINEDRIVERS
OUT
0/+6dB STEP
2Vrms (typ)
4.15Vdc
2Vrms
4.15Vdc
or
4Vrms
6Vdc
D00AU1205
4.2
Speaker (linedriver) outputs
The Speaker outputs can be configured in three different operating modes:
1.
- Internal reference mode with 0dB output gain,
2.
- External reference mode with 0dB output gain
3.
- External reference mode with 6dB output gain
Basically, in the internalreference mode the linedriver amplifier acts as a buffer with 0dB gain
regardless of the output gain programmed by bit D0. Since the buffer tracks the internal
generated reference, the OUTPUTREF pin may be left floating.
In the external reference mode the linedriver amplifiers reference tracks the voltage present
at the OUTPUTREF pin. This reference does not necessary have to be external to the
device, it can also be generated by invoking the VCC/2 divider inside the TDA7501 (bit
D1/6). In practice, the term external reference implied that the OUTPUTREF pin at least has
to connect to an external capacitor. In the external reference mode, an additional gain of
6dB can be added by assessing bit D0. This provides a nominal 4VRMS output level in case
the TDA7501 is powered from a dual supply (VDD = 8.3V). When fed from a single supply,
only 2.8VRMS output level can be acheived.
For the programming of output gain and reference selection see the programming section.
Figure 12. Speaker (Linedriver) outputs simplified
D1/6
2R
from VOLUME-STAGE
2Vrms
4.15Vdc
R
6dB
3R
VREF
OUTPUTREF
6dB
0dB
buffer
D0/6
+
D1/6
D0/6
6dB
6dB
VREF
2R
14/29
SPKROUT
R
3R
D00AU1207
TDA7501
5
Reference concept
Reference concept
For the input section the TDA7501 generates the internal reference voltage by multiplying
the V33 voltage by 1.2575.
The V33 voltage is also buffered and fed back to the CODEC where it is used to generate all
necessary references. For best performance it is recommended to filter the V33 reference
pin by means of a passive second order lowpass as shown in Figure 13. This concept allows
a direct DC coupling between the TDA7501 and the DSP because of the accurate matching
of DC levels. On the output side the TDA7501 offers two main modes: a single supply and a
dual supply mode.
5.1
Dual supply mode
In this mode the outputs are able to provide up to 4V rms with a minimum supply VCC of 12V
as well as a output reference voltage set to half of VCC (bit D0 of the mode select byte set to
'1').
If the switch D1/byte mode select is open the output reference voltage must be defined
externally e.g. a zener diode with RC lowpass.
If the switch is closed the reference voltage will be half of VCC and only an external capacitor
has to be added.
5.2
Single supply mode
If VCC and Vdd are connected to a single supply the maximum possible output swing is about
2.8V rms .
The output reference voltage pin can be left open or otherwise the internal voltage divider
can be used to generate for the outputs a VCC/2 reference.
Figure 13. Reference voltage generation
TDA7500
TDA7501
15/29
Digital interface
6
TDA7501
Digital interface
The TDA7501 digital interface offers two different protocols: SPI and I2C.
To select I2C-mode the SEL-pin has to beconnected to VDD. If the voltage at the SEL-pin is
more than about 1V below the VDD voltage the interface switches to SPI-mode.
In both cases the interface is able to work with a 3.3V microprocessor as well as with a 5V
microprocessor. For details of both protocols refer to the programming section.
16/29
TDA7501
SPI bus mode
7
SPI bus mode
7.1
Interface protocol
The TDA7501 SPI interface protocol comprises :
●
a subaddress and
●
a sequence of n databytes
each consisting of 8 bits (see Figure 14).
The interface accepts both a positiv (Cpol = 1, Cpha = 1) as well as a negativ (Cpol = 0,
Cpha = 0) clocking scheme. However, the data transmitted has to be valid on the rising
edges of the serial clock SCL.
Figure 14. Timing diagram for the SPI bus mode.
SEL
SCL
Cpol=1
SCL
Cpol=0
SDA
SA3 SA2 SA1 SA0
D7
D6
D5
D4
SUBADDRESS
Table 5.
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
DATA-n
D0
D00AU1209
Switching characteristics (SPI mode)
Symbol
fSCLK
D3
DATA
Parameter
Min.
Typ.
Max.
Unit
4.0
MHz
Serial input clock frequency (SCL)
0
Tsu
Serial data setup time
40
ns
Thld
Serial data hold time
40
ns
Twh
Serial clock high time width
100
ns
Twl
Serial clock low time width
100
ns
Tscl
Select (SEL) to select (SCL) falling setup time
200
ns
Trel
Select (SCL) to select (SEL) rising release time
200
ns
tr
Data rise time
2
ms
tf
Data fall time
2
ms
Tsh
Chip select high time
200
ns
Figure 15. Timing diagram for switching characteristic
Tscl
Tsu
Thld
Twh
Twl
Trel
Tsh
SEL
SCL
SDA
SAx,Dy
D00AU1208
17/29
I2C bus mode
TDA7501
8
I2C bus mode
8.1
Interface protocol
The interface protocol comprises:
●
a start condition (S)
●
a chip address byte (write mode only)
●
a subaddress byte
●
a sequence of data (N-bytes + acknowledge)
●
a stop condition (P)
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
1
ACK = Acknowledge
S = Start
P = Stop
18/29
0
MSB
0 ACK 0
DATA 1...DATA n
LSB
0
I
0 SA3 SA2 SA1 SA0 ACK
MSB
LSB
DATA
ACK P
TDA7501
Software specification for both modes
9
Software specification for both modes
9.1
Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled.
9.2
Reset condition
A Power-On-Reset is invoked if the Supply-Voltage V dd is below than 3.5V. After POR the
following data is written automatically into the registers of all subaddresses :
MSB
LSB
1
1
1
1
1
1
1
0
The programming after POR is marked bold-face in the programming tables.
With this programming all the outputs are muted to their corresponding reference voltages.
9.3
Programming modes
Table 6.
Subaddresses
MSB
LSB
Name
D7
D6
I
D4
0
1
0
0
SA3
SA2
SA1
SA0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input selector 1L
Input selector 1R
Input selector 2L
Input selector 2R
Phone/Navigation
Mode Select
Configuration
Output selector
Volume 1L
Volume 1R
Volume 2L
Volume 2R
Volume 3L
Volume 3R
FM-level
reserved
Autoincrement mode off
Autoincrement mode on
0
must be "0”
19/29
Software specification for both modes
Table 7.
TDA7501
Input selector 1L..3R, bits D7 ..D3 (subaddresses 0..3)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
mute
off
on
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 8.
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
1
gain
15dB
14dB
13dB
12dB
11dB
10dB
9dB
8dB
7dB
6dB
5dB
4dB
3dB
2dB
1dB
0dB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input selector 1L, bits D2 ..D0 (subaddresses 0)
MSB
LSB
Function
D7
20/29
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
source select
CDL
Phone/FDL
Navigation/FDR
Phone/Navigation mix
CassL
MPX-RDS
AM
AM-level
TDA7501
Software specification for both modes
Table 9.
Input selector 1R, bits D2 ..D0 (subaddresses 1)
MSB
LSB
Function
D7
D6
Table 10.
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
source select
CDR
Phone/FDL
Navigation/FDR
Phone/Navigation mix
CassR
MPX-RDS
FM (or MPX1/MPX2 in Dual MPX
mode)
AM-spikes
Input selector 2L, bits D2 ..D0 (subaddresses 2)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
0
0
0
0
1
1
1
1
Table 11.
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
source select
CDL
Phone/FDL
Navigation/FDR
Phone/Navigation mix
CassL
AM
FM-level
AM-level
Input selector 2R, bits D2 ..D0 (subaddresses 3)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
source select
CDR
Phone/FDL
Navigation/FDR
Phone/Navigation mix
CassR
MPX-RDS
FM (or MPX1/MPX2 in Dual MPX
mode)
AM-spikes
21/29
Software specification for both modes
Table 12.
TDA7501
Phone navigation (subaddress 4)
MSB
LSB
Function
D7
D6
D5
D4
D3
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
22/29
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
mix level phone/navigation
0/mute
-1.6dB/-15.5dB
-3.6/-9.6dB
-6/-6dB
-9.6/-3.6dB
-15.5/-1.6dB
mute/0dB
mute
Input configuration
quasidifferential input (no level
shift function)
Navi & AM Level input
gain
15dB
14dB
13dB
12dB
11dB
10dB
9dB
8dB
7dB
6dB
5dB
4dB
3dB
2dB
1dB
0dB
TDA7501
Software specification for both modes
Table 13.
Mode select (subaddress 5)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
0
0
1
1
D1
D0
0
0
1
1
0
1
0
1
AM-IF rectifier corner frequency
14KHz
18.5KHz
28KHz
56KHz
0
1
0
1
backkground tuner select (internal AMpath)
FM-in (MPX1)
AM-in (MPX2)
0
1
Dual MPX mode
on (control through Tuner- - voltage)
off
0
1
0
0
1
0
1
0
1
1
Table 14.
AM-IF rectifier gain
18dB
15.5dB
12dB
6dB
forced Dual MPX mode
MPX1 (allows automatic selection)
MPX2 (overwrites automatic selection)
MPX1+ MPX2 (overwrites automatic
selection)
MPX1 (overwrites automatic selection)
Configuration (subaddress 6)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
01
01
01
output gain
0dB
+6dB
reference voltage setting for output
external reference / internal reference
(V33*1.25)
internal divider for output reference
voltage connected to VCC/2
disconnected
fast charge (switches at CD input)
open closed
Input level select (output
power)12dB6d0
23/29
Software specification for both modes
Table 14.
TDA7501
Configuration (subaddress 6) (continued)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
RDS-mute (high
impedance)mutedunmuted
01
mute pin function I"0" does not
activate the output mute"1" activates
the output mute
01
mute pin function II"0" activates the
high impedance mute"1" does not
activate the high impedance mute
01
Table 15.
Output selector (subaddress 7)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
24/29
0
1
0
1
0
1
0
1
0
1
0
1
D0
0
1
0
1
source select SPKR 1L
Bypass
CDL
Phone/Navigation mix / IN1L
IN1L
source select SPKR 1R
Bypass
CDL
Phone/Navigation mix / IN1RI
N1R
source select SPKR 2L
Bypass
CDL
mute
IN2L
source select SPKR 2R
Bypass
CDL
mute
IN2R
TDA7501
Software specification for both modes
Table 16.
Volume speaker outputs (subaddresses 8...13)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
1
:
1
1
0
0
:
0
0
:
0
0
0
:
0
0
0
0
:
0
0
:
1
1
0
:
0
0
0
0
:
0
0
:
0
0
0
:
0
0
0
0
:
0
1
:
0
0
1
;
0
0
0
0
:
1
0
:
1
1
1
;
0
0
0
0
:
1
0
:
1
1
1
;
0
0
0
0
:
1
0
:
1
1
1
;
1
0
0
1
:
1
0
:
0
1
+15dB
:
+1dB
0dB
0dB
-1dB
:
-15dB
-16dB
:
-78dB
-79dB
x
1
1
x
x
x
x
x
Mute
Table 17.
FM level range (subaddress 14)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
1
0
0
0
1
1
1
1
:
1
:
1
D1
D0
0...6Volts
0...5 Volts
0
1
1
1
0
Must be
The unused subaddresses 14/15 must be programmed to "11111110" to allow software
compatibility to future extensions.
25/29
Software specification for both modes
TDA7501
Figure 16. Test board diagram
10K
6.8K
3.3V
10μF
V33
1
10μF
SIGGND
100nF
CASSL
100nF
CASSR
100nF
CDL
100nF
CDGND
100nF
CDR
100nF
PHONE+
100nF
PHONE100nF
NAVI100nF
NAVI+
100nF
FM
100nF
AM
100nF
MPX
100nF
AM-IF
100nF
TUNER-
44
CASSL
CASSR
CDL+
CD-
CDR+
PHONE+
PHONE-
NAVI-
NAVI+
FM
AM
MPX-RDS
AM-IF
TUNER-
43
2
42
3
41
4
40
39
5
6
38
7
37
8
9
35
10
34
33
11
32
31
14
30
16
29
28
17
27
26
18
25
24
15
13
12
AM-LEVEL
FM-LEVEL
AM-LEVEL
26/29
36
TDA7501
19
GND
FM-LEVEL
22
PGND
21
20
VDD
VCC
8.3V
12V
23
OUT1L
3.3nF
OUT1R
3.3nF
OUT2L
330pF
OUT2R
330pF
ADCYDDREF
IN1L
IN1R
IN2L
IN2R
IN3L
IN3R
220nF
TDA7500
220nF
220nF
220nF
220nF
220nF
MUTE
MUTE
SDA
SDA
SCL
SCL
SEL
SEL
SPKR1L
OUTLF
SPKR1R
OUTRF
SPKR2L
OUTLR
SPKR2R
OUTRR
SPKR3L
OUTSWL
SPKR3R
OUTSWR
10K
OUTPUTREF
10μF
VCC 12V
6.8K
10μF
6V
D00AU1210
TDA7501
10
Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 17. LQFP44 (10x10) mechanical data & package dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.60
MAX.
0.063
A1
0.05
0.15
0.002
A2
1.35
1.40
1.45
0.053
0.055
0.057
B
0.30
0.37
0.45
0.012
0.015
0.018
0.006
C
0.09
0.20
0.004
D
11.80
12.00
12.20
0.464
0.472
0.480
D1
9.80
10.00
10.20
0.386
0.394
0.401
E
11.80
12.00
12.20
0.464
E1
9.80
10.00
10.20
0.386
D3
8.00
0.008
0.315
0.472
0.480
0.394
0.401
E3
8.00
0.315
e
0.80
0.031
L
L1
k
ccc
0.45
0.60
OUTLINE AND
MECHANICAL DATA
0.75
1.00
0.018
0.024
0.030
0.039
LQFP44 (10 x 10 x 1.4mm)
0˚(min.), 3.5˚(typ.), 7˚(max.)
0.10
0.0039
0076922 E
27/29
Revision history
11
TDA7501
Revision history
Table 18.
28/29
Document revision history
Date
Revision
Changes
21-Jun-2004
1
Initial release.
22-Jun-2004
2
Minor revision, content edit.
9-Sep-2004
3
Minor revision, content edit.
15-Dec-2004
4
Minor revision, content edit.
17-Jan-2007
5
Package changed, layout change, text modifications
TDA7501
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