STMICROELECTRONICS TDA7342EQ2N

TDA7342EQ2N
Digitally controlled audio processor
Features
■
Input multiplexer
– Two stereo and one mono inputs
– One quasi differential input
– Selectable input gain for optimal adaptation
to different sources
■
Fully programmable loudness function
■
Volume control in 0.3dB steps including gain
up to 20dB
■
Zero crossing mute, soft mute and direct mute
■
Bass and treble control
■
Four speaker attenuators
– Four independent speakers control in
1.25dB steps for balance and fader facilities
– Independent mute function
■
All functions programmable via serial I2C bus
Description
The audioprocessor TDA7342EQ2N is an
upgrade of the TDA731X audioprocessor family.
TQFP32
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained. Several new features like
softmute, and zero-crossing mute are
implemented. The soft Mute function can be
activated in two ways:
1.
Via serial bus (Mute byte, bit D0)
2.
Directly on pin 21 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
Order codes
Part number
Package
Packing
TDA7342EQ2N
TQFP32
Tray
TDA7342EQ2NTR
TQFP32
Tape and reel
August 2006
Rev 1
1/21
www.st.com
1
Contents
TDA7342EQ2N
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pns description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
5
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5
Transmission without Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3
Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
TDA7342EQ2N
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SUBADDRESS (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
List of figures
TDA7342EQ2N
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
4/21
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Validity on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TQFP32 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RIGHT
INPUTS
C5
C4
MONO INPUT
CD
LEFT
INPUTS
C7
C3
C6
C2
C1
6
R2
VS
7
8
M
R1
5
10
11
12
13
R3
SGND
L3
L2
L1
30
31
SUPPLY
R3
L3
3
OUT(R)
28
INPUT
SELECTOR
+ GAIN
CSM
47nF
C10
47nF
C8
CSM
4
LOUD(R)
2
14
LOUD+
VOL
IN(R)
ZERO
CROSS +
MUTE
19
C12
R1
4.7K
TREBLE(L)
TREBLE
32
C17 2.7nF
MUTE
SPKR
ATT
MUTE
SPKR
ATT
C13
BIN(R)
1
TREBLE
C16
2.7nF
TREBLE(R)
MUTE
SPKR
ATT
MUTE
SPKR
ATT
SERIAL BUS DECODER + LATCHES
100nF
BOUT(R)
BASS
17
C15
100nF
BIN(L)
BASS
100nF
20
SOFT
MUTE
9
LOUD+
VOL
18
LOUD(L)
ZERO
CROSS +
MUTE
15
16
CREF
10µF
R1
R2
M
M
L2
L1
IN(L)
OUT(L)
C14
D93AU043B
21
23
25
26
27
29
22
24
OUT
RIGHT REAR
BUS
+Vcc
OUT
RIGHT FRONT
DIGGND
SDA
ADDR
SCL
OUT
LEFT REAR
OUT
LEFT FRONT
Figure 1.
C11
47nF
BOUT(L)
R2
4.7K
100nF
1
C9
TDA7342EQ2N
Block diagram
Block diagram
Block diagram
5/21
Pns description
Pns description
DIG GND
SDA
SCL
CREF
ADDR
VS
Pin connection (Top view)
TR L
Figure 2.
GND
2
TDA7342EQ2N
32 31 30 29 28 27 26 25
TR R
1
24
OUT LF
IN R
2
23
OUT RF
OUT R
3
22
OUT LR
LOUD R
4
21
OUT RR
IN R3
5
20
BOUT R
IN R2
6
19
BIN R
IN R1
7
18
BOUT L
MONO
8
17
BIN L
OUT L
IN L
CSM
IN L1
IN L2
IN L3
LOUD L
6/21
CD GND
9 10 11 12 13 14 15 16
D94AU060A
TDA7342EQ2N
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 1.
Absolute Maximum Ratings
Symbol
VS
3.2
Parameter
Operating Supply Voltage
Unit
10.5
V
Tamb
Operating Ambient Temperature
-40 to 85
°C
Tstg
Storage Temperature Range
-55 to 150
°C
Quick reference data
Table 2.
Quick reference data
Symbol
Parameter
Min.
Typ.
Max.
Unit
6
9
10.2
V
2.1
2.6
VS
Supply Voltage
VCL
Max. input signal handling
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio
106
dB
SC
Channel Separation
100
dB
Volume Control 0.3dB step
Vrms
0.08
%
-59.7
20
dB
Treble Control 2dB step
-14
+14
dB
Bass Control 2dB step
-10
+18
dB
-38.75
0
dB
0
11.25
dB
Fader and Balance Control 1.25dB step
Input Gain 3.75dB step
Mute Attenuation
3.3
Value
100
dB
Value
Unit
150
°C/W
Thermal data
Table 3.
Symbol
Rth j-amb
Thermal data
Parameter
Thermal Resistance Junction-pins
7/21
Electrical specifications
TDA7342EQ2N
3.4
Electrical characteristics
Table 4.
Electrical characteristics
(VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test
circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
70
100
130
KΩ
2.1
2.6
VRMS
100
dB
INPUT SELECTOR
RI
VCL
Input Resistance
Clipping Level
d ≤ 0.3%
SI
Input Separation
80
RL
Output Load Resistance
2
KΩ
GI MIN
Minimum Input Gain
-0.75
0
0.75
dB
GI MAX
Maximum Input Gain
10.25
11.25
12.25
dB
Step Resolution
2.75
3.75
4.75
dB
Gstep
eN
VDC
Input Noise
20Hz to 20 KHz unweighted
2.3
Adiacent Gain Steps
1.5
µV
10
mV
DC Steps
GIINto GIMAX
3
mV
DIFFERENTIAL INPUT ( IN 3)
RI
CMRR
Input selector BIT D6 = 0 (0dB)
10
15
20
KΩ
Input selector BIT D6 = 1(-6dB)
14
20
30
KΩ
VCM = 1VRMS; f =1KHz
48
75
dB
f = 10KHz
45
70
dB
Input Resistance
Common Mode Rejection Ratio
d
Distortion
VI= 1VRMS
eIN
Input Noise
20Hz to 20KHz; Flat; D6 = 0
GDIFF
0.01
0.08
%
µV
5
D6 = 0
-1
0
1
dB
D6 = 1
-7
-6
-5
dB
35
50
Differential Gain
VOLUME CONTROL
RI
Input Resistance
KΩ
GMAX
Maximum Gain
18.75
20
21.25
dB
AMAX
Maximum Attenuation
57.7
59.7
62.7
dB
ASTEPC
Step Resolution Coarse Atten.
0.5
1.25
2.0
dB
ASTEPF
Step Resolution Fine Attenuation
0.11
0.31
0.51
dB
G = 20 to -20dB
-1.25
0
1.25
dB
G = -20 to -58dB
-3
2
dB
2
dB
0
3
mV
0.5
5
mV
EA
Attenuation Set Error
Et
Tracking Error
Adiacent Attenuation Steps
VDC
8/21
-3
DC Steps
From 0dB to AMAX
TDA7342EQ2N
Table 4.
Electrical specifications
Electrical characteristics (continued)
(VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test
circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
35
50
65
KΩ
LOUDNESS CONTROL
RI
Internal Resistor
Loud = On
AMAX
Maximum Attenuation
17.5
18.75
20.0
dB
Astep
Step Resolution
0.5
1.25
2.0
dB
ZERO CROSSING MUTE
VTH
AMUTE
VDC
Zero Crossing Threshold (1)
WIN = 11
20
mV
WIN = 10
40
mV
WIN = 01
80
mV
WIN = 00
160
mV
100
dB
Mute Attenuation
DC Step
80
0dB to Mute
0
3
mV
SOFT MUTE
AMUTE
Mute Attenuation
TDON
ON Delay Time
IDOFF
OFF Current
VTHSM
Soft Mute Threshold (pin 14)
45
60
CCSM = 22nF; 0 to -20dB; I = IMAX
0.7
1
1.7
ms
CCSM = 22nF; 0 to -20dB; I = IMIN
20
35
55
ms
VCSM= 0V; I = IMAX
25
50
75
µA
VCSM= 0V; I = IMIN
dB
µA
1
1.5
2.5
3.5
V
15
18
20
dB
-8.5
-10
-11.5
dB
BASS CONTROL
BBOOST
Max Bass Boost
BCUT
Max Bass Cut
Astep
Step Resolution
1
2
3
dB
Internal Feedback Resistance
45
65
85
KΩ
±13
±14
±15
dB
1
2
3
dB
35
37.5
40
dB
0.5
1.25
2.00
dB
80
100
Rg
TREBLE CONTROL
CRANGE Control Range
Astep
Step Resolution
SPEAKER ATTENUATORS
CRANGE Control Range
Astep
AMUTE
Step Resolution
Output Mute Attenuation
EA
Attenuation Set Error
VDC
DC Steps
Data Word = XXX11111
Adjacent Attenuation Steps
0
dB
1.25
dB
3
mV
9/21
Electrical specifications
Table 4.
TDA7342EQ2N
Electrical characteristics (continued)
(VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test
circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
2.1
2.6
Max.
Unit
AUDIO OUTPUT
Vclip
Clipping Level
RL
Output Load Resistance
RO
Output Impedance
VDC
DC Voltage Level
d = 0.3%
Vrms
2
KΩ
30
100
Ω
3.5
3.8
4.1
V
GENERAL
VCC
Supply Voltage
6
9
10.2
V
ICC
Supply Current
5
10
15
mA
60
80
dB
B = 20 to 20kHz "A" weighted
65
dB
Output Muted (B = 20 to 20kHz
flat)
2.5
µV
All Gains 0dB (B = 20 to 20kHz
flat)
5
15
µV
AV= 0 to -20dB
0
1
dB
AV= -20 to -60dB
0
2
dB
f = 1KHz
PSRR
eNO
Et
Power Supply Rejection Ratio
Output Noise
Total Tracking Error
S/N
Signal to Noise Ratio
SC
Channel Separation
d
Distortion
All Gains = 0dB; VO= 1Vrms
80
VIN =1V
106
dB
100
dB
0.01
0.08
%
1
V
BUS INPUTS
VIL
Input Low Voltage
VlN
Input High Voltage
IlN
Input Current
VIN = 0.4V
VO
Output Voltage SDA
Acknowledge
IO= 1.6mA
3
-5
1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold.
10/21
V
0.4
5
µA
0.8
V
TDA7342EQ2N
4
I2C bus interface
I2C bus interface
Data transmission from microprocessor to the TDA7342EQ2N and viceversa takes place
thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
4.1
Data Validity
As shown in Figure 3, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
4.2
Start and Stop Conditions
As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
A STOP conditions must be sent before each START condition.
4.3
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
4.4
Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 5). The peripheral (audioprocessor) that acknowledges has to pull-down
(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
4.5
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data. This approach of course is less protected from misworking and decreases the
noise immunity.
11/21
I2C bus interface
TDA7342EQ2N
Figure 3.
Data Validity on the I2C BUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
Figure 4.
CHANGE
DATA
ALLOWED
D99AU1031
Timing Diagram of I2C BUS
SCL
I2CBUS
SDA
D99AU1032
START
Figure 5.
STOP
Acknowledge on the I2C BUS
SCL
1
2
3
7
8
9
SDA
MSB
START
Patent note:
12/21
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
Purchase of I2C Components of STMicrolectronics,
conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the
system conforms to the I2C Standard Specifications as
defined by Philips.
TDA7342EQ2N
Software specification
5
Software specification
5.1
Interface Protocol
The interface protocol comprises:
●
A start condition (s)
●
A chip address byte, (the LSB bit determines read/write transmission)
●
A subaddress byte.
●
A sequence of data (N-bytes + acknowledge)
●
A stop condition (P)
CHIP ADDRESS
MSB
S
1
SUBADDRESS
LSB
0
0
0
1
0
A
DATA 1 ... DATA n
MSB
R/W
ACK
X
LSB
X
X
I
A3 A2 A1 A0
MSB
LSB
ACK
DATA
ACK
P
D06AU1650
ACK = Acknowledge
S
= Start
P
= Stop
I
= Auto Increment
X
= Not used
A
= I2C address value selectable according to ADDR pin status
ADDR = Open/Gnd A = O
ADDR = VCC
A=I
MAX CLOCK SPEED 500kbits/s
5.2
Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled
Table 5.
SUBADDRESS (receive mode)
MSB
X
LSB
X
X
I
Function
A3
A2
A1
A0
0
0
0
0
Input Selector
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, Treble
0
1
0
0
Speaker Attenuator LF
0
1
0
1
Speaker Attenuator LR
0
1
1
0
Speaker Attenuator RF
0
1
1
1
Speaker Attenuator RR
1
0
0
0
Mute
13/21
Software specification
5.3
TDA7342EQ2N
Transmitted data
Table 6.
Send mode
MSB
LSB
X
X
X
X
X
SM
ZM
X
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
5.4
Data byte specification
X = not relevant; set to "1" during testing
Table 7.
Input selector
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
not used
0
1
0
0
1
IN 2
0
1
0
1
0
IN 1
0
1
0
1
1
AM mono
0
1
1
0
0
not used
0
1
1
0
1
not used
0
1
1
1
0
not allowed
0
1
1
1
1
not allowed
0
1
0
0
11.25dB gain
0
1
0
1
7.5dB gain
0
1
1
0
3.75dB gain
0
1
1
1
0dB gain
0
0dB differential input gain (IN3)
1
-6dB differential input gain (IN3)
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
14/21
TDA7342EQ2N
Software specification
Table 8.
Loudness
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
0
0
0
0
0
0dB
X
X
X
0
0
0
0
1
-1.25dB
X
X
X
0
0
0
1
0
-2.5dB
X
X
X
0
0
0
1
1
-3.75dB
X
X
X
0
0
1
0
0
-5dB
X
X
X
0
0
1
0
1
-6.25dB
X
X
X
0
0
1
1
0
-7.5dB
X
X
X
0
0
1
1
1
-8.75dB
X
X
X
0
1
0
0
0
-10dB
X
X
X
0
1
0
0
1
-11.25dB
X
X
X
0
1
0
1
0
-12.5dB
X
X
X
0
1
0
1
1
-13.75dB
X
X
X
0
1
1
0
0
-15dB
X
X
X
0
1
1
0
1
-16.25dB
X
X
X
0
1
1
1
0
-17.5dB
X
X
X
0
1
1
1
1
-18.75dB
X
X
X
1
D3
D2
D1
D0
Loudness OFF (1)
1. If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency
response. D0 to D3 determine the attenuation level.
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
Table 9.
Mute
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
1
0
D0
1
Soft Mute On
0
1
Soft Mute with fast slope (I = IMAX)
1
1
Soft Mute with slow slope (I = IMIN)
Direct Mute
0
1
Zero Crossing Mute On
0
0
Zero Crossing Mute Off
(delayed until next zerocrossing)
1
0
D1
Zero Crossing Mute and Pause Detector
Reset
160mV ZC Window Threshold (WIN =
00)
15/21
Software specification
Table 9.
TDA7342EQ2N
Mute
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
1
80mV ZC Window Threshold (WIN = 01)
1
0
40mV ZC Window Threshold (WIN = 10)
1
1
20mV ZC Window Threshold (WIN = 11)
0
Nonsymmetrical Bass Cut (1)
1
Symmetrical Bass Cut
1. Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
An additional direct mute function is included in the Speaker Attenuators.
Table 10.
Speaker attenuators
MSB
LSB
SPEAKER ATTENUATOR LF, LR, RF, RR
D7
D6
D5
D4
D3
D2
D1
D0
1.25dB step
X
X
X
0
0
0
0dB
X
X
X
0
0
1
-1.25dB
X
X
X
0
1
0
-2.5dB
X
X
X
0
1
1
-3.75dB
X
X
X
1
0
0
-5dB
X
X
X
1
0
1
-6.25dB
X
X
X
1
1
0
-7.5dB
X
X
X
1
1
1
-8.75dB
10dB step
X
X
X
0
0
0dB
X
X
X
0
1
-10dB
X
X
X
1
0
-20dB
X
X
X
1
1
-30dB
X
X
X
1
1
1
1
1
Speaker Mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
Table 11.
Bass/Treble
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Treble step
16/21
0
0
0
0
-14dB
0
0
0
1
-12dB
TDA7342EQ2N
Software specification
Table 11.
Bass/Treble (continued)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
Bass steps
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
-0dB
1
1
1
1
-0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
0
0
0
1
146B
0
0
0
0
18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
17/21
Software specification
Table 12.
TDA7342EQ2N
Volume
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0.31dB Fine Attenuation Steps
0
0
0dB
0
1
-0.31dB
1
0
-0.62dB
1
1
-0.94dB
1.25dB Coarse Attenuation Steps
0
0
0
0dB
0
0
1
-1.25dB
0
1
0
-2.5dB
0
1
1
-3.75dB
1
0
0
-5dB
1
0
1
-6.25dB
1
1
0
-7.5dB
1
1
1
-8.75dB
10dB Gain / Attenuation Steps
0
0
0
20dB
0
0
1
10dB
0
1
0
0dB
0
1
1
-10dB
1
0
0
-20dB
1
0
1
-30dB
1
1
0
-40dB
1
1
1
-50dB
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1
Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
18/21
TDA7342EQ2N
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
TQFP32 Mechanical Data & Package Dimensions
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
A
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
0.30
C
0.09
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.37
0.45
0.012
0.015
0.018
0.20
0.004
9.00
0.354
D1
7.00
0.276
D3
5.60
0.220
e
0.80
0.031
E
9.00
0.354
E1
7.00
0.276
E3
5.60
0.220
0.45
0.60
0.75
0.018
Weight: 0.20gr
0.008
D
L
MAX.
0.024
L1
1.00
K
0˚(min.), 3.5°(typ.), 7°(max.)
0.030
TQFP32 (7 x 7 x 1.40mm)
0.039
D
A
D1
A2
D3
24
A1
17
25
16
0.10mm
.004
B
E
E1
Seating Plane
E3
9
32
8
1
C
e
L
L1
Figure 6.
B
6
Package information
K
TQFP32
0060661 C
19/21
Revision history
7
TDA7342EQ2N
Revision history
Table 13.
20/21
Document revision history
Date
Revision
03-Aug-2006
1
Changes
Initial release.
TDA7342EQ2N
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