TEA2164S SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT . . . .. .. POSITIVE AND NEGATIVE OUTPUT CURRENT UP TO 1.2A AND – 1.7A A TWO LEVEL COLLECTOR CURRENT LIMITATION COMPLETE TURN OFF AFTER LONG DURATION OVERLOADS UNDER AND OVER VOLTAGE LOCK-OUT SOFT START BY PROGRESSIVE CURRENT LIMITATION DOUBLE PULSE SUPPRESSION BURST MODE OPERATION UNDER STANDBY CONDITIONS DESCRIPTION In a master slave architecture,the TEA2164Scontrol IC achieves the slave function. Primarily designed for TV receivers and monitors applications, this circuit provides an easy synchronization and smart solution for low power stand by operation. Located at the primary side the TEA2164S control IC ensures : - the power supply start-up - the power supply control under stand-by conditions - the process of the regulation signals sent by the master circuit located at the secondary side - direct base drive of the bipolar switching transistor - the protection of the transistor and the power supply under abnormal conditions. For more details, refer to application note AN409. POWERDIP16 (Plastic Package) ORDER CODE : TEA2164S GROUND 1 16 VCC SUPPLY VOLTAGE I COPY 2 15 OUTPUT STAGE POSITIVE SUPPLY VOLTAGE LONG OVERLOAD CAPACITOR 3 14 OUTPUT (BASE CURRENT) SUBSTRATE 4 13 SUBSTRATE SUBSTRATE 5 12 SUBSTRATE PULSE INPUT 6 11 IC(Max.) SENSE OSCILLATOR TIMING RESISTOR 7 10 LOW FREQUENCY OSCILLATOR CAPACITOR OSCILLATOR TIMING CAPACITOR 8 9 January 1998 2164S-01.EPS PIN CONNECTIONS FEEDBACK INPUT IN BURST MODE 1/16 TEA2164S BLOCK DIAGRAM R1 C1 9 10 11 12 Soft Start tON LIMITATION V- IC(Max.) OUT V+ VCC 14 15 16 13 TEA2164S IC(M3) VLF OSCILLATOR IC(Max.) DETECTION IC(M2) VCC MONITORING IC(M1) Valid 1 VCC Sawtooth Return R 16V Internal VCC S Q 13% 1 V+ & 1 & Sawtooth Return SYNC RC OSCILLATOR Positive Pulse SYNC SWITCH 8 7 6 COSC ROSC IN Q IC COPY + AMP R Q DELAY AMP V- VCC < 4.6V Negative Pulse PULSE SHAPER S R Q S 5 REPETITIVE OVERCURRENT PROTECTION 4 V- 3 2 1 C2 ICOPY GND 2164S-02.EPS & Figure 1 : Simplified Application Diagram VCC IN TEA2164S VOUT OUT SLAVE I.C. TEA5170 VREF MASTER I.C. SYNC. INPUT 2164S-03.EPS PWM 2/16 TEA2164S Symbol VCC Parameter Value Unit 18 V Positive Power Supply V16-V1 V+ Positive Power Supply of the Output Stage V15-V1 18 V V– Negative Power Supply V4, 5, 12, 13-V1 –5 V Total Power Supply V16-V4, 5, 12, 13 or V15-V4, 5, 12, 13 20 V Iout+ Positive Output Current 1.5 A Iou t– Negative Output Current 2 A VCC - V– V+ - V– Tj Junction Temperature 150 °C Tstg Storage Temperature – 40, + 150 °C Value Unit 11 °C/W 2164S-01.TBL ABSOLUTE MAXIMUM RATINGS Symbol Rth(j-c) Parameter Junction Case Thermal Resistance 2164S-02.TBL THERMAL DATA MAXIMUM POWER DISSIPATION Ptot (W) 3.5 3.0 2.5 45°C/W 2.0 1.0 0.5 Tamb (°C) 0 50 2164S-04.EPS 1.5 100 RECOMMANDED OPERATING CONDITIONS Parameter VCC Positive Power Supply V– Negative Power Supply (see Figure 2) VCC – V– Min. -5 Typ. Max. 10 14 Unit V 0 V V Total Power Supply 18 Iout+ Positive Output Current 1.2 A Iou t– Negative Output Current 1.7 A Fsw Switching Frequency 50 khz Ro Oscillator Resistor Range 30 150 kΩ Co Oscillator Capacitor Range 470 2700 pF C1 Starting Oscillator Capacitor Range 0.1 4.7 µF C2 Repetitive Overload Protection Capacitor 1 22 µF Vin Input Pulses Amplitude (peak) (derivated pulses - time constant = 1 µs) 0.5 1 V Toper Operating Ambiant Temperature – 20 70 °C 3/16 2164S-03.TBL Symbol TEA2164S Figure 2 : Substrat Biasing Vsubstrat = V- or Vsubstrat = 0 VV+ V+ IB > 0 13 15 12 13 15 IB > 0 TEA2164S IB > 0 TEA2164S 14 14 IB < 0 1 4 IB < 0 5 1 4 5 V- IB < 0 IB < 0 Capacitive Coupling 2164S-05.EPS 12 IB > 0 ELECTRICAL OPERATING CHARACTERISTICS Tamb = 25oC, VCC = 10V, VCC- = 0V, potentials referenced to ground (Pin 1) (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit POWER SUPPLY VCC (start) Starting Voltage (VCC increasing) 8 9 9.6 V VCC (stop) Stopping Voltage (VCC decreasing) 5 6.2 7.4 V V ∆VCC Hysteresis (V CC start – VCC stop) 2 2.8 3.5 Vccmax Overvoltage Lock-out 14.8 15.5 16.2 V Iccstart Starting Positive Supply Current 0.5 0.8 1.5 mA Pulse by Pulse Current Limitation Threshold (see Note) TEA2164SL (Low range) TEA2164SH (high range) -1 -0.875 -0.925 -0.775 -0.825 -0.700 V V VCM2 Current Monitoring 2nd Threshold 1200 1350 1500 mV ∆VCM ∆VCM = VCM2 – VCM1 (L or H) 300 500 700 mV CURRENT LIMITATION AND PROTECTION (Pin 11) VCM1 REPETITIVE OVERCURRENT PROTECTION VCM3 VCM3 - VCM1 VC2 I3 disch I3 ch. Repetitive Overcurrent Threshold (Pin 11) -1.1 -0.9 -0.7 V VCM3 - VCM1 (L or H) -0.16 0.05 0.16 V 2.4 3 3.6 V Lock-out Voltage on Pin 3 Capacitor C2 Discharge Current (synchronized mode) 10 20 30 µA Capacitor C2 Charge Current 50 80 110 µA OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION To Ton(max) Tsyn TO 19.3 21 22.7 µs Maximum Duty Cycle (Tsyn = 1.05 To) 60 70 85 % Synchronization Window 1.0 Oscillator Initial Accuracy (RT = 50kΩ, CT = 1nF) 1.5 I14/I 2 Ic Copy Current Gain 1000 IBON Base Current Starting Pulse 300 mA 13 % VERY LOW FREQUENCY OSCILLATOR Burst Duty Cycle Note : For the best accuracy of VCM1 value the TEA2164S is marked as follows : TEA2164SL (low range) or TEA2164SH (high range). 4/16 2164S-04.TBL OUTPUT STAGE TEA2164S I - FIELD OF APPLICATION The TEA2164S control circuit has been designed primarily for discontinuous mode flyback built with a master-slave architecture, whatever the field of application. But due to its capability to synchronize the transistor switching-off with an external signal (line flyback) and due to an adaptedburst-mode operation for a low power stand-by operation, the TEA2164 offers a smart solution for monitors and TV sets applications. Power supply main features : - maximum output power 140W (transistor forced gain : 3.5) - stand-by mode output power (1W ≤ Psb ≤ 6W ; efficiency > 50%) - operating frequency up to 50kHz - power-switch : bipolar transistor Adapted master-circuit : - Monitor application → TEA5170 - Standard TV application → TEA2028B TEA2029C TEA2128 TEA5170 - Digital TV application → TEA5170 (TEA2028B, TEA2029C and TEA2128 are deflection processors with built-in PWM generator). Figure 3 : Master Slave Power Supply Architecture AUDIO OUTPUT STAGE Muting Control R P1 Mains Input Synchronization SCANNING DEVICE Remote Standby C P2 VOLTAGE REGULATOR Remote Standby VCC TEA2164S TEA5170 µP P1 : Output voltage adjustment in normal mode P2 : Output voltage adjustment in standby Power primary ground Second ground (isolated from mains) 5/16 2164S-06.EPS INFRA-RED RECEIVER TEA2164S II - GENERAL DESCRIPTION In a master slave architecture,the TEA2164SControl IC, located at the primary side of an off line power supplyachievesthe slavefunction; whereas the master circuit is located at the secondary side. The link between both circuits is realizedby a small pulse transformer (Figure 4). The PWM signal are sent towards the primary side through small differentiating transformer. For the TEA2164Spositive pulses are transistorswitchingon commands ; and negative pulses are transistor switching-off commands (Figure 5). In this configuration, only by synchronizing the master oscillator, the switching transistor may be synchronized with an external signal. In the operation of the master-slave architecture, four majors cases must be considered : - normal operating - stand-by mode - power supply start-up - abnormal conditions : off load, short circuit, ... II.2 - Stand-by Mode In this configuration the master circuit no longer sends PWM signals, the structure is not synchronized ; and the TEA2164Soperates in burst mode. The average power consumption at the secondary side may be very low 1W ≤ P ≤ 6W (as it is consumed in TV set during stand by). By action on the maximum duty cycle control, a primary loop maintains a semi-regulation of the output voltages.Voltage on feed-backis applied on Pin 9. BurstperiodisexternallyprogrammedbycapacitorC1. II.1 - Normal Operating (master slave mode) In this configuration,the master circuit generates a pulse width modulatedsignal issued from the monitoring of the output voltage which needs the best accuracy (in TV applications : the horizontal deflectionstage supply voltage). Themaster circuit power supply can be supplied by another output. Figure 4 : System Description Waveforms VCC(START) TEA2164S VCC Voltage VCC(STOP) t 0 t BURST Collector Current Envelop 0 B B b b b b t Output Voltage t 0 t 1 µP Supply Voltage 2 Standby 1 2 0 Start-up tBURST : burst period t DELAY : time constant generated by µP 6/16 tDELAY Standby t1 Normal Operation B : burst envelop (out of regulation) b : burst envelop (with standby regulation) t2 t Standby t1, t2 : commands issued by µP 2164S-07.EPS TEA5170 Output Voltage Envelop 0 TEA2164S II - GENERAL DESCRIPTION (continued) Figure 5 : Master Slave Mode Waveforms Sync. Pulses Synchronization PWM Signal SLAVE CIRCUIT MASTER CIRCUIT Pulse Input 2164S-08.EPS Base Current Figure 6 : Burst Mode Waveforms θ Collector Current Envelop Soft Start 0 t 4V P2 Voltage (Pin 10) 1V C1 10 0 9 t Tb TEA2164S ton Tb θ Output Voltage Max. C1 3.3 0 t 106 (C in Farad) 2164S-09.EPS T 3.3 - 1.6 (V9) 0.13 Tb II.3 - Power Supply Start-up After the mains have been switched-on, the VCC storage capacitor of the TEA2164S is charged through a high value resistor connected to the rectified high voltage. When Vcc reaches VCC start threshold (9V typ), the TEA2164 starts operating in burst mode. Since available output power is low in burst mode the output power consumption must remain low before complete setting-up of output voltage. In TV application it can be achieved by maintaining the TV in stand-by mode during start-up (Figure 7). 7/16 TEA2164S II - GENERAL DESCRIPTION (continued) Figure 7 : Power Supply Start-up VCC(START) TEA2164S VCC Voltage 0 VCC(STOP) t tBURST Collector Current Envelop 0 t Tch Tch 1s (typ.) T1 0.3s (typ.) B T1 b b b b Regulated Standby 2164S-10.EPS B TSTART-UP = Tch + T1 T1 : necessary time for voltage setting-up II.4 - Abnormal conditions : safety functions Overvoltage Protection When VCC exceeds VCC max, an internal flip-flop stops output conduction signals. The circuit will start again after the capacitor C1 discharge ; it means : after loss of synchronization or after VCC stop crossing (Figure 8). In flyback converters, this function protects the power supply against output voltage runaway. Under Voltage Lock-out The TEA2164S control circuit stops operating when VCC goes under VCC stop. Power Limitation, Current Protection, Long Duration Overload Protection - Output power limitation : by a pulse by pulse collector current limitation the TEA2164S limits the maximum output power. VCM1 is the corresponding voltage threshold, its detection is memorized up to the next period. - Current protection (transistor protection) Under particular conditions a hard overload or short circuit may induce a flux runaway in spite of the current limitation (VCM1). The TEA2164S control circuit features a second 8/16 current protection, VCM2. When this threshold is reached an internal flip-flop memorizes it and output conduction signals are inhibited. The circuit will send base drives again after capacitor C1 discharge (Figure 8). - Long duration overload protection : (Figure 9) An overload is detected when the sense-voltage on Pin 11 reaches VCM3 before a negative pulse has been applied to Pin 6. In this case the capacitor C2 (connected to Pin 3) is charged with I3 ch up to the end of the period and discharged with I3 disch until a next VCM3 detector. By this way in case of long duration overload, the capacitor keeps charging at each period and its voltage encreases gradually. When the voltage on Pin 3 exceeds VC2, the TEA2164S control circuit stops sending base drives and memorizes this event. No restart is allowed as long as Vpin 3 is higher than VC2 and VCC higher than 4.8V. * Remark : - The harder is the overload the faster is the protection - The capacitor keeps charging between two burst after VCM2 detection. TEA2164S II - GENERAL DESCRIPTION (continued) Figure 8 : Overvoltages Lock-out VCC > VCC(Max.) IC > ICM2 S S Q 1 : discharge R R VCC STOP CROSSING 2164S-11.EPS BURST OSCILLATOR R OUTPUT FLIP-FLOP Synchro ”off” Figure 9 : Long Duration Overload Monitoring Circuit I3 ch. + I3 disch. Q S 1 : VCM3 detection before negative pulse occurence R sawtooth return C2 3 I3 disch. S VC2 R Q 2164S-11.EPS VCC < 4.8V I3 dischr. = 0 in burst mode Figure 10 : Long Duration Overload Detection ICM1 Collector Current Envelop 0 VC2 Capacitor C2 Voltage 0 TEA2164S VCC Voltage 0 2164S-13.EPS VCC(START) VCC(STOP) Overload 9/16 TEA2164S II - GENERAL DESCRIPTION (continued) Figure 11 : Repetitive Over-current Protection ICM2 Collector Current Envelop t 0 Tburst Capacitor C2 Voltage 2164S-14.EPS VC2 t 0 III - SWITCHING OSCILLATOR AND SYNCHRONIZATION III.1. Switching oscillator When the TEA2164S control circuit operates in burst mode, the switching frequency is fixed by the free frequency oscillator. The period is determined by two external components CO and RO. In order to avoid any erratic conduction of the power transistor, the first synchronizationpulse will arrive simultanously with the sawtooth return of the TEA2164S oscillator. To get synchronization the free frequency must be higher than the synchronization frequency. III.2. Synchronization When the master-circuit starts to send pulses both oscillators are not synchonuous. TO < Tsync. < 1.50 TO Figure 12 : Free Frequency Running TR 5V V8 2.74V CURRENT MIRROR 1.66V 15kΩ IO IO 0 Tcharge 3.2V RR 1kΩ 7 RO 7.5kΩ TR TO TR 8 9.1kΩ CO TO ~ Tcharge + TR TO ~ 0.4 ROCO + 0.47 COR R RR ~ 1000Ω Q 10/16 13.4kΩ 2164S-15.EPS CO in Farad, R O in Ohms Q conductingin burst mode TEA2164S III - SWITCHING OSCILLATOR AND SYNCHRONIZATION (continued) Figure 13 : Synchronization Pulse Shaper and Synchronization 2 VD To Output Flip-Flop Reset MONO 6 2 VD + 0.4V Q S Q MONO OSCILLATOR SECTION Pulse Transformer R Sawtooth Return 9.1kΩ 13.4kΩ 2164S-16.EPS Q Synchro ”OFF” VD ~ 0.65V Figure 14 : Operation after Synchronization 1 - NORMAL OPERATION Synchro Pulse 2 - NEGATIVE PULSE MISSING Synchro Pulse ∆T 3.3V V8 V8 2.66V 1.66V 3.3V 2.5V 1.66V 0V Base Current Base Current ∆T : Synchronization Window Transistor turn-off is ensured by VCM1 current limitation crossing or by an internal t ON(Max.) limitation set by a 2.5V threshold. 3 - ERRATIC POSITIVE PULSES P1 Synchro Pulse 4 - fsynchro < 0.65 fO P2 P1 Synchro Pulse ∆T 3.3V 1.66V 2.66V V8 1.66V 0V S1 Base Current Base Current P1 and P2 are masked dur to the synchronization window. Signal S1 triggers burst oscillator capacitor discharge. The TEA2164S restarts in burst mode. 0V 2164S-17.EPS V8 11/16 TEA2164S IV - MAXIMUM DUTY CYCLE LIMITATION Burst mode : The maximum duty cycle is controlled by the voltage on Pin 9 (Figure 15). Synchronized mode : Normally the maximum duty cycle is set by the master circuit. However the maximum conducting time will never exceed the value given by the comparison of the oscillator wave-form with the 2.5V internal threshold. - After the starting pulse I BON, the base current is proportional to the collector current. The current gain is easily fixed by a resistor RB (Figure 16). - A fast and safe transistor turn-off is realized by a fast positive base current cut-off and by applying a negative base drive which draws stored carriers. Atypical 0.7s delay prevents from cross-conduction of positive and negative output stages. V - OUTPUT STAGE TEA2164S output stage has been designed to drive switching bipolar transistor. - Each base drive begins with a positive pulse IBON that realizes an efficient transistor turn-on. Remark : In order to reduce power dissipation on the positive output stage with the low gain transistors, for high base currents the positive output stage operates in saturated mode (Figure 17). This can be achieved by using a resistor between VCC and V+. Figure 15 : Maximum Duty Cycle Limitation Synchro ”ON” 6 IO S OUTPUT FLIP-FLOP 9 e V1 2.5V R V1 = 4.5V - 1.25 x (e) ; IO = 2164S-18.EPS OSC 2.5V RO Figure 16 : Output Stage Architecture and Base Drive IB 16 I BON 15 CURRENT MIRROR I Cmax IB t IC 14 Virtual Ground t 2 Pins 4-5-12-13 RS IC RB IB @ GF IC GF = 12/16 IC IB = RS = RB 1000 x R S V CM1 I Cmax 2164S-19.EPS V- TEA2164S V - OUTPUT STAGE (continued) Figure 17 : Power Supply Start-up and Normal Operation 0 VCC(START) VCC(STOP) Tb Collector Current Envelop t Burst normal duration 0 1 Output Voltage 2 Master Circuit 0 Output t 1 2 2164S-20.EPS TEA2164S VCC Voltage t Power Supply Start-up Normal Mode VI - MONITOR APPLICATIONS In most of monitor applications, the power supply must start-up under full load conditions and the stand -by mode is no longer useful. The energy of the starting burst must be high enough to ensure start-up, then the capacitor C1 must be higher in these applications than on TV application (typ. : 1µF). 13/16 13 12 10 5 4 1nF 3 11 6.8Ω 1 2 TEA2164S 4.7µF 9 7 12kΩ 8 110kΩ 2164S-21.EPS 100Ω 14 6 2µH 10Ω 220mF 100kΩ (2W) 1N4444 16 15 2 x 47µF (385V) 390Ω Primary Ground (connected to mains) Secondary ground (isolated from mains) 2.2µF 1.2nF 470kΩ 330Ω 2.2Ω 2.2Ω 0.27Ω 100Ω 47µF 3 x 1N404 BA157 BA157 BU508A 2 1 7 9 6 10µF 220Ω + VCC 470µF 1000µF 100µF + VCC 1N4148 24 20 7 22 19 18 17 15 16 100nF VIDEO INPUT 27 23 VCR Switch 13V 2N1711 MUTE OUT & 50/60Hz IDENTIFICATION 8.2kΩ AGC PULSE 15kW 1.5nF 15nF 330Ω 5.6kW 1.8kΩ 220Ω 3.9kΩ 5.6kW 503 kHz 150pF +25V 470kΩ 10kW 680Ω 27Ω 33kΩ +135V / 0.6A Horizontal Phase Adjust BY218 BY218 BY218 4.7µF + VCC 470Ω BA159 2.2nF 22 21 19 20 13 22nF 100nF 300kΩ 220Ω OREGA G.4173.04 3.3nF 220nF 3 14 22nF 220 µF + VCC 8 26 25 1.5kΩ SMPS Output Voltage Adjust 11 9 28 21 5 3 1 2 6 4 10 100kΩ 220pF 10kΩ 1kΩ 220pF 150kΩ SUPER SANDCASTLE LINE OUTPUT FLYBACK 12 TEA2029C 13 3.32kΩ (1%) 100nF 4 x 1N4007 4.7nF 1kΩ 1kΩ 220VAC MAINS INPUT 1kΩ 820Ω 220Ω 100nF 1nF BA157 1kΩ 33Ω Frame Phase Adjust 220Ω 6.8kΩ 3.3kΩ 3.3kΩ 82kΩ 220Ω 200V +24V 4.7Ω Frame Amplitude Adjust FRAME YOKE 120µH 60W 0.47µF LINE FLYBACK 47nF ESM 740 EHT TRANSFORMER 500µH LINE YOKE E/W CORRECTION 2.2kΩ 220kΩ 470nF 2.7MΩ 820Ω 1kΩ 390Ω 14/16 6.8kΩ FUSE 1.6A +24V +200V TEA2164S COMPLETE APPLICATION DIAGRAM (SMPS + DEFLECTION) (with stand-by function) 9 8 10 7 2164S-22.EPS f : 32kHz POUT : 120W 100kΩ 1% 100nF 1nF 560 pF 2% 6 4 12 13 68kΩ 1nF 1 11 16V 4.7µ F 3 TEA2164S 5 P2 22kΩ 14 2 5.6Ω (1W) 47µF BZX85C-3V0 220µ F 25V 4.7Ω (2W) BA157 0.24Ω (1W) 2.2µF 18Ω 120kΩ (2W) 1N4148 16 15 150µF (385V) 330Ω 330Ω VIN = 220 VAC ± 20% 4 x 1N4007 100Ω BA159 SGSF344 7 9 6 3 21 22 17 14 19 20 13 Pulse Transformer 2.7nF 1kV 470Ω (8W) G4453-02 270Ω BY218-100 BY218-100 PLR811 BY218-600 10µF 16V 1000µ F (40V) 1000µ F (25V) 470µF (25V) 100µF (250V) 3 2 6 100kΩ 7 8 2.2kΩ 6.8kΩ 150pF 47nF Stand-by Control 1N4148 1 5 75kΩ TEA5170 4 560 pF 560 pF BC550C 25V 10kΩ 7.5V 100kΩ P1 100kΩ Sync. Input 135V TEA2164S STAND-ALONE 32kHz POWER SUPPLY ELECTRICAL DIAGRAM 15/16 TEA2164S PM-DIP16.EPS PACKAGE MECHANICAL DATA 16 PINS - PLASTIC POWERDIP a1 B b b1 D E e e3 F I L Z Min. 0.51 0.85 Millimeters Typ. Max. 1.40 Min. 0.020 0.033 0.50 0.38 Inches Typ. Max. 0.055 0.020 0.50 20.0 0.015 8.80 2.54 17.78 0.020 0.787 0.346 0.100 0.700 7.10 5.10 3.30 0.280 0.201 0.130 1.27 0.050 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1998 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 16/16 DIP16PW.TBL Dimensions