TEA2019 CURRENT MODE SWITCHING POWER SUPPLY CONTROL CIRCUIT . . .. . .. . . DIRECT DRIVE OF THE EXTERNAL SWITCHING TRANSISTOR POSITIVE AND NEGATIVE OUTPUT CURRENTS UP TO 0.5A CURRENT LIMITATION TRANSFORMER DEMAGNETIZATION AND POWER TRANSISTOR SATURATION SENSING FULL OVERLOAD AND SHORT-CIRCUIT PROTECTION PROPORTIONAL BASE CURRENT DRIVING LOW STANDBY CURRENT BEFORE STARTING (1.6mA) SYNCHRONIZATION CAPABILITY WITH INTERNAL PLL THERMAL PROTECTION Due to its current mode regulation, the TEA2019 facilitates design of power supplies with following features : High stability regulation loop. Automatic input voltage feed-forward in discontinuous mode fly-back. Automatic pulse-by-pulse current limitation. Typical applications : Video Display Units, TV sets, typewriters, micro-computers and industrial applications. For more details, see application note AN406/0591. .. . DIP 14 (Plastic package) DESCRIPTION The TEA2019 is an 14-pin DIP low cost integrated circuit designed for the control of switch mode power supplies. It has the same basic functions as the TEA2018Abut with synchronization capability by internal PLL. It is particularly suitable for applications where oscillator synchronization is required. ORDER CODE : TEA2019 PIN CONNECTIONS 1 14 NEGATIVE SUPPLY (OUTPUT STAGE) AUXILIARY OUTPUT SUPPLY 2 13 SUBSTRATE POSITIVE SUPPLY VOLTAGE 3 12 I C SAMPLE (NEGATIVE) SATURATION SENSING 4 11 GROUND DEMAGNETIZATION SENSING 5 10 OSCILLATOR CAPACITOR ERROR AMPLIFIER NON-INVERTING INPUT 6 9 OSCILLATOR REFERENCE CURRENT 7 8 PLL OUTPUT SYNCHRONIZATION INPUT August 1992 2019-01.EPS OUTPUT 1/7 TEA2019 14 V 13 Substrate 3.2V 12 I SENSE 11 Ground R & 1 V REF 2019-02.EPS Feed-back 6 TEA2019 -1V VOLTAGE LIMITATION x 50 80% DUTY CYCLE LIMITATION V CC Ct 10 OSCILLATOR Rt 9 PHASE LOCKED LOOP Sync. 7 THERMAL SHUT-DOWN S Sampling Pulse 01.V Demagnetization Sensing V CC ”good” Bias & FLIP FLOP Q 4 V CE Monitoring 1 IC RECOPY Q SWITCH 3 V CC V CC 5 PLL Out 8 C o mp ara tor IS V REF = 2.4V Undervoltage DELAY 200ms 2 V AUX 1 Output BLOCK DIAGRAM Symbol + V CC V(aux) – V CC IO (peak) II Tj Toper Tstg 2/7 Parameter Positive Supply Voltage Auxiliary Output Supply Voltage Negative Supply Voltage Peak Output Current (duty cycle < 5%) Input Current Pins 4-5 Junction Temperature Operating Ambient Temperature Range Storage Temperature Range Value 15 15 –5 ±1 ±5 150 – 20, + 70 – 40, + 150 Unit V V V A mA °C °C °C 2019-01.TBL ABSOLUTE MAXIMUM RATINGS THERMAL DATA Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Value 80 Unit °C/W 2019-02.TBL TEA2019 ELECTRICAL OPERATING CHARACTERISTICS Tamb = + 25oC, potentials referenced to ground (unless otherwise specified) τmax AV + II V(REF) ∆V(REF) ∆T TOSC ∆fOSC ∆T ∆fOSC ∆VCC ton(min) Parameter Positive Supply Voltage Negative Supply Voltage + Minimum positive supply voltage required for starting (V CC rising) Minimum positive voltage below which device stops operating (V+CC falling) + Hysteresis on V CC Threshold + Standby Supply Current Before Starting [V CC < VCC(start)] Current Limitation Threshold Voltage (pin 12) Collector Current Sensing Input Resistance Demagnetization Sensing Threshold Demagnetization Sensing Input Current (pin 5 grounded) Maximum Duty Cycle Error Amplifier Gain Error Amplifier Input Current (non-inverting input) (pin 6) Internal Reference Voltage Min. 6.6 –1 Typ. 8 –3 6 4.2 4.9 0.7 1.1 1 –1100 –1000 1000 75 100 1 70 80 50 2 2.3 2.4 125 2.5 –4 Reference Voltage Temperature Drift 10 Oscillator Free-running Period ( R = 59kΩ, C = 1.5nF) Oscillator Frequency Drift with Temperature Max. 15 –5 6.6 5.6 1.6 1.6 –880 + (V CC 60 = + 8V) Oscillator Frequency Drift with V+CC (+ 8V < V+CC < + 14V) Minimum Conducting Time (Ct = 1nF) 65 Unit V V V V V mA mV Ω mV µA % µA V V/°C 70 µs 0.05 %/°C 0.5 %/V 2 µs 2019-03.TBL Symbol + V CC VCC VCC(start) VCC(stop) + ∆ V CC ICC(sb) Vth (Ic) R(Ic ) IS Typ. 0.5 20 Max. 2.5 Unit V kΩ Min. Typ. 100 8 8 Max. Unit Hz/µA µs µs Typ. 3.2 Max. Unit V µA kΩ Max. Unit V V A kHz 2019-04.TBL Min. 2019-05.TBL Parameter Peak to Peak Sawtooth Voltage Input Impedance 2019-06.TBL Symbol V7pp R (7) 2019-07.TBL SYNCHRONIZATION INPUT (pin 7) PLL CHARACTERISTICS (see Test Circuit) Symbol ∆T Parameter Frequency Sensitivity Capture Range (TOSC = 64µs Typ.) TSYN max - TOSC TOSC - TSYN min 5.5 4.5 SATURATION SENSING (pin 4) Symbol V(4) I(4) Parameter Input Threshold Input Current (V4 > 3.2V) Input Internal Resistance Min. 50 1 RECOMMENDED OPERATING CONDITIONS Symbol + V CC VCC IO Foper Parameter Positive Supply Voltage Negative Supply Voltage Output Current Operating Frequency Min. Typ. 8 3 0.5 30 3/7 TEA2019 TYPICAL CIRCUIT V6 V5 V3 470Ω 22nF 10Ω 10nF AS1 4.7µF 22nF 8.2kΩ 10nF 7 6 5 4 3 2 1 10kΩ RAMP GENERATOR IC TEA2019 0V 8 22nF 56kΩ 10 12 13 14 -1V 4.7µF 59kΩ 1% 1.5nF GENERAL DESCRIPTION (see application note AN406/0591) Operating Principles (Figure 1) On every period, the beginning of the conduction time of the transistor is triggered by the fall of the oscillator saw-tooth which acts as clock signal. The period Tosc is given by : Tosc ≈ 0.69 Ct (Rt + 2000) (Tosc in seconds, Ct in Farad, Rt in Ω) The end of the conduction time is determined by a signal issued from comparing the following signals. a) the sawtooth waveform representing the collector current of the switching transistor, sampled across the emitter shunt resistor. b) the output of the error amplifier. Base Drive • Fast turn-on On each period, a current pulse ensures fast transistor switch-on. This pulse performs also the ton(min) function at the beginning of the conduction. • Proportional base drive In order to save power, the positive base current after the starting pulse becomes an image of the collector current. IC The ratio is programmed as follows (Figure 2). IB IC RB = IB RE V12 V14 Figure 1 : Current Mode Control Vi OUTPUT FILTER FLIP-FLOP OSCILLATOR S ERROR AMPLIFIER IC Q V REF ERROR SIGNAL R COMPARATOR Re I C SENSE OSCILLATOR SAWTOOTH t I C (sample) Error Signal t FLIP-FLOP OUTPUT t 2019-05.EPS / 2019-04.EPS V10 47nF 2019-03.EPS 100Ω 3.3nF 4/7 11 LOAD 3.9kΩ 9 TEA2019 • Efficient and fast switch-off When the positive base drive is removed, 1s (typically) will elapse before the application of negative current therefore allowing a safe and rapid collector current fall. Safety Functions • Overload & short-circuit protection When the voltage applied to pin 12 exceeds the current limitation thershold voltage [Vth(Ic)], the output flip-flop is reset and the transistor is turned off. The shunt resistor Re must be calculated so as to obtain the current limitation threshold on pin 12 at the maximum allowable collector current. • Demagnetization sensing This function disables any new conduction cycle of the transistor as long as the core is not completely demagnetized. When not used, pin 5 must be grounded. • ton(max) Outside the regulation area and in the absence of current limitation, the maximum conduction time is set at about 70% of the period. • ton(min) A minimum conducting time is ensured during each period (see Figure 2). • Supply voltage monitoring The TEA2019 will stop operatingif VCC+ on Pin 3 falls below the threshold level VCC(stop). Figure 2 IC COLLECTOR CURRENT I C t 0 IC IB t on(min) RB BIAS CURRENT 1 IB IB 12 Starting Process (Figure 3) Prior to starting, a low current is drawn from the high voltage source through a high value resistor. This current charges the power supply storage capacitor of the device. No output pulses are available before the voltage on pin 3 has reached the threshold level [VCC(start), V+CC rising]. During this time the TEA2019 draws only 1mA (typically). When the voltage on pin 3 reaches this threshold base drive pulses appear. The energy drawn by these pulses tends to discharge the power supply storage capacitor. However a hysteresis of about 1.1V (typically) (∆ VCC) is implemented to avoid the device from stopping. Re IC t 0 2019-06.EPS Re RB Figure 3 : Normal TEA2019 Start up Sequence V CC V CC (start) 6V 4.9V V CC V CC (stop) t 5/7 2019-07.EPS TEA2019 TEA2019 The TEA2019 has some additional capabilities compared to the TEA2018A : voltage in order to reduce the I.C. power dissipation. For low power applications, the circuit can be normally supplied by connecting pins 2 and 3 together. • In order to protect the substrate (pin 13) from the parasitic voltage peaks produced by negative output current peaks at pin 14, the substrate (pin 13) is internally separated from the negative supply (pin 14). They must be externally connected together. • The switching transistor saturation voltage can be monitored at pin 4. To achieve this, a high voltage diode must be connected between the collector of the switching transistor and pin 4. Also a resistor must be connected from pin 4 to V+CC (see application diagram). This arrangement is useful when the chosen value of base current is very low and as a consequence the saturationvoltage will be high. In thisevent, when VCE(sat) increases above 2.5V, the base current is interrupted before the normal end of the period. Remark : the TEA2019 can also operate without this protection. • The oscillator charge current its supplied through an internal current generator,programmed externally - instead of using an external charging resistor. The sawtooth so obtained is linear. • The oscillator can be synchronized through an internal PLL circuit. This feature provides synchronization between the external sync pulse and the end of the switching transistor current. The sync pulse can be for example the fly-back pulse of a TV horizontal sweep circuit. As indicated in the application diagram, this pulse is applied first to a R.C. network to obtain a low voltage sawtooth and then to pin 7 of the circuit. The PLL output (pin 8) supplies a correction current to pin 9 through an external resistor, so as to maintain the oscillator at the correct frequency (refer to application note AN406/0591 for detailed information). • In the TEA2019, the power supply of the positive output stage is separated from the main power supply, so that it can be supplied from a lower TYPICAL APPLICATION BYT11-800 47µF 385V 4 x 1N4007 1N4148 18 Ω Sync. Pulse 0.1µF 3.9Ω 1N4148 n3 10kΩ 82kΩ 120kΩ 1W 470µF 10µF BYT11-800 n0 BYT 11-100 1.8kΩ 0.1µF 7 6 5 C2 33nF 4 n2 10Ω 10kΩ 10kΩ 3.3Ω 3 2 1 24V 0.5A 470µF 40V 1kΩ 3W BYT11-100 BUV 46A BYT11-1000 RF Filter 2 x 12mH 47nF 120V 0.4A 100µF n1 160V 680Ω 3W 2.2nF TEA2019 0.5A 8 9 10 11 12 13 0.47Ω 14 100Ω 56kΩ 3.9kΩ 3.3nF 56kΩ 22nF 1.5nF 10µF 4.7Ω Primary Ground Secondary Ground .. . 6/7 PMAX = 60W Free-running Frequency : 15kHz 155VRMS ≤ VAC ≤ 250VRMS . . 3 x 1N4001 120V ± 3%, 0.4A 24V ±3%, 0.5A Monitoring Outputs: VCE 2019-08.EPS Mains Input TEA2019 I b1 L a1 PACKAGE MECHANICAL DATA 14 PINS - PLASTIC DIP b B e E Z Z e3 D 8 1 7 a1 B b b1 D E e e3 F i L Z Min. 0.51 1.39 Millimeters Typ. Max. 1.65 Min. 0.020 0.055 0.5 0.25 Inches Typ. 0.065 0.020 0.010 20 0.787 8.5 2.54 15.24 0.335 0.100 0.600 7.1 5.1 0.280 0.201 3.3 1.27 Max. DIP14.TBL Dimensions PM-DIP14.EPS F 14 0.130 2.54 0.050 0.100 Information furnished is believed to be accurate and reliable. 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