TI TL751L05CD

TL750L, TL751L SERIES
LOW-DROPOUT VOLTAGE REGULATORS
www.ti.com
SLVS017S – SEPTEMBER 1987 – REVISED AUGUST 2005
FEATURES
•
•
•
Very Low Dropout Voltage, Less Than 0.6 V at
150 mA
Very Low Quiescent Current
TTL- and CMOS-Compatible Enable on
TL751L Series
60-V Load-Dump Protection
OUTPUT
COMMON
COMMON
NC
1
8
2
7
3
6
4
5
INPUT
COMMON
COMMON
NC
Reverse Transient Protection Down to –50 V
Internal Thermal-Overload Protection
Overvoltage Protection
Internal Overcurrent-Limiting Circuitry
Less Than 500-µA Disable (TL751L Series)
TL750L . . . KTE PACKAGE
(TOP VIEW)
TL750L . . . KC PACKAGE
(TOP VIEW)
COMMON
TL750L . . . D PACKAGE
(TOP VIEW)
•
•
•
•
•
OUTPUT
COMMON
INPUT
COMMON
•
OUTPUT
COMMON
INPUT
NC − No internal connection
TL751L . . . D PACKAGE
(TOP VIEW)
OUTPUT
COMMON
COMMON
NC
1
8
2
7
3
6
4
5
INPUT
COMMON
COMMON
ENABLE
NC − No internal connection
TL751L . . . P PACKAGE
(TOP VIEW)
OUTPUT
NC
NC
NC
1
8
2
7
3
6
4
5
INPUT
NC
COMMON
ENABLE
TL750L . . . LP PACKAGE
(TO-92, TO-226AA)
(TOP VIEW)
INPUT
COMMON
OUTPUT
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
The TL750L and TL751L series of fixed-output voltage regulators offer 5-V, 8-V, 10-V, and 12-V options. The
TL751L series also has an enable (ENABLE) input. When ENABLE is high, the regulator output is placed in the
high-impedance state. This gives the designer complete control over power up, power down, or emergency
shutdown.
The TL750L and TL751L series are low-dropout positive-voltage regulators specifically designed for
battery-powered systems. These devices incorporate overvoltage and current-limiting protection circuitry, along
with internal reverse-battery protection circuitry to protect the devices and the regulated system. The series is
fully protected against 60-V load-dump and reverse-battery conditions. Extremely low quiescent current during
full-load conditions makes these devices ideal for standby power systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerFLEX is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1987–2005, Texas Instruments Incorporated
TL750L, TL751L SERIES
LOW-DROPOUT VOLTAGE REGULATORS
www.ti.com
SLVS017S – SEPTEMBER 1987 – REVISED AUGUST 2005
ORDERING INFORMATION
TJ
VO TYP
AT 25°C
PACKAGE (1)
PowerFLEX™ – KTE
TL750L05CKTER
Tube of 75
TL750L05CD
Reel of 2500
TL750L05CDR
Tube of 75
TL751L05CD
Reel of 2500
TL751L05CDR
Bulk of 1000
TL750L05CLP
Reel of 2000
TL750L05CLPR
Tube of 50
TL750L05CKC
Tube of 75
TL750L08CD
Reel of 2500
TL750L08CDR
TO-226/TO-92 – LP
Bulk of 1000
TL750L08CLP
750L08C
PDIP – P
Tube of 50
TL751L10CP
TL751L10C
Tube of 75
TL750L10CD
Reel of 2500
TL750L10CDR
Tube of 75
TL751L10CD
Reel of 2500
TL751L10CDR
Bulk of 1000
TL750L10CLP
Reel of 2000
TL750L10CLPR
Tube of 75
TL750L12CD
Reel of 2500
TL750L12CDR
Tube of 75
TL751L12CD
Reel of 2500
TL751L12CDR
Bulk of 1000
TL750L12CLP
5V
TO-226/TO-92 – LP
TO-220 – KC
0°C to 125°C
10 V
SOIC – D
SOIC – D
TO-226/TO-92 – LP
12 V
SOIC – D
TO-226/TO-92 – LP
(1)
(2)
TL750L05C
50L05C
51L05C
750L05C
TL750L05C
50L08C
50L10C
51L10C
750L10C
50L12C
51L12C
750L12C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
For the most current ordering information, see the Package Option Addendum at the end of this data sheet.
DEVICE COMPONENT COUNT
2
TOP-SIDE MARKING
Reel of 2000
SOIC – D
8V
ORDERABLE PART NUMBER (2)
Transistors
20
JFETs
2
Diodes
5
Resistors
16
TL750L, TL751L SERIES
LOW-DROPOUT VOLTAGE REGULATORS
www.ti.com
SLVS017S – SEPTEMBER 1987 – REVISED AUGUST 2005
Absolute Maximum Ratings
(1)
over operating junction temperature range (unless otherwise noted)
MIN
MAX
Continuous input voltage
Transient input voltage (2)
t ≤ 100 ms
Transient reverse input voltage
TJ
Operating virtual junction temperature
Lead temperature
Tstg
(1)
(2)
V
60
V
–15
V
TA = 25°C
Continuous reverse input voltage
1,6 mm (1/16 in) for 10 s
Storage temperature range
–65
UNIT
26
–50
V
150
°C
260
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The transient input voltage rating applies to the waveform shown in Figure 1.
Package Thermal Data (1)
(1)
PACKAGE
BOARD
θJC
θJA
PDIP (P)
High K, JESD 51-7
57°C/W
85°C/W
PowerFLEX™ (KTE)
High K, JESD 51-5
3°C/W
23°C/W
SOIC (D)
High K, JESD 51-7
39°C/W
97°C/W
TO-226/TO-92 (LP)
High K, JESD 51-7
55°C/W
140°C/W
TO-220 (KC)
High K, JESD 51-5
3°C/W
19°C/W
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
Recommended Operating Conditions
over recommended operating junction temperature range (unless otherwise noted)
VI
Input voltage
VIH
High-level ENABLE input voltage
MIN
MAX
TL75xL05
6
26
TL75xL08
9
26
TL75xL10
11
26
TL75xL12
13
26
TL75xLxx
2
15
TJ = 25°C
TL75xLxx
–0.3
0.8
TJ = 0°C to 125°C
TL75xLxx
–0.15
0.8
UNIT
V
V
VIL (1)
Low-level ENABLE input voltage
IO
Output current
TL75xLxx
0
150
mA
TJ
Operating virtual junction temperature
TL75xLxxC
0
125
°C
(1)
V
The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
ENABLE voltage levels and temperature only.
3
TL750L, TL751L SERIES
LOW-DROPOUT VOLTAGE REGULATORS
www.ti.com
SLVS017S – SEPTEMBER 1987 – REVISED AUGUST 2005
TL75xL05 Electrical Characteristics (1)
VI = 14 V, IO = 10 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
Output voltage
Input regulation voltage
VI = 6 V to 26 V, IO = 0 to 150 mA
TJ = 0°C to 125°C
TYP
4.8
5
4.75
VI = 6 V to 26 V
6
30
IO = 5 mA to 150 mA
60
65
20
0.2
IO = 150 mA
0.6
f = 10 Hz to 100 kHz
VI = 6 V to 26 V, IO = 10 mA, TJ = 0°C to 125°C
1
ENABLE ≥ 2 V
mV
mV
V
µV
500
10
V
dB
50
IO = 10 mA
IO = 150 mA
(1)
5.2
5.25
10
VI = 8 V to 18 V, f = 120 Hz
Input bias current
UNIT
MAX
5
Output regulation voltage
Output noise voltage
TJ = 25°C
MIN
VI = 9 V to 16 V
Ripple rejection
Dropout voltage
TL750L05
TL751L05
TEST CONDITIONS
12
2
mA
0.5
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects
must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF capacitor,
with equivalent series resistance of less than 0.4 Ω, across the output.
TL75xL08 Electrical Characteristics (1)
VI = 14 V, IO = 10 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
Output voltage
Input regulation voltage
VI = 9 V to 26 V, IO = 0 to 150 mA
TJ = 0°C to 125°C
8
8.32
7.6
8.4
20
50
60
65
40
0.2
IO = 150 mA
0.6
f = 10 Hz to 100 kHz
VI = 9 V to 26 V, IO = 10 mA, TJ = 0°C to 125°C
ENABLE ≥ 2 V
V
mV
dB
80
IO = 10 mA
IO = 150 mA
4
7.68
25
IO = 5 mA to 150 mA
(1)
MAX
10
VI = 11 V to 21 V, f = 120 Hz
Input bias current
TYP
VI = 9 V to 26 V
Output regulation voltage
Output noise voltage
TJ = 25°C
UNIT
MIN
VI = 10 V to 17 V
Ripple rejection
Dropout voltage
TL750L08
TL751L08
TEST CONDITIONS
mV
V
µV
500
10
12
1
2
mA
0.5
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects
must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF capacitor,
with equivalent series resistance of less than 0.4 Ω, across the output.
TL750L, TL751L SERIES
LOW-DROPOUT VOLTAGE REGULATORS
www.ti.com
SLVS017S – SEPTEMBER 1987 – REVISED AUGUST 2005
TL75xL10 Electrical Characteristics
(1)
VI = 14 V, IO = 10 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
Output voltage
Input regulation voltage
VI = 11 V to 26 V, IO = 0 to 150 mA
TYP
MAX
TJ = 25°C
9.6
10
10.4
TJ = 0°C to 125°C
9.5
25
VI = 11 V to 26 V
30
60
VI = 12 V to 22 V, f = 120 Hz
IO = 5 mA to 150 mA
60
65
50
0.2
IO = 150 mA
0.6
f = 10 Hz to 100 kHz
VI = 11 V to 26 V, IO = 10 mA, TJ = 0°C to 125°C
1
ENABLE ≥ 2 V
(1)
mV
mV
V
µV
700
10
V
dB
100
IO = 10 mA
IO = 150 mA
Input bias current
10.5
10
Output regulation voltage
Output noise voltage
UNIT
MIN
VI = 12 V to 19 V
Ripple rejection
Dropout voltage
TL750L10
TL751L10
TEST CONDITIONS
12
2
mA
0.5
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects
must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF capacitor,
with equivalent series resistance of less than 0.4 Ω, across the output.
TL75xL12 Electrical Characteristics (1)
VI = 14 V, IO = 10 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
Output voltage
Input regulation voltage
VI = 13 V to 26 V, IO = 0 to 150 mA
TJ = 0°C to 125°C
TYP
MAX
11.52
12
12.48
11.4
15
30
20
40
VI = 13 V to 23 V, f = 120 Hz
IO = 5 mA to 150 mA
55
50
IO = 150 mA
0.6
f = 10 Hz to 100 kHz
VI = 13 V to 26 V, IO = 10 mA, TJ = 0°C to 125°C
V
mV
dB
120
0.2
ENABLE ≥ 2 V
(1)
50
IO = 10 mA
IO = 150 mA
Input bias current
12.6
VI = 13 V to 26 V
Output regulation voltage
Output noise voltage
TJ = 25°C
UNIT
MIN
VI = 14 V to 19 V
Ripple rejection
Dropout voltage
TL750L12
TL751L12
TEST CONDITIONS
mV
V
µV
700
10
12
1
2
mA
0.5
Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects
must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF capacitor,
with equivalent series resistance of less than 0.4 Ω, across the output.
PARAMETER MEASUREMENT INFORMATION
The TL750L, TL751L series are low-dropout regulators. This means that capacitance loading is important to the
performance of the regulator because it is a vital part of the control loop. The capacitor value and its equivalent
series resistance (ESR) both affect the control loop and must be defined for the load range and temperature
range. Figure 1 shows the recommended range of ESR for a given load with a 10-µF capacitor on the output.
5
TL750L, TL751L SERIES
LOW-DROPOUT VOLTAGE REGULATORS
www.ti.com
SLVS017S – SEPTEMBER 1987 – REVISED AUGUST 2005
TYPICAL CHARACTERISTICS
TL750L05
EQUIVALENT SERIES RESISTANCE
vs
LOAD CURRENT
TRANSIENT INPUT VOLTAGE
vs
TIME
60
0.9
0.8
Potential Instability Region
0.7
0.6
0.5
0.4
0.3
Region of Best Stability
0.2
0.1
0.024
0
TA = 25°C
VI = 14 V + 46e(−t/0.230)
for t ≥ 5 ms
CL = 10-µF Tantalum Capacitor
TA = − 40°C to 125°C
V i − Transient Input Voltage − V
ESR − Equivalent Series Resistance − Ω
1.0
50
40
30
tr = 1 ms
20
10
0
Potential Instability Region
10
80
120
0
0
150
100
200
300
400
500
600
t − Time − ms
IL − Load Current − mA
Figure 1.
Figure 2.
TL750L05
INPUT CURRENT
vs
INPUT VOLTAGE
TL750L12
INPUT CURRENT
vs
INPUT VOLTAGE
60
40
35
50
II − Input Current − mA
II − Input Current − mA
30
25
20
15
40
30
20
10
10
5
0
0
0
1
2
3
4
VI − Input Voltage − V
Figure 3.
6
5
6
0
2
4
6
8
10
VI − Input Voltage − V
Figure 4.
12
14
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9166901Q2A
OBSOLETE
LCCC
FK
20
TBD
Call TI
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5962-9166901QPA
OBSOLETE
CDIP
JG
8
TBD
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TL750L05CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L05CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L05CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L05CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L05CKC
NRND
TO-220
KC
3
50
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L05CKCE3
NRND
TO-220
KC
3
50
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L05CKCS
ACTIVE
TO-220
KCS
3
50
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L05CKTER
NRND
PFM
KTE
3
2000
TBD
CU SNPB
TL750L05CLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
Level-1-220C-UNLIM
N / A for Pkg Type
TL750L05CLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L05CLPM
OBSOLETE
TO-92
LP
3
TBD
Call TI
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TL750L05CLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L05CLPRE3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L05CP
OBSOLETE
PDIP
P
8
TBD
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TL750L05QD
OBSOLETE
SOIC
D
8
TBD
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TL750L05QDR
OBSOLETE
SOIC
D
8
TBD
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TL750L05QKC
OBSOLETE
TO-220
KC
3
TBD
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TL750L05QLP
OBSOLETE
TO-92
LP
3
TBD
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TL750L05QP
OBSOLETE
PDIP
P
8
TBD
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TL750L08CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
TL750L08CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
TL750L08CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
TL750L08CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
TL750L08CKC
OBSOLETE
TO-220
KC
3
TBD
Call TI
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TL750L08CLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L08CLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L08CP
OBSOLETE
PDIP
P
8
TBD
Call TI
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TL750L08QD
OBSOLETE
SOIC
D
8
TBD
Call TI
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2007
Orderable Device
Status (1)
TL750L08QDR
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL750L08QKC
OBSOLETE
TO-220
KC
3
TBD
Call TI
Call TI
TL750L08QLP
OBSOLETE
TO-92
LP
3
TBD
Call TI
Call TI
TL750L10CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L10CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L10CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L10CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L10CKC
OBSOLETE
TO-220
KC
3
TBD
Call TI
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TL750L10CLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L10CLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L10CLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L10CLPRE3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TL750L10CP
OBSOLETE
PDIP
P
8
TBD
Call TI
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TL750L10QD
OBSOLETE
SOIC
D
8
TBD
Call TI
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TL750L10QDR
OBSOLETE
SOIC
D
8
TBD
Call TI
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TL750L10QKC
OBSOLETE
TO-220
KC
3
TBD
Call TI
Call TI
TL750L10QLP
OBSOLETE
TO-92
LP
3
TBD
Call TI
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TL750L10QP
OBSOLETE
PDIP
P
8
TBD
Call TI
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TL750L12CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L12CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L12CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L12CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL750L12CKC
OBSOLETE
TO-220
KC
3
TBD
Call TI
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TL750L12CLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L12CLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
TL750L12CP
OBSOLETE
PDIP
P
8
TBD
Call TI
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TL750L12QD
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL750L12QDR
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL750L12QKC
OBSOLETE
TO-220
KC
3
TBD
Call TI
Call TI
TL750L12QLP
OBSOLETE
TO-92
LP
3
TBD
Call TI
Call TI
TL750L12QP
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL751L05CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L05CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL751L05CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L05CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L05CP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
TL751L05MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
TL751L05MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
TL751L05QD
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL751L05QDR
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL751L05QP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
TL751L10CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L10CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L10CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L10CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L10CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL751L10CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL751L10QD
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL751L10QP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
TL751L12CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L12CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L12CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL751L12CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
TL751L12CP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
TL751L12MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
TL751L12MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
TL751L12QD
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL751L12QDR
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
TL751L12QP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2007
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPFM001E – OCTOBER 1994 – REVISED JANUARY 2001
KTE (R-PSFM-G3)
PowerFLEX PLASTIC FLANGE-MOUNT
0.375 (9,52)
0.080 (2,03)
0.070 (1,78)
0.365 (9,27)
0.360 (9,14)
0.050 (1,27)
0.040 (1,02)
0.350 (8,89)
0.220 (5,59)
NOM
0.010 (0,25) NOM
Thermal Tab
(See Note C)
0.360 (9,14)
0.350 (8,89)
0.295 (7,49)
NOM
0.320 (8,13)
0.310 (7,87)
0.420 (10,67)
0.410 (10,41)
1
3
0.025 (0,63)
0.031 (0,79)
0.100 (2,54)
Seating Plane
0.004 (0,10)
0.010 (0,25) M
0.005 (0,13)
0.001 (0,03)
0.200 (5,08)
0.041 (1,04)
0.031 (0,79)
0.010 (0,25)
NOM
Gage Plane
3°– 6°
0.010 (0,25)
4073375/F 12/00
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
The center lead is in electrical contact with the thermal tab.
Dimensions do not include mold protrusions, not to exceed 0.006 (0,15).
Falls within JEDEC MO-169
PowerFLEX is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSOT002A – OCTOBER 1994 – REVISED NOVEMBER 2001
LP (O-PBCY-W3)
PLASTIC CYLINDRICAL PACKAGE
0.205 (5,21)
0.175 (4,44)
0.165 (4,19)
0.125 (3,17)
DIA
0.210 (5,34)
0.170 (4,32)
Seating
Plane
0.157 (4,00) MAX
0.050 (1,27)
C
0.500 (12,70) MIN
0.104 (2,65)
FORMED LEAD OPTION
0.022 (0,56)
0.016 (0,41)
0.016 (0,41)
0.014 (0,35)
STRAIGHT LEAD OPTION
D
0.135 (3,43) MIN
0.105 (2,67)
0.095 (2,41)
0.055 (1,40)
0.045 (1,14)
1
2
3
0.105 (2,67)
0.080 (2,03)
0.105 (2,67)
0.080 (2,03)
4040001-2 /C 10/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead dimensions are not controlled within this area
D. FAlls within JEDEC TO -226 Variation AA (TO-226 replaces TO-92)
E. Shipping Method:
Straight lead option available in bulk pack only.
Formed lead option available in tape & reel or ammo pack.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSOT002A – OCTOBER 1994 – REVISED NOVEMBER 2001
LP (O-PBCY-W3)
PLASTIC CYLINDRICAL PACKAGE
0.539 (13,70)
0.460 (11,70)
1.260 (32,00)
0.905 (23,00)
0.650 (16,50)
0.610 (15,50)
0.020 (0,50) MIN
0.098 (2,50)
0.384 (9,75)
0.335 (8,50)
0.748 (19,00)
0.217 (5,50)
0.433 (11,00)
0.335 (8,50)
0.748 (19,00)
0.689 (17,50)
0.114 (2,90)
0.094 (2,40)
0.114 (2,90)
0.094 (2,40)
0.169 (4,30)
0.146 (3,70)
DIA
0.266 (6,75)
0.234 (5,95)
0.512 (13,00)
0.488 (12,40)
TAPE & REEL
4040001-3 /C 10/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Tape and Reel information for the Format Lead Option package.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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