STMICROELECTRONICS VN808SR

VN808SR
Octal channel high side driver
Features
Type
RDS(on)
Iout
VCC
VN808SR
150 mΩ
0.7 A
45 V
■
VCC/2 compatible input
■
Junction over-temperature protection
■
Case over-temperature protection for thermal
independence of the channels
■
Current limitation
■
Shorted load protection
■
Undervoltage shut-down
■
Protection against loss of ground
■
Very low stand-by current
■
Compliance to 61000-4-4 IEC test up to 4 kV
Description
The VN808SR is a monolithic device designed in
STMicroelectronics VIPower M0-3 technology,
intended for driving any kind of load with one side
connected to ground.
Figure 1.
July 2008
PowerSO-36
Active current limitation combined with thermal
shutdown and automatic restart, protect the
device against overload. In overload condition,
the channel turns OFF and back ON
automatically so as to maintain the junction
temperature between TTSD and TR. If this
condition makes the case temperature reach
TCSD, the overloaded channel is turned OFF and
restarts only when the case temperature has
decreased to TCR (see waveform 3 Figure 7 on
page 10). Non overloaded channels continue to
operate normally. The device automatically turns
OFF in the case of a ground pin disconnection.
This device is especially suitable for industrial
applications and conforms to IEC 61131.
Block diagram
Rev 4
1/17
www.st.com
17
Contents
VN808SR
Contents
1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Current, voltage conventions and internal diagram . . . . . . . . . . . . . . . 8
5
Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
VN808SR
1
Maximum ratings
Maximum ratings
Table 1.
Absolute maximum rating
Symbol
Parameter
VCC
DC supply voltage
-IGND
DC ground pin reverse current
TRAN ground pin reverse current
(pulse duration < 1 ms)
IOUT
DC output current
-IOUT
Reverse DC output current
IIN
DC Input current
VIN
Input voltage range
Value
Unit
45
V
-250
-6
mA
A
Internally limited
A
-2
A
± 10
mA
-3/+VCC
V
2000
V
VESD
Electrostatic discharge (R = 1.5 kΩ; C = 100 pF)
PTOT
Power dissipation at Tc = 25 °C
96
W
LMAX
Max inductive load (VCC = 24 V, RLOAD = 48 Ω,
TA = 100 °C)
2
H
TJ
Junction operating temperature
Internally limited
°C
TC
Case operating temperature
Internally limited
°C
-40 to 150
°C
Value
Unit
Max
1.3
°C/W
Max
50
°C/W
TSTG
Table 2.
Symbol
RthJC
RthJA
Storage temperature
Thermal data
Parameter
Thermal resistance junction-case
Thermal resistance junction-ambient
(1)
1. When mounted on FR4 printed circuit board with 0.5 cm2 of copper area (at least 35 µm think) connected
to all TAB pins.
3/17
Electrical characteristics
2
VN808SR
Electrical characteristics
(10.5 V < VCC < 32 V; -40 °C < TJ < 125 °C; unless otherwise specified)
Table 3.
Symbol
Parameter
Test conditions
VCC
Operating supply
voltage
VUSD
Undervoltage
shutdown
RON
On state resistance
IOUT = 0.5 A; TJ = 25 °C
IOUT = 0.5 A;
Supply current
OFF state; VCC = 24 V;
TCASE = 25 °C
ON state (all channels ON);
VCC = 24 V, TCASE = 100 °C
IS
ILGND
Output current at
turn-off
VCC = VSTAT = VIN = VGND = 24 V
VOUT = 0 V
IL(off)
OFF state output
current
VIN = VOUT = 0 V;
Power-on delay time
from VCC rising edge
Table 7.
td(Vccon)
Table 4.
Symbol
4/17
Power section
Min
Typ
Max
Unit
10.5
45
V
7
10.5
V
185
280
mΩ
mΩ
150
µA
12
mA
1
mA
5
µA
150
0
1
ms
Switching (VCC = 24 V)
Parameter
Test conditions
Min
Typ
Max
Unit
tON
Turn-on time
RL = 48 Ω from 80%
VOUT Figure 5.
50
100
µs
tOFF
Turn-off time
RL = 48 Ω to 10% VOUT Figure 5.
75
150
µs
dVOUT/dt(on) Turn-on voltage slope
RL = 48 Ω from VOUT = 2.4 V to
VOUT = 19.2 V Figure 5.
0.7
V/µs
dVOUT/dt(off) Turn-off voltage slope
RL = 48 Ω from VOUT = 21.6 V to
VOUT = 2.4 V Figure 5.
1.5
V/µs
VN808SR
Electrical characteristics
Table 5.
Symbol
Input pin
Parameter
VINL
Input low level
IINL
Low level input
current
VINH
Input high level
IINH
High level input
current
VI(HYST)
Input hysteresis
voltage
IIN
Table 6.
Symbol
Input current
Parameter
Case shut-down
temperature
TCR
Case reset
temperature
TCHYST
Case thermal
hysteresis
TR
VCC /2-1
V
VCC /2+1
V
VIN = VCC / 2 + 1 V
150
260
0.6
VIN = VCC = 32 V
Test conditions
µΑ
V
300
µΑ
Min
Typ
Max
Unit
125
130
135
°C
110
°C
150
175
Junction reset
temperature
135
DC Short circuit
current
VCC = 24 V; RLOAD = 10 mΩ
Turn-off output clamp
IOUT = 0.5 A; L = 6mH
voltage
°C
200
°C
°C
7
15
°C
0.7
1.7
VCC-57 VCC-52 VCC-47
A
V
Status pin
Parameter
Test conditions
IHSTAT
High level output
current
VCC = 18...32 V; RSTAT = 1 kΩ
(Fault condition)
ILSTAT
Leakage current
Normal operation; VCC = 32 V
Clamp voltage
ISTAT = 1 mA
ISTAT = -1 mA
VCLSTAT
Unit
µΑ
Junction shutdown
temperature
Ilim
Symbol
Max
80
VIN = VCC / 2 - 1 V
15
Junction thermal
hysteresis
Table 7.
Typ
7
THYST
Vdemag
Min
Protections
TCSD
TTSD
Test conditions
Min
Typ
Max
Unit
2
3
4
mA
0.1
µA
8.0
V
V
6.0
6.8
-0.7
5/17
Pin connections
3
6/17
VN808SR
Pin connections
Figure 2.
Connection diagram (top view)
Table 8.
Pin functions
Pin N°
Symbol
TAB
VCC
Positive power supply voltage
1
VCC
Positive power supply voltage
2,3,4,5
NC
Not connected
6
Input 1
Input of channel 1
7
Input 2
Input of channel 2
8
Input 3
Input of channel 3
9
Input 4
Input of channel 4
10
Input 5
Input of channel 5
11
Input 6
Input of channel 6
12
Input 7
Input of channel 7
13
Input 8
Input of channel 8
14,15,16,17,18
NC
19
GND
20
STATUS
Common open source diagnostic for over-temperature
21,22
Output 8
High-side output of channel 8
23,24
Output 7
High-side output of channel 7
Function
Not connected
Logic ground
VN808SR
Pin connections
Table 8.
Pin functions (continued)
Pin N°
Symbol
25,26
Output 6
High-side output of channel 6
27.28
Output 5
High-side output of channel 5
29,30
Output 4
High-side output of channel 4
31,32
Output 3
High-side output of channel 3
33,34
Output 2
High-side output of channel 2
35,36
Output 1
High-side output of channel 1
Function
7/17
Current, voltage conventions and internal diagram
4
Current, voltage conventions and internal diagram
Figure 3.
Current and voltage conventions
Figure 4.
Equivalent internal block diagram (same structure for all channel)
Table 9.
Truth table
Conditions
8/17
VN808SR
INPUTn
OUTPUTn
STATUS
Normal operation
L
H
L
H
L
L
Current limitation
L
H
L
X
L
L
Overtemperature
(see waveforms 3, 4 Figure 7) -> TJ > TTSD
L
H
L
L
L
H
Undervoltage
L
H
L
L
X
X
VN808SR
5
Switching time waveforms
Switching time waveforms
Figure 5.
Turn-ON and turn-OFF
Figure 6.
VCC turn-ON
9/17
Switching time waveforms
Figure 7.
10/17
Waveforms
VN808SR
VN808SR
Switching time waveforms
Figure 7.
Waveforms (continued)
11/17
Reverse polarity protection
6
VN808SR
Reverse polarity protection
A schematic solution to protect the IC against a reverse polarity condition is proposed.
This schematic is effective with any type of load connected to the outputs of the IC.
The RGND resistor value can be selected according to the following conditions to be met:
1.
RGND ≤ 600 mV / (IS in ON state max).
2.
RGND ≥ (-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
The power dissipation associated to RGNG during reverse polarity condition is:
PD = (-VCC)2/RGND
This resistor can be shared by several different ICs. In such case IS value on formula (1) is
the sum of the maximum ON-state currents of the different devices.
Please note that if the microprocessor ground and the device ground are separated then the
voltage drop across the RGND (given by IS in ON state max * RGND) produce a difference
between the generated input level and the IC input signal level. This voltage drop will vary
depending on how many devices are ON in the case of several high side switches sharing
the same RGND.
Figure 8.
Reverse polarity protection
+ Vcc
Statusi
Outputi
Inputi
RGND
(Optional)
12/17
GND
Load
VN808SR
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 10.
PowerSO-36 mechanical data
mm
inch
Dim.
Min
Typ
A
a1
Max
Min
Typ
3.60
0.10
0.30
a2
Max
0.1417
0.003
0.0118
3.30
0.1299
a3
0
0.10
0
0.0039
b
0.22
0.38
0.008
0.0150
c
0.23
0.32
0.009
0.0126
D (1)
15.80
16.00
0.622
0.6299
D1
9.40
9.80
0.370
0.3858
E
13.90
14.50
0.547
0.5709
E1 (1)
10.90
11.10
0.429
0.4370
E2
E3
2.90
5.8
6.2
0.1142
0.228
0.2441
e
0.65
0.025
e3
11.05
0.435
G
0
0.10
0.000
0.0039
H
15.50
15.90
0.610
0.6260
h
L
1.10
0.80
N
S
1.10
0.0433
0.031
10°
0°
8°
0.0433
10°
0°
8°
13/17
Package mechanical data
Figure 9.
14/17
PowerSO-36 drawings
VN808SR
VN808SR
8
Order codes
Order codes
Table 11.
Order codes
Order codes
Package
Packaging
VN808SR
PowerSO-36
Tube
VN808SR13TR
PowerSO-36
Tape and reel
15/17
Revision history
9
VN808SR
Revision history
Table 12.
16/17
Document revision history
Date
Revision
Changes
13-Sep-2005
1
Initial release
01-Mar-2007
2
Document reformatted
26-Mar-2007
3
Typo in Figure 3.
07-Jul-2008
4
Added Section 4 on page 8
VN808SR
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