STMICROELECTRONICS VNQ500PEP-E

VNQ500PEP-E
QUAD CHANNEL HIGH SIDE DRIVER
Table 1. General Features
Figure 1. Package
Type
RDS(on)
IOUT
VCC
VNQ500PEP-E
500 mΩ
0.4 A
36V
CMOS COMPATIBLE I/O’s
■ CHIP ENABLE
■ JUNCTION OVERTEMPERATURE
PROTECTION AND DIAGNOSTIC
■ CURRENT LIMITATION
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
■
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PowerSSO-12
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DESCRIPTION
The VNQ500PEP-E is a monolithic device
designed in STMicroelectronics VIPower M0-3
Technology, intended for driving any kind of load
with one side connected to ground.
Active current limitation combined with latched
thermal shutdown, protect the device against
overload.
)
s
(
ct
)
s
t(
In case of overtemperature of one channel the
relative I/O pin is pulled down.
Device automatically turns off in case of ground
pin disconnection.
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Table 2. Order Codes
bs
O
Package
PowerSSO-12
Tube
Tape and Reel
VNQ500PEP-E
VNQ500PEPTR-E
Rev. 4
June 2005
1/17
VNQ500PEP-E
Figure 2. Block Diagram
VCC
UNDERVOLTAGE
DETECTION
VCC
CLAMP
CE
GND
I/O 1
OT1
CLAMP POWER
OUTPUT 1
I/O 2
LOGIC
OT2
OUTPUT 2
CURRENT LIMITER
OUTPUT 3
I/O 3
JUNCTION TEMP.
DETECTION
OT3
c
u
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Same structure for all
channels
I/O 4
OT4
Table 3. Pin Definitions And Functions
Pin No
TAB
7,12
1
2
3
4
5
6
8
9
10
11
VCC
VCC
GND
CE
I/O 1
I/O 2
I/O 3
I/O 4
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
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Function
Positive power supply voltage
Positive power supply voltage
Logic ground
Chip Enable
Input/Output of channel 1
Input/Output of channel 2
Input/Output of channel 3
Input/Output of channel 4
High-Side output of channel 4
High-Side output of channel 3
High-Side output of channel 2
High-Side output of channel 1
)
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2/17
Symbol
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OUTPUT 4
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VNQ500PEP-E
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
41
V
VCC
DC Supply voltage
-VCC
Reverse supply voltage
-0.3
V
- IGND
DC Ground pin reverse current
- 250
mA
Internally Limited
A
-1
A
+/- 10
mA
4000
V
5000
V
73
W
Internally Limited
°C
IOUT
- IOUT
IIN
DC Output current
Reverse DC output current
DC Input current
Electrostatic discharge (R=1.5KΩ; C=100pF)
VESD
- I/On
- OUTn & Vcc
Ptot
Tj
Tstg
Power dissipation at Tc=25°C
Junction operating temperature
Storage temperature
- 55 to 150
c
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Figure 3. Configuration Diagram (Top View)
TAB = VCC
GND
CE
I/O1
I/O2
I/O3
I/O4
1
2
3
4
5
6
)
s
(
ct
VCC
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
VCC
12
11
10
9
8
7
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)
s
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°C
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Figure 4. Current and Voltage Conventions
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IS
VCC
VCC
IINn
I/On
VINn
IOUTn
OUTPUTn
VOUTn
ICE
VCE
CE
GND
IGND
3/17
VNQ500PEP-E
Table 5. Thermal Data
Symbol
Rthj-case
Rthj-amb
Parameter
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Value
1.7
Max
Max
61 (1)
Unit
°C/W
°C/W
50 (2)
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick) connected to all VCC pins.
Note: 2. When mounted on a standard single-sided FR-4 board with 8cm2 of Cu (at least 35µm thick) connected to all VCC pins.
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified)
Table 6. Power
Symbol
Parameter
VCC (**)
Test Conditions
Min.
Typ.
Max.
Unit
Operating supply voltage
5.5
13
36
V
VUSD (**)
Undervoltage shut-down
3
4
5.5
V
VOV (**)
Overvoltage shutdown
On state resistance
36
RON
IOUTn=0.25A; Tj=25°C
500
IOUTn=0.25A
1000
VCE=VI/On=0V; VCC=13V; Tcase=25°C
Supply current
IS
VCC=VCE=VI/On=VGND=13V
Output current at turn-off
IL(off) (**)
Off state output current
VI/On=VOUTn=0V
ILoff2 (**)
Off state output current
VI/On=0V, VOUTn=0V, VCC=13V;
Tcase=25°C
VOUTn=0V
Note: (**) Per channel
Table 7. Switching (VCC =13V)
)
s
(
ct
Parameter
Turn-on time
ton
u
d
o
dVOUT/
dt(on)
Turn-on voltage slope
dVOUT/
dt(off)
Turn-off voltage slope
r
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Test Conditions
0
Min.
(1)
Typ.
)
s
t(
mΩ
µA
8
mA
1
mA
5
µA
1
µA
Max.
Unit
50
µs
75
µs
RL=52Ω from VOUT=1.3V to
VOUT=10.4V (1)
0.3
V/µs
RL=52Ω from VOUT=11.7V to
VOUT=1.3V (1)
0.3
V/µs
RL=52Ω from 80% VOUT
Turn-off time
toff
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mΩ
20
c
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On state (all channels ON); VCC=13V
ILGND (**)
Symbol
V
RL=52Ω to 10% VOUT
(1)
Note: (1) see figure 5 :switching time waveforms
Table 8. Input & CE Pin
s
b
O
Symbol
Parameter
VINL
I/O low level
IINL
Low level I/O current
VINH
I/O high level
IINH
High level I/O current
VI(hyst)
I/O hysteresis voltage
VICL
Input Clamp Voltage
4/17
Test Conditions
VIN=1.25V
Min.
Typ.
Max.
Unit
1.25
V
1
µA
3.25
V
VIN=3.25V
10
0.5
IIN=1mA
IIN=-1mA
6
µA
V
6.8
-0.7
8
V
V
VNQ500PEP-E
ELECTRICAL CHARACTERISTICS (continued)
Table 9. Protections (see note 1)
Symbol
VOL
TTSD
Ilim
Vdemag
treset
Parameter
I/O low level default
Test Conditions
detection
Junction shut-down
temperature
DC Short circuit current
Turn-off output clamp
voltage
Thermal latch reset time
Min
Typ
IIN=1mA, latched thermal shutdown
150
VCC=13V; RLOAD=10mΩ
175
0.4
IOUT=0.25 A; L=50mH
VCC-41
VCC-48
Tj < TTSD (see figure 3 in waveforms)
Max
Unit
0.5
V
200
°C
0.9
A
VCC-55
V
10
µs
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles
Figure 5. Switching Time Waveforms: Turn-on & Turn-off
ton
toff
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VIN
)
s
t(
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VOUT
dVOUT/dt(on)
)
s
(
ct
tr
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s
b
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-
90%
80%
dVOUT/dt(off)
tf
10%
du
t
Figure 6. Driving Circuit
t
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MCOUT n
Rprot(*)
I/O n
OUTPUT n
Rprot(*)
MCU
Diagnostic feedback
Rprot(*)
VNQ500PEP
CE
(*) see pag. 8
5/17
VNQ500PEP-E
Table 10. Truth Table
CONDITIONS
MCOUTn
L
H
L
H
L
H
L
H
X
Normal operation
Current limitation
Overtemperature
Undervoltage
Stand-by
CE
H
H
H
H
H
H
H
H
L
I/On
L
H
L
H
L
L (latched)
L
H
X
OUTPUTn
L
H
L
H
L
L
L
L
L
Table 11. Electrical Transient Requirements On VCC Pin
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
I
II
TEST LEVELS
III
IV
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
ISO T/R 7637/1
Test Pulse
CLASS
C
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6/17
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IV
C
C
C
C
C
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CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
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I
C
C
C
C
C
C
1
2
3a
3b
4
5
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
VNQ500PEP-E
Figure 7. Waveforms
1) NORMAL OPERATION
CE
MCOUTn
I/On
VOUTn
2) UNDERVOLTAGE
CE
VUSDhyst
VCC
VUSD
MCOUTn
c
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I/On
VOUTn
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t
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3) SHORTED LOAD OPERATION
CE
TTSD
Tjn
)
s
(
ct
MCOUTn
I/On
)
s
t(
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treset
o
s
b
O
VOL
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IOUTn
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s
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7/17
VNQ500PEP-E
Figure 8. Application Schematic
+5V
VCC
Rprot
CE
Dld
µC
Rprot
I/0n
OUTPUT
Rprot
Diagnostic feedback
GND
RGND
VGND
DGND
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GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
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8/17
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the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
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Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / (IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on many devices are ON in the case of several
high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
)
s
(
ct
)
s
t(
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the VCC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
µC I/Os PROTECTION:
If a ground protection network is used and negative
transient are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
VNQ500PEP-E
Figure 9. Off State Output Current
Figure 10. High Level Input Current
Iih (uA)
IL(off) (uA)
6
0.3
5.5
0.27
Vin=3.25V
Vcc=36V
0.24
5
0.21
4.5
0.18
4
0.15
3.5
0.12
3
0.09
2.5
0.06
2
0.03
1.5
1
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 11. Input Clamp Voltage
Figure 13. Overvoltage Shutdown
Vicl (V)
Vov (V)
10
60
9.5
c
u
d
55
Iin=1mA
9
50
8.5
e
t
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45
8
7.5
40
7
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s
b
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35
6.5
)
s
t(
30
6
5.5
5
-50
-25
0
25
50
75
Tc (°C)
o
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e
100
125
c
u
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(t s)
150
175
Figure 12. Turn-on Voltage Slope
25
20
-50
-25
0
dVout/dt(off) (V/ms)
800
t
e
l
o
100
125
150
175
150
175
750
Vcc=13V
Rl=6.5Ohm
s
b
O
700
75
Figure 14. Turn-off Voltage Slope
dVout/dt(on) (V/ms)
800
50
Tc (°C)
1000
900
25
Vcc=13V
Rl=6.5Ohm
700
650
600
500
600
400
550
300
500
200
450
100
0
400
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
9/17
VNQ500PEP-E
Figure 15. ILIM Vs Tcase
Figure 18. Input Hysteresis Voltage
Ilim (A)
Vhyst (V)
1.4
1
0.9
1.3
Vcc=13V
0.8
1.2
0.7
1.1
0.6
1
0.5
0.9
0.4
0.8
0.3
0.7
0.2
0.6
0.1
0
0.5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
Ron (mOhm)
Ron (mOhm)
900
900
800
700
700
500
500
Tc= -40°C
200
200
100
0
25
Vcc (V)
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Figure 17. Input High Level
30
(t s)
35
c
u
d
3.2
0
-50
-25
0
25
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Figure 20. Input Low Level
Vil (V)
3
2.75
2.5
s
b
O
3
100
40
t
e
l
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3.4
)
s
t(
300
Tc= 25°C
300
3.6
175
o
s
b
O
400
400
Vih (V)
150
o
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e
t
le
600
Tc= 150°C
600
20
125
c
u
d
Iout=0.25A
Vcc=8V, 13V & 36V
Iout=0.25A
800
15
100
Figure 19. On State Resistance Vs Tcase
1000
10
75
Tc (°C)
Figure 16. On State Resistance Vs VCC
5
50
2.25
2.8
2
2.6
1.75
2.4
1.5
2.2
1.25
2
1
1.8
-50
-25
0
25
50
75
Tc (°C)
10/17
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
VNQ500PEP-E
Figure 21. Maximum Turn Off Current Versus Load Inductance
ILM AX (A)
10
1
A
B
C
c
u
d
0.1
10
100
L(mH)
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
)
s
(
ct
Conditions:
VCC=13.5V
t
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1000
o
s
b
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-
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
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VIN, IL
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)
s
t(
Demagnetization
Demagnetization
Demagnetization
s
b
O
t
11/17
VNQ500PEP-E
PowerSSO-12 Thermal Data
Figure 22. PowerSSO-12 PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 78mm x 78mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2).
c
u
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Figure 23. Rthj-amb Vs PCB copper area in open box free air condition
e
t
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RTHj_amb(°C/W)
70
)
s
(
ct
65
o
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P
o
s
b
O
-
u
d
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60
r
P
e
55
t
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l
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50
s
b
O
45
0
2
4
6
PCB Cu heatsink area (cm^2)
12/17
8
10
)
s
t(
VNQ500PEP-E
Figure 24. Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
100
Footprint
8 cm2
10
c
u
d
1
e
t
le
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
Figure 25. Thermal Fitting Model of a Quad
Channel HSD in PowerSSO-12
uc
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t
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(t s)
o
s
b
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-
10
)
s
t(
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100
1000
Pulse Calculation Formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
δ = tp ⁄ T
Table 12. Thermal Parameter
Area/island (cm2)
R1=R7=R9=R11 (°C/W)
R2=R8=R10=R12 (°C/W)
R3 ( °C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1=C7=C9=C11 (W.s/°C)
C2=C8=C10=C12 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
0.8
2.6
1.5
8
28
30
0.00006
0.0005
0.015
0.1
0.15
3
8
18
22
0.17
5
13/17
VNQ500PEP-E
PACKAGE MECHANICAL
Table 13. PowerSSO-12™ Mechanical Data
millimeters
Symbol
Min
Typ
DIM.
MIN.
TYP
1.250
1.620
A1
0.000
0.100
A2
1.100
1.650
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
0.800
)
s
t(
H
5.800
6.200
h
0.250
0.500
L
0.400
k
0º
X
1.900
Y
3.600
c
u
d
1.270
e
t
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ddd
o
s
b
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-
Figure 26. PowerSSO-12™ Package Dimensions
)
s
(
ct
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14/17
MAX.
A
e
s
b
O
Max
mm.
o
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P
8º
2.500
4.200
0.100
VNQ500PEP-E
Figure 27. PowerSSO-12 Tube Shipment (No Suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 28. Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
ro
c
u
d
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
P
e
let
)
s
(
ct
TAPE DIMENSIONS
u
d
o
o
s
b
O
-
)
s
t(
2500
2500
330
1.5
13
20.2
12.4
60
18.4
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
r
P
e
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
t
e
l
o
s
b
O
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
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VNQ500PEP-E
REVISION HISTORY
Table 14. Revision History
Date
Revision
Description of Changes
Dec. 2004
1
- First Issue.
Jun. 2005
2
- Electrical characterization insertion;
- Configuration diagram drawing change;
- Thermal data insertion;
- Shipment data insertion;
- Minor changes.
Jun. 2005
3
- Maximum Turn Off Current Versus Load Inductance curve insertion;
- Thermal Impedance Junction Ambient Single Pulse curve insertion.
Jun. 2005
4
- Maximum Turn Off Current Versus Load Inductance curve review.
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d
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16/17
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b
O
-
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r
P
)
s
t(
VNQ500PEP-E
c
u
d
e
t
le
)
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P
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
s
b
O
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