TI SN74LVC1G66YEAR

SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
1.65-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 0.8 ns at 3.3 V
High On-Off Output Voltage Ratio
High Degree of Linearity
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
Low On-State Resistance, Typically ≈5.5 Ω
(VCC = 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
A
B
GND
1
5
VCC
4
C
2
3
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
GND
B
A
3 4
C
2
1 5
VCC
description/ordering information
This single analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G66 can handle both analog and digital signals. The device permits signals with amplitudes of
up to 5.5 V (peak) to be transmitted in either direction.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC1G66YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
−40°C to 85°C
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC1G66YZAR
Reel of 3000
−40°C to 85°C
SOT (SC-70) − DCK
_ _ _C6_
SN74LVC1G66YEPR
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SOT (SOT-23) − DBV
TOP-SIDE
MARKING‡
SN74LVC1G66YZPR
Reel of 3000
SN74LVC1G66DBVR
Reel of 250
SN74LVC1G66DBVT
Reel of 3000
SN74LVC1G66DCKR
Reel of 250
SN74LVC1G66DCKT
C66_
C6_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
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1
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
FUNCTION TABLE
CONTROL
INPUT
(C)
SWITCH
L
OFF
H
ON
logic diagram (positive logic)
1
2
A
B
4
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Control input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
On-state switch current, IT (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 4): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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recommended operating conditions (see Note 5)
MIN
VCC
VI/O
VIH
UNIT
Supply voltage
1.65
5.5
V
I/O port voltage
0
VCC
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage, control input
VIL
Low-level input voltage, control input
VI
Control input voltage
∆t/∆v
MAX
VCC × 0.65
VCC × 0.7
V
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC × 0.35
VCC × 0.3
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC × 0.3
V
5.5
V
0
Input transition rise/fall time
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
10
20
ns/V
10
TA
Operating free-air temperature
−40
85
°C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
ron
ron(p)
On-state switch resistance
Peak on resistance
TEST CONDITIONS
VI = VCC or GND,
VC = VIH
(see Figures 1 and 2)
VI = VCC to GND,
VC = VIH
(see Figures 1 and 2)
VCC
MIN
TYP†
MAX
IS = 4 mA
IS = 8 mA
1.65 V
12
30
2.3 V
9
20
IS = 24 mA
IS = 32 mA
3V
7.5
15
4.5 V
5.5
10
IS = 4 mA
IS = 8 mA
1.65 V
74.5
100
20
30
IS = 24 mA
IS = 32 mA
3V
11.5
20
4.5 V
7.5
15
2.3 V
±1
UNIT
Ω
Ω
IS(off)
Off-state switch leakage current
VI = VCC and VO = GND or
VI = GND and VO = VCC,
VC = VIL (see Figure 3)
5.5 V
IS(on)
On-state switch leakage current
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 4)
5.5 V
±1
±0.1†
µA
A
II
Control input current
VC = VCC or GND
5.5 V
±1
±0.1†
A
µA
ICC
Supply current
VC = VCC or GND
5.5 V
10
1†
µA
A
∆ICC
Cic
Supply current change
VC = VCC − 0.6 V
5.5 V
500
µA
Control input capacitance
5V
2
pF
Cio(off)
Switch input/output capacitance
5V
6
pF
Cio(on)
Switch input/output capacitance
† TA = 25°C
5V
13
pF
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±0.1†
µA
A
3
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 5)
PARAMETER
tpd†
ten‡
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
C
A or B
VCC = 1.8 V
± 0.15 V
MIN
MAX
2.5
12
VCC = 2.5 V
± 0.2 V
MIN
2
MAX
VCC = 3.3 V
± 0.3 V
MIN
MAX
1.2
1.9
6.5
VCC = 5 V
± 0.5 V
MIN
0.8
1.8
5
1.5
UNIT
MAX
0.6
ns
4.2
ns
tdis§
C
A or B
2.2
10
1.4
6.9
2
6.5
1.4
5
ns
† tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and
the specified load capacitance when driven by an ideal voltage source (zero output impedance).
‡ tPZL and tPZH are the same as ten.
§ tPLZ and tPHZ are the same as tdis.
analog switch characteristics, TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response¶
(switch ON)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
Crosstalk
(control input to signal output)
C
A or B
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 7)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
Feed-through attenuation#
(switch OFF)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
CL = 50 pF, RL = 10 kΩ,
k ,
fin = 1 kHz (sine wave)
(see Figure 9)
Sine-wave distortion
A or B
B or A
k ,
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 9)
¶ Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads −3 dB.
# Adjust fin voltage to obtain 0 dBm at input.
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VCC
TYP
1.65 V
35
2.3 V
120
3V
175
4.5 V
195
1.65 V
>300
2.3 V
>300
3V
>300
4.5 V
>300
1.65 V
35
2.3 V
50
3V
70
4.5 V
100
1.65 V
−58
2.3 V
−58
3V
−58
4.5 V
−58
1.65 V
−42
2.3 V
−42
3V
−42
4.5 V
−42
1.65 V
0.1
2.3 V
0.025
3V
0.015
4.5 V
0.01
1.65 V
0.15
2.3 V
0.025
3V
0.015
4.5 V
0.01
UNIT
MHz
mV
dB
%
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
8
• DALLAS, TEXAS 75265
9
VCC = 3.3 V
TYP
9
VCC = 5 V
TYP
11
UNIT
pF
5
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
B or A
A or B
VI = VCC or GND
VIH
VO
C
VC
(ON)
GND
IS
r on +
V
VI − VO
Figure 1. On-State Resistance Test Circuit
100
VCC = 1.65 V
r on − Ω
VCC = 2.3 V
VCC = 3.0 V
10
1
0.0
VCC = 4.5 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − V
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
6
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VI * VO
W
IS
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
VI
A
VIL
B or A
A or B
VO
C
VC
(OFF)
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
VCC
VI = VCC or GND
A
VIH
B or A
A or B
VO
VO = Open
C
VC
(ON)
GND
Figure 4. On-State Leakage-Current Test Circuit
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7
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
0.1 µF
50 Ω
fin
VIH
B or A
A or B
VO
C
VC
RL
(ON)
GND
CL
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 6. Frequency Response (Switch ON)
VCC
VCC
Rin
600 Ω
VCC/2
A or B
B or A
VO
RL
600 Ω
C
VC
GND
50 Ω
CL
50 pF
VCC/2
Figure 7. Crosstalk (Control Input − Switch Output)
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9
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
0.1 µF
RL
50 Ω
fin
B or A
A or B
VO
C
VC
VIL
CL
RL
(OFF)
GND
VCC/2
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 8. Feed-Through (Switch OFF)
VCC
VCC
10 µF
fin
600 Ω
VIH
VO
RL
10 kΩ
C
VC
(ON)
GND
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
VCC = 3 V, VI = 2.5 VP-P
VCC = 4.5 V, VI = 4 VP-P
Figure 9. Sine-Wave Distortion
10
10 µF
B or A
A or B
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VCC/2
CL
50 pF
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
5
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-2/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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