TI SN74LV4051ATPWRQ1

SCLS520B − AUGUST 2003 − REVISED MAY 2004
D Qualification in Accordance With
D, DW, OR PW PACKAGE
(TOP VIEW)
AEC-Q100†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
D
D
D
D
D
D
D
Y4
Y6
COM
Y7
Y5
INH
GND
GND
Can Be Supported Along With
Major-Change Approval
2-V to 5.5-V VCC Operation
Supports Mixed-Mode Voltage Operation on
All Ports
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
Y2
Y1
Y0
Y3
A
B
C
† Contact factory for details. Q100 qualification data available on
request.
description/ordering information
This 8-channel CMOS analog multiplexer/demultiplexer is designed for 2-V to 5.5-V VCC operation.
The SN74LV4051A handles both analog and digital signals. Each channel permits signals with amplitudes up
to 5.5 V (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
−40°C
−40
C to 105
105°C
C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − D
Tape and reel
SN74LV4051ATDRQ1
L4051AQ
SOIC − DW
Tape and reel
SN74LV4051ATDWRQ1
L4051AQ
TSSOP − PW
Tape and reel
SN74LV4051ATPWRQ1
L4051AQ
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
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1
SCLS520B − AUGUST 2003 − REVISED MAY 2004
FUNCTION TABLE
INPUTS
A
ON
CHANNEL
L
L
Y0
L
H
Y1
H
L
Y2
L
H
H
Y3
H
L
L
Y4
H
L
H
Y5
H
H
L
Y6
L
H
H
H
Y7
H
X
X
X
None
INH
C
L
L
L
L
L
L
L
L
L
L
B
logic diagram (positive logic)
3
13
A
14
11
15
B
12
10
1
C
5
9
2
INH
2
4
6
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COM
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SCLS520B − AUGUST 2003 − REVISED MAY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage,
control inputs
VIL
VI
VIO
∆t/∆v
MIN
2‡
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V
V
0.5
VCC × 0.3
VCC × 0.3
0
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
V
VCC × 0.7
0
Input/output voltage
UNIT
1.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Control input voltage
5.5
VCC × 0.7
VCC × 0.7
VCC = 2 V
VCC = 2.3 V to 2.7 V
Low-level input voltage,
control inputs
MAX
VCC × 0.3
5.5
V
V
VCC
200
V
100
ns/V
20
TA
Operating free-air temperature
−40
105
°C
‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCLS520B − AUGUST 2003 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VCC
MIN
TA = 25°C
TYP
MAX
MIN
MAX
UNIT
IT = 2 mA,
VI = VCC or GND,
VINH = VIL
(see Figure 1)
2.3 V
38
180
225
3V
30
150
190
4.5 V
22
75
100
IT = 2 mA,
VI = VCC to GND,
VINH = VIL
2.3 V
113
500
600
3V
54
180
225
4.5 V
31
100
125
Difference in
on-state resistance
between switches
IT = 2 mA,
VI = VCC to GND,
VINH = VIL
2.3 V
2.1
30
40
3V
1.4
20
30
4.5 V
1.3
15
20
Control input current
VI = 5.5 V or GND
0 to
5.5 V
±0.1
±1
µA
IS(off)
Off-state switch
leakage current
VI = VCC and
VO = GND, or
VI = GND and
VO = VCC,
VINH = VIH
(see Figure 2)
5.5 V
±0.1
±1
µA
IS(on)
On-state switch
leakage current
VI = VCC or GND,
VINH = VIL
(see Figure 3)
5.5 V
±0.1
±1
µA
20
µA
ron
ron(p)
∆ron
II
ICC
CIC
4
TEST CONDITIONS
On-state
switch resistance
Peak on-state resistance
Supply current
Control input capacitance
VI = VCC or GND
f = 10 MHz
5.5 V
Ω
Ω
Ω
3.3 V
2
pF
CIS
Common
terminal capacitance
3.3 V
23.4
pF
COS
Switch terminal capacitance
3.3 V
5.7
pF
CF
Feedthrough capacitance
3.3 V
0.5
pF
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SCLS520B − AUGUST 2003 − REVISED MAY 2004
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
TA = 25°C
TYP
MAX
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 4)
2.5
9
12
ns
MIN
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
5.5
20
25
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
8.8
20
25
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
TA = 25°C
TYP
MAX
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 4)
1.5
6
8
ns
MIN
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
4
14
18
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
6.2
14
18
ns
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5
SCLS520B − AUGUST 2003 − REVISED MAY 2004
analog switch characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
Frequency response
(switch on)
Crosstalk
(control input to signal output)
Feedthrough attenuation
(switch off)
Sine-wave distortion
TA = 25°C
TYP
MAX
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC
20
Yn or COM
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz (sine wave)
(see Note 5 and Figure 6)
2.3 V
COM or Yn
3V
25
4.5 V
35
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz (square wave)
(see Figure 7)
2.3 V
20
3V
35
4.5 V
60
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz
(see Note 6 and Figure 8)
2.3 V
−45
3V
−45
4.5 V
−45
CL = 50 pF,
RL = 10 kΩ,
fin = 1 kHz
(sine wave)
(see Figure 9)
2.3 V
0.1
3V
0.1
4.5 V
0.1
INH
COM or Yn
COM or Yn
Yn or COM
COM or Yn
Yn or COM
VI = 2 Vp-p
VI = 2.5 Vp-p
VI = 4 Vp-p
MIN
UNIT
MHz
mV
dB
%
NOTES: 5. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB.
6. Adjust fin voltage to obtain 0-dBm input.
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIL
VCC
VI = VCC or GND
VO
(ON)
GND
r on +
2 mA
V
VI − VO
Figure 1. On-State Resistance Test Circuit
6
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VI – VO
2
10 –3
W
TYP
UNIT
5.9
pF
SCLS520B − AUGUST 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIH
VCC
A
VI
(OFF)
VO
GND
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
Figure 2. Off-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VCC
VI
A
(ON)
Open
GND
VI = VCC or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VCC
Input
Output
(ON)
50 Ω
CL
GND
Figure 4. Propagation Delay Time, Signal Input to Signal Output
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SCLS520B − AUGUST 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
50 Ω
VINH
VCC
VI
S1
VO
TEST
S1
S2
tPLZ/tPZL
tPHZ/tPZH
GND
VCC
VCC
GND
1 kΩ
S2
CL
GND
TEST CIRCUIT
VCC
VCC
VINH
50%
50%
0V
0V
tPZH
tPZL
≈VCC
VOH
VO
50%
50%
VOL
≈0 V
(tPZL, tPZH)
VCC
VCC
VINH
50%
50%
0V
0V
tPHZ
tPLZ
≈VCC
VOH
VO
VOL + 0.3 V
VOL
VOH − 0.3 V
≈0 V
(tPLZ, tPHZ)
VOLTAGE WAVEFORMS
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
VCC
VINH = GND
0.1 µF
fin
VI
VCC
(ON)
GND
50 Ω
VO
RL
CL
VCC/2
NOTE A: fin is a sine wave.
Figure 6. Frequency Response (Switch On)
8
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SCLS520B − AUGUST 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
50 Ω
VINH
VCC
VO
GND
600 Ω
RL
VCC/2
CL
VCC/2
Figure 7. Crosstalk (Control Input, Switch Output)
VCC
VINH = VCC
0.1 µF
VI
fin
50 Ω
VCC
(OFF)
VO
GND
600 Ω
RL
CL
VCC/2
VCC/2
Figure 8. Feedthrough Attenuation (Switch Off)
VCC
VINH = GND
10 µF
fin
600 Ω
10 µF
VCC
(ON)
GND
VO
RL
CL
VCC/2
Figure 9. Sine-Wave Distortion
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9
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74LV4051ATDRQ1
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LV4051ATDWRQ1
ACTIVE
SOIC
DW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LV4051ATPWRQ1
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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