TEMIC TSC251G1DXXX

TSC87251G1A
Extended 8–bit Microcontroller with Serial Communication
Interfaces
1. Description
The TSC87251G1A products are derivatives of the
TEMIC Microcontroller family based on the extended
8–bit C251 Architecture. This family of products is
tailored to 8–bit microcontroller applications requiring
an increased instruction throughput, a reduced operating
frequency or a larger addressable memory space. The
architecture can provide a significant code size
reduction when compiling C programs while fully
preserving the legacy of C51 assembly routines.
The TSC87251G1A derivatives are pin–out and
software compatible with standard 80C51/Fx/Rx with
extended on–chip data memory (1 Kbyte RAM),
on–chip memory (16 Kbytes EPROM/OTPROM) and
up to 256 Kbytes of external code and data.
They provide transparent enhancements to Intel’s
87C251Sx family with an additional Synchronous Serial
Link Controller (SSLC supporting I2C, µWire and SPI
protocols), a Keyboard interrupt interface and Power
Monitoring and Management features.
Notes:
This Datasheet provides the technical description of the TSC87251G1A derivatives. For further information on the device usage, please request
the TSC80251 Programmers’ Guide and the TSC80251G1 Design Guide.
For information on the Mask ROM and ROMless devices, please refer to the TSC87251G1D Datasheet.
2. Typical Applications
ISDN terminals
Plotters
High–Speed modems
Scanners
PABX (SOHO)
Banking machines
Networking
Barcode readers
Line cards
Smart cards readers
Computer peripherals
High–end digital monitors
Printers
High–end joysticks
Purchase of TEMIC I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev. A
– September 21, 1998
1
TSC87251G1A
3. Features
D Pin–Out and software compatibility with standard
80C51 products and 80C51FA/FB/RA/RB
D Plug–in replacement of Intel’s 80C251Sx
D C251 core: Intel’s MCSR251 step A compliance
G
G
G
G
G
125 ns Instruction cycle time at 16 MHz
40–byte Register File
Registers Accessible as Bytes, Words or Dwords
Six–stage instruction Pipeline
16–bit Internal Code Fetch
D Enriched C51 Instruction Set
G 16–bit and 32–bit ALU
G Compare and Conditional Jump Instructions
G Expanded Set of Move Instructions
D Linear Addressing
D 1 Kbyte of on–chip RAM
D External memory space (Code/Data) programmable
from 64 Kbytes to 256 Kbytes
D TSC87251G1A: 16 Kbytes of on–chip EPROM/
OTPROM (production with TSC83251G1D:
on–chip masked ROM version)
D Secured 14–bit Hardware Watchdog Timer
D Power Monitoring and Management
G Power–Fail reset
G Power–On reset (integrated on the chip)
G Power–Off flag (cold and warm resets)
G Software programmable system clock
G Idle and Power–Down modes
D Keyboard interrupt interface on Port 1
D ONCE mode and full speed Real–Time In–Circuit
Emulation support (Third Party Vendors)
D Speed ranges:
G 0 to 16 MHz
D Supply ranges:
G 5 V ±10 %
D Temperature ranges:
G Commercial (0°C to +70°C)
G Industrial (–40°C to +85°C)
G Option: extended range (–55°C to +125°C)
D Packages:
D SINGLE–PULSE Programming Algorithm
G PDIL 40, PLCC 44
D Four 8–bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the
standard 80C51)
G UV–Window CQPJ 44
D Serial I/O Port: full duplex UART (80C51
compatible) with independent Baud Rate Generator
G Options: known good dice and ceramic packages
D SSLC: Synchronous Serial Link Controller
G I2C master only protocol
G µWire and SPI master only protocol
D Three 16–bit Timers/Counters (Timers 0, 1 and 2 of
the standard 80C51)
D EWC: Event and Waveform Controller
G Compatible with Intel’s Programmable Counter
Array (PCA)
G Common 16–bit Timer/Counter reference with
four possible clock sources (Fosc/4, Fosc/12,
Timer 1 and external input)
G Five modules with four programmable modes:
– 16–bit software Timer/Counter
– 16–bit Timer/Counter Capture Input and
software pulse measurement
– High–speed output and 16–bit software Pulse
Width Modulation (PWM)
– 8–bit hardware PWM without overhead
G 16–bit Watchdog Timer/Counter capability
2
Rev. A
– September 21, 1998
TSC87251G1A
4. Block Diagram
P3(A16) P2(A15–8) P1(A17)
P0(AD7–0)
PSEN#
PORTS 0–3
EPROM
OTPROM
16 Kbytes
Timers 0, 1 and 2
RAM
1 Kbyte
ALE/PROG#
UART
16–bit Memory Code
16–bit Memory Address
Event and Waveform
Controller
I2C/SPI/Wire
Controller
Watchdog Timer
RST
8-bit Internal Bus
24-bit Data Address Bus
8-bit Data Bus
16-bit Inst. Bus
24-bit Prog. Counter Bus
Bus Interface Unit
Peripheral Interface Unit
EA#/VPP
Power Monitoring
XTAL2
Clock Unit
Clock System Prescaler
XTAL1
Keyboard Interface
CPU
Interrupt Handler
Unit
VDD
VSS
VSS1
VSS2
Figure 1. TSC87251G1A Block Diagram
Rev. A
– September 21, 1998
3
TSC87251G1A
5. Pin Description
5.1. Pinout
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK
P1.7/A17/CEX4/SDA/MOSI
RST
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSC87251G1A
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
6
5
4
3
2
1
44
43
42
41
40
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
Figure 2. TSC87251G1A 40–pin DIP package
7
8
9
10
11
12
13
14
15
16
17
TSC87251G1A
39
38
37
36
35
34
33
32
31
30
29
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NC
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
18
19
20
21
22
23
24
25
26
27
28
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK
P1.7/A17/CEX4/SDA/MOSI
RST
P3.0/RXD
NC
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
Figure 3. TSC87251G1A 44–pin PLCC/CQPJ Package
4
Rev. A
– September 21, 1998
TSC87251G1A
Table 1. TSC87251G1A Pin Assignment
DIP
PLCC
Name
1
VSS1
1
2
P1.0/T2
2
3
P1.1/T2EX
3
4
4
DIP
PLCC
Name
23
VSS2
21
24
P2.0/A8
22
25
P2.1/A9
P1.2/ECI
23
26
P2.2/A10
5
P1.3/CEX0
24
27
P2.3/A11
5
6
P1.4/CEX1
25
28
P2.4/A12
6
7
P1.5/CEX2/MISO
26
29
P2.5/A13
7
8
P1.6/CEX3/SCL/SCK
27
30
P2.6/A14
8
9
P1.7/A17/CEX4/SDA/MOSI
28
31
P2.7/A15
9
10
RST
29
32
PSEN#
10
11
P3.0/RXD
30
33
ALE/PROG#
12
NC
34
NC
11
13
P3.1/TXD
31
35
EA#/VPP
12
14
P3.2/INT0#
32
36
P0.7/AD7
13
15
P3.3/INT1#
33
37
P0.6/AD6
14
16
P3.4/T0
34
38
P0.5/AD5
15
17
P3.5/T1
35
39
P0.4/AD4
16
18
P3.6/WR#
36
40
P0.3/AD3
17
19
P3.7/A16/RD#
37
41
P0.2/AD2
18
20
XTAL2
38
42
P0.1/AD1
19
21
XTAL1
39
43
P0.0/AD0
20
22
VSS
40
44
VDD
5.2. Signals
Table 2. TSC87251G1A Signal Descriptions
Signal
Name
Type
A17
O
Description
18th Address Bit
Alternate
Function
P1.7
Output to memory as 18th external address bit (A17) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
A16
O
17th Address Bit
P3.7
Output to memory as 17th external address bit (A16) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
A15:8(1)
O
Address Lines
P2.7:0
Upper address lines for the external bus.
AD7:0(1)
I/O
Address/Data Lines
P0.7:0
Multiplexed lower address lines and data for the external memory.
ALE
O
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid address information are
available onlines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address
from address/databus.
CEX4:0
O
PCA Input/Output pins
P1.7:3
CEXx are input signals for the PCA capture mode and output signals for the PCA compare and
PWM modes.
EA#
I
External Access Enable
EA# directs program memory accesses to on–chip or off–chip code memory.
For EA#= 0, all program memory accesses are off-chip.
For EA#= 1, an access is on-chip EPROM/OTPROM if the address is within the range of the on–
chip EPROM/OTPROM; otherwise the access is off-chip. The value of EA# is latched at reset.
Rev. A
– September 21, 1998
5
TSC87251G1A
Signal
Name
Type
ECI
O
Alternate
Function
Description
PCA External Clock input
P1.2
ECI is the external clock input to the 16–bit PCA timer.
MISO
I/O
SPI Master Input Slave Output line
P1.5
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave
mode, MISO outputs data to the master controller.
MOSI
I/O
SPI Master Output Slave Input line
P1.7
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave
mode, MOSI receives data from the master controller.
INT1:0#
I
External Interrupts 0 and 1.
P3.3:2
INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set,
bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set
by a low level on INT1#/INT0#
P0.0:7
I/O
Port 0
P1.0:7
I/O
Port 1
AD7:0
P0 is an 8–bit open–drain bidirectional I/O port.
P1 is an 8–bit bidirectional I/O port with internal pull–ups. P1 provides interrupt capability for
a keyboard interface.
P2.0:7
I/O
Port 2
A15:8
P2 is an 8–bit bidirectional I/O port with internal pull–ups.
P3.0:7
I/O
Port 3
P3 is an 8–bit bidirectional I/O port with internal pull–ups.
PROG#
O
Programming Pulse input
The programming pulse is applied to this input for programming the on–chip EPROM/
OTPROM.
PSEN#
O
Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
RD#
O
Read or 17th Address Bit (A16)
P3.7
Read signal output to external data memory depending on the values of bits RD0 and RD1 in
UCONFIG0 byte (see Table 13).
RST
I
Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running resets the device.
The Port pins are driven to their reset conditions when a voltage greater than VIH1 is applied,
whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset by connecting a
capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power–Down mode returns the chip to normal
operation.
RXD
I/O
Receive Serial Data
P3.0
RXD sends and receives data in serial I/O mode 0 and receives data in serial modes I/O 1, 2 and 3.
SCL
I/O
I2C Serial Clock
P1.6
SCL outputs the serial clock to slave peripherals.
SCK
I/O
SPI Serial Clock
P1.6
SCK outputs clock to the slave peripheral.
SDA
I/O
I2C Serial Data
P1.7
SDA is the bidirectional I2C data line.
T1:0
I/O
Timer 1:0 External Clock Inputs
When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.
6
Rev. A
– September 21, 1998
TSC87251G1A
Signal
Name
Type
T2
I/O
Description
Timer 2 Clock Input/Output
Alternate
Function
P1.0
For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock–out mode,
T2 is the clock output.
T2EX
I
Timer 2 External Input
P1.1
In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto–reload
mode, a falling edge causes the timer 2 register to be reloaded. In the up–down counter mode,
this signal determines the count direction: 1= up, 0= down.
TXD
I/O
Transmit Serial Data
P3.1
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3.
VDD
PWR
Digital Supply Voltage
VSS
GND
Circuit Ground
Connect this pin to +5V or +3V supply voltage.
Connect this pin to ground.
VSS1
GND
Secondary Ground 1
This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC87251G1A as a
pin–for–pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of compatibility.
Not available on DIP package.
VSS2
GND
Secondary Ground 2
This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC87251G1A as a
pin–for–pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of compatibility.
Not available on DIP package.
VPP
I
Programming Supply Voltage
The programming supply voltage is applied to this input for programming the on–chip EPROM/
OTPROM
WR#
O
Write
P3.6
Write signal output to external memory.
XTAL1
I
Input to the on–chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing.
XTAL2
O
Output of the on–chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, leave XTAL2 unconnected.
Note:
1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the non–page mode chip configuration. If the chip is configured in page mode
operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0).
Rev. A
– September 21, 1998
7
TSC87251G1A
6. Address Spaces
The TSC87251G1A implements four different address spaces:
On–chip EPROM/OTPROM program/code memory
On–chip RAM data memory
Special Function Registers (SFRs)
Configuration array
6.1. Program/Code Memory
The TSC87251G1A implements 16 Kbytes of on–chip EPROM/OTPROM for program/code memory. Figure 4 shows
the split of the internal and external program/code memory spaces. If EA# is tied to a high level, the 16–Kbyte on–chip
program/code memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The rest of
the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the internal
program/code memory is not used and all the accesses are directed to the external memory.
Program/code
External Memory Space
Program/code
Segments
On–chip Memory
EPROM/OTPROM Code
FF:FFFFh
48 Kbytes
16 Kbytes
64 Kbytes
FF:4000h
FF:3FFFh
EA#= 0
EA#= 1
FF:0000h
FE:FFFFh
16 Kbytes
ÈÈÈÈÈ
ÈÈÈÈÈ
ÈÈÈÈÈ
ÈÈÈÈÈ
FE:0000h
FD:FFFFh
Reserved
02:0000h
01:FFFFh
128 Kbytes
01:0000h
00:FFFFh
00:0000h
Figure 4. Program/Code Memory Mapping
Notes:
Special care should be taken when the Program Counter (PC) increments:
– If the program executes exclusively from on–chip code memory (not from external memory), beware of executing code from the upper eight bytes of
the on–chip EPROM (FF:3FF8h–FF:3FFFFh). Because of its pipeline capability, the TSC87251G1A may attempt to prefetch code from external
memory (at an address above FF:3FFFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does not affect Ports 0
and 2.
– When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC increments
beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of segment 01:, it loops to
the beginning of segment 00: (this prevents from its going into the reserved area).
8
Rev. A
– September 21, 1998
TSC87251G1A
6.2. Data Memory
The TSC87251G1A implements 1 Kbyte of on–chip data RAM. Figure 5 shows the split of the internal and external
data memory spaces. This memory is mapped in the data space just over the 32 bytes of registers area (see TSC80251
Programmers’ Guide). Hence, the part of the on–chip RAM located from 20h to FFh is bit addressable. This on–chip
RAM is not accessible through the program/code memory space.
For faster computation with the on–chip EPROM code of the TSC87251G1A, its upper 8 Kbytes are also mapped in
the upper part of the region 00: if the On–Chip Code Memory Map configuration bit is cleared (EMAP# bit in
UCONFIG1 byte, see Figure 7). However, if EA# is tied to a low level, the TSC87251G1A derivative is running as
a ROMless product and the code is actually fetched in the corresponding external memory (i.e. the upper 8 Kbytes of
the lower 16 Kbytes of the segment FF:). If EMAP# bit is set, the on–chip EPROM is not accessible through the region
00:.
All the accesses to the portion of the data space with no on–chip memory mapped onto are redirected to the external
memory.
Data External
Memory Space
On–chip Memory
EPROM/OTPROM Code
Data Segments
FF:FFFFh
48 Kbytes
16 Kbytes
FF:4000h
FF:3FFFh
FF:0000h
FE:FFFFh
EA#= 0
EA#= 1
8 Kbytes
64 Kbytes
ÈÈÈÈÈ
ÈÈÈÈÈ
ÈÈÈÈÈ
FE:0000h
FD:FFFFh
Reserved
02:0000h
01:FFFFh
8 Kbytes
64 Kbytes
01:0000h
8 Kbytes
EMAP#= 1
00:FFFFh
00:E000h
00:DFFFh
EMAP#= 0
RAM Data
1 Kbyte
56 Kbytes
00:0420h
32 bytes reg.
Figure 5. Data Memory Mapping
6.3. Special Function Registers
The Special Function Registers (SFRs) of the TSC87251G1A derivatives fall into the categories detailed in Table 3
to Table 11.
SFRs are placed in a reserved on–chip memory region S: which is not represented in the data memory mapping
(Figure 5). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12.
They are upward compatible with the SFRs of the standard 80C51 and the Intel’s 80C251Sx family. In this table, the
C251 core registers are in italics and are described in the TSC80251 Programmer’s Guide. The other SFRs are described
in the TSC80251G1 Design Guide. All the SFRs are bit–addressable using the C251 instruction set.
Rev. A
– September 21, 1998
9
TSC87251G1A
Table 3. C251 Core SFRs
Mnemonic
Name
Mnemonic
Name
Accumulator
SPH(1)
Stack Pointer High – MSB of SPX
B Register
DPL(1)
Data Pointer Low byte – LSB of DPTR
Program Status Word
DPH(1)
Data Pointer High byte – MSB of DPTR
PSW1
Program Status Word 1
DPXL(1)
Data Pointer Extended Low byte of DPX – Region number
SP(1)
Stack Pointer – LSB of SPX
ACC(1)
B(1)
PSW
Note:
1. These SFRs can also be accessed by their corresponding registers in the register file.
Table 4. I/O Port SFRs
Mnemonic
Name
Mnemonic
Name
P0
Port 0
P2
Port 2
P1
Port 1
P3
Port 3
Table 5. Timers SFRs
Mnemonic
Name
Mnemonic
Name
TL0
Timer/Counter 0 Low Byte
TMOD
Timer/Counter 0 and 1 Modes
TH0
Timer/Counter 0 High Byte
T2CON
Timer/Counter 2 Control
TL1
Timer/Counter 1 Low Byte
T2MOD
Timer/Counter 2 Mode
TH1
Timer/Counter 1 High Byte
RCAP2L
Timer/Counter 2 Reload/Capture Low Byte
TL2
Timer/Counter 2 Low Byte
RCAP2H
Timer/Counter 2 Reload/Capture High Byte
TH2
Timer/Counter 2 High Byte
WDTRST
WatchDog Timer Reset
TCON
Timer/Counter 0 and 1 Control
Table 6. Serial I/O Port SFRs
Mnemonic
Name
Mnemonic
Name
SCON
Serial Control
SADDR
Slave Address
SBUF
Serial Data Buffer
BRL
Baud Rate Reload
SADEN
Slave Address Mask
BDRCON
Baud Rate Control
Table 7. SSLC SFRs
Mnemonic
Name
Mnemonic
Name
SSCON
Synchronous Serial control
SSCS
Synchronous Serial Control and Status
SSDAT
Synchronous Serial Data
SSBR
Synchronous Serial Bit Rate
10
Rev. A
– September 21, 1998
TSC87251G1A
Table 8. Event Waveform Control SFRs
Mnemonic
Name
Mnemonic
Name
CCON
EWC–PCA Timer/Counter Control
CCAP1L
EWC–PCA Compare Capture Module 1 Low Register
CMOD
EWC–PCA Timer/Counter Mode
CCAP2L
EWC–PCA Compare Capture Module 2 Low Register
CL
EWC–PCA Timer/Counter Low Register
CCAP3L
EWC–PCA Compare Capture Module 3 Low Register
CH
EWC–PCA Timer/Counter High Register
CCAP4L
EWC–PCA Compare Capture Module 4 Low Register
CCAPM0
EWC–PCA Timer/Counter Mode 0
CCAP0H
EWC–PCA Compare Capture Module 0 High Register
CCAPM1
EWC–PCA Timer/Counter Mode 1
CCAP1H
EWC–PCA Compare Capture Module 1 High Register
CCAPM2
EWC–PCA Timer/Counter Mode 2
CCAP2H
EWC–PCA Compare Capture Module 2 High Register
CCAPM3
EWC–PCA Timer/Counter Mode 3
CCAP3H
EWC–PCA Compare Capture Module 3 High Register
CCAPM4
EWC–PCA Timer/Counter Mode 4
CCAP4H
EWC–PCA Compare Capture Module 4 High Register
CCAP0L
EWC–PCA Compare Capture Module 0 Low
Register
Table 9. System Management SFRs
Mnemonic
Name
Mnemonic
Name
PCON
Power Control
PFILT
Power Filter
POWM
Power Management
CKRL
Clock Reload
Table 10. Interrupt SFRs
Mnemonic
Name
Mnemonic
Name
IE0
Interrupt Enable Control 0
IPL0
Interrupt Priority Control Low 0
IE1
Interrupt Priority Control 1
IPH1
Interrupt Priority Control High 1
IPH0
Interrupt Priority Control High 0
IPL1
Interrupt Priority Control Low 1
Table 11. Keyboard Interface SFRs
Mnemonic
Name
Mnemonic
Name
P1IE
Port 1 Input Interrupt Enable
P1LS
Port 1 Level Selection
P1F
Port 1 Flag
Rev. A
– September 21, 1998
11
TSC87251G1A
Table 12. SFR Addresses and Reset Values
0/8
F8h
F0h
1/9
2/A
3/B
4/C
5/D
6/E
CH
0000 0000
CCAP0H
0000 0000
CCAP1H
0000 0000
CCAP2H
0000 0000
CCAP3H
0000 0000
CCAP4H
0000 0000
7/F
FFh
B(1)
0000 0000
F7h
CL
0000 0000
E8h
E0h
ACC(1)
0000 0000
D8h
CCON
00X0 0000
CMOD
00XX X000
D0h
PSW(1)
0000 0000
PSW1(1)
0000 0000
C8h
T2CON
0000 0000
T2MOD
XXXX XX00
CCAP0L
0000 0000
CCAP1L
0000 0000
CCAP2L
0000 0000
CCAP3L
0000 0000
CCAP4L
0000 0000
EFh
E7h
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
DFh
D7h
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
CFh
C0h
C7h
B8h
IPL0
X000 0000
SADEN
0000 0000
B0h
P3
1111 1111
IE1
XX0X XXX0
A8h
IE0
0000 0000
SADDR
0000 0000
A0h
P2
1111 1111
98h
SCON
0000 0000
90h
P1
1111 1111
88h
TCON
0000 0000
80h
SBUF
SPH(1)
0000 0000
IPL1
XX0X XXX0
IPH1
XX0X XXX0
IPH0
X000 0000
B7h
AFh
BRL
0000 0000
BDRCON
XXX0 0000
P1LS
0000 0000
P1IE
0000 0000
SSBR
0000 0000
SSCON
0000 0000
SSCS
(2)
SSDAT
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
P0
1111 1111
SP
0000 0111
DPL(1)
0000 0000
DPH(1)
0000 0000
DPXL(1)
0000 0001
0/8
1/9
2/A
3/B
4/C
XXXX XXXX
BFh
5/D
WDTRST
1111 1111
A7h
P1F
0000 0000
9Fh
97h
CKRL
0000 1000
POWM
0XXX 0XXX
8Fh
PFILT
XXXX XXXX
PCON
0000 0000
87h
6/E
7/F
reserved
Notes:
1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).
2. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode.
12
Rev. A
– September 21, 1998
TSC87251G1A
6.4. Configuration Bytes
The TSC87251G1A derivatives provide user design flexibility by configuring certain operating features at device reset.
These features fall into the following categories:
external memory interface (page mode, address bits, programmed wait states and the address range for RD#,
WR#, and PSEN#)
source mode/binary mode opcodes
selection of bytes stored on the stack by an interrupt
mapping of the upper portion of on–chip code memory to region 00:
Two user configuration bytes CONFIG0 (see Figure 6) and CONFIG1 (see Figure 7) provide the information.
For TSC87251G1A devices, configuration information is stored in on–chip separate memory (see paragraph 8.
“EPROM Programming”). Whatever the EA# level, the configuration information is retrieved from this on–chip
memory.
CONFIG0
Configuration Byte 0
7
6
5
4
3
2
1
0
–
–
WSA
XALE#
RD1
RD0
PAGE#
SRC
Bit
Number
Bit
Mnemonic
7
–
Reserved
Set this bit when writing to CONFIG0.
6
–
Reserved
Set this bit when writing to CONFIG0.
5
WSA
4
XALE#
3
RD1
2
RD0
1
PAGE#
0
SRC
Description
Wait State A bits
Clear to generate one wait state for all memory region except 01:.
Set for no wait states for all memory region except 01:.
Extend ALE bit
Clear to extend the duration of the ALE pulse from TOSC to 3×TOSC.
Set to minimize the duration of the ALE pulse to 1×TOSC.
Memory Signal Select bits
Specify a 18–bit,
18 bit 17–bit
17 bit or 16–bit
16 bit external address bus and the usage of RD#,
RD# WR# and PSEN# signals
(see Table 13).
Page Mode Select bit
Clear to select the faster page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0.
Set to select the non–page mode(1) with A15:8 on Port 2 and A7:0/D7:0 on Port 0.
Source Mode/Binary Mode Select bit
Clear to select the binary mode.
Set to select the source mode.
Note:
1. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0.
Figure 6. Configuration Byte 0
Rev. A
– September 21, 1998
13
TSC87251G1A
CONFIG1
Configuration Byte 1
7
6
5
4
3
2
1
0
–
–
–
INTR
WSB
–
–
EMAP#
Bit
Number
Bit
Mnemonic
7
–
Reserved
Set this bit when writing to CONFIG1.
6
–
Reserved
Set this bit when writing to CONFIG1.
5
–
Reserved
Set this bit when writing to CONFIG1.
Description
4
INTR
Interrupt Mode bit(1)
Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the PSW1
register).
3
WSB
Wait State B bit
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
2
–
Reserved
Set this bit when writing to CONFIG1.
1
–
Reserved
Set this bit when writing to CONFIG1.
0
EMAP#
On–Chip Code Memory Map bit
Clear to map the upper 8 Kbytes of on–chip code memory (at FF:2000h–FF:3FFFh) to the data space (at
00:E000h–00:FFFFh).
Set not to map the upper 8 Kbytes of on–chip code memory (at FF:2000h–FF:3FFFh) to the data space.
Note:
1. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used with code
executing outside region FF:.
Figure 7. Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
RD1
RD0
P1.7
P3.7/RD#
PSEN#
WR#
External Memory
0
0
A17
A16
Read signal for all external
memory locations
Write signal for all external
memory locations
256 Kbytes
0
1
I/O pin
A16
Read signal for all external
memory locations
Write signal for all external
memory locations
128 Kbytes
1
0
I/O pin
I/O pin
Read signal for all external
memory locations
Write signal for all external
memory locations
64 Kbytes
1
1
I/O pin
Read signal for regions 00:
and 01:
Read signal for regions FE:
and FF:
Write signal for all external
memory locations
2 × 64 Kbytes(1)
Note:
1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.
14
Rev. A
– September 21, 1998
TSC87251G1A
7. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its
length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are two
concurrent processes limiting the effective instruction throughput:
D Instruction Fetch
D Instruction Execution
Table 20 to Table 34 assume code executing from on–chip memory, then the CPU is fetching 16–bit at a time and this
is never limiting the execution speed.
If the code is fetched from external memory, a pre–fetch queue will store instructions ahead of execution to optimize
the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited
depending on the average size of instructions (for the considered section of the program flow). The maximum average
instruction throughput is provided by Table 14 depending on the external memory configuration (from Page Mode to
Non–Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the
maximum effective throughput is found by pondering the number of states for the neighbor integer values.
Table 14. Minimum Number of States per Instruction for given Average Sizes
Non–Page Mode (states)
Average ssize
ze of
Instructions (bytes)
Page Mode
(states)
0 Wait State
1 Wait State
2 Wait States
1
1
2
3
4
2
2
4
6
8
3
3
6
9
12
4
4
8
12
16
5
5
10
15
20
If the average execution time of the considered instructions is larger than the number of states given by Table 14, this
larger value will prevail as the limiting factor. Otherwise, the value from Table 14 must be taken. This is providing
a fair estimation of the execution speed but only the actual code execution can provide the final value.
7.1. Notation for Instruction Operands
Table 15 to Table 19 provide Notation for Instruction Operands.
Table 15. Notation for Direct Addressing
Direct Address
Description
C251
C51
n
dir8
A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address
(80h-FFh). It is a byte (default), word or double word depending on the other operand.
n
dir16
A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing.
n
Table 16. Notation for Immediate Addressing
Immediate
Address
Description
C251
C51
n
#data
An 8-bit constant that is immediately addressed in an instruction
n
#data16
A 16-bit constant that is immediately addressed in an instruction
n
#0data16
#1data16
A 32-bit constant that is immediately addressed in an instruction. The upper word is filled
with zeros (#0data16) or ones (#1data16).
n
#short
A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction.
n
Rev. A
– September 21, 1998
15
TSC87251G1A
Table 17. Notation for Bit Addressing
Direct Address
Description
C251
bit51
A directly addressed bit (bit number= 00h-FFh) in memory or an SFR. Bits 00h-7Fh are the
128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits in the
16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h.
bit
A directly addressed bit in memory locations 00:0020h-00:007Fh or in any defined SFR.
C51
n
n
Table 18. Notation for Destination in Control Instructions
Direct Address
Description
C251
C51
n
n
rel
A signed (two’s complement) 8-bit relative address. The destination is –128 to +127 bytes
relative to the next instruction’s first byte.
addr11
An 11-bit target address. The target is in the same 2-Kbyte block of memory as the next
instruction’s first byte.
n
addr16
A 16-bit target address. The target can be anywhere within the same 64-Kbyte region as the
next instruction’s first byte.
n
addr24
A 24-bit target address. The target can be anywhere within the 16–Mbyte address space.
n
Table 19. Notation for Register Operands
Register
Description
C251
C51
@Ri
A memory location (00h-FFh) addressed indirectly via byte registers R0 or R1
n
Rn
n
Byte register R0-R7 of the currently selected register bank
Byte register index: n= 0-7
n
Rm
Rmd
Rms
m, md, ms
Byte register R0-R15 of the currently selected register file
Destination register
Source register
Byte register index: m, md, ms= 0-15
WRj
WRjd
WRjs
@WRj
Word register WR0, WR2, ..., WR30 of the currently selected register file
Destination register
Source register
A memory location (00:0000h-00:FFFFh) addressed indirectly through word register
WR0-WR30, is the target address for jump instructions.
A memory location (00:0000h-00:FFFFh) addressed indirectly through word register
(WR0-WR30) + 16–bit signed (two’s complement) displacement value
Word register index: j, jd, js= 0-30
n
Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently selected register file
Destination register
Source register
A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register
DR0-DR28, DR56 and DR60, is the target address for jump instruction
A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register
(DR0-DR28, DR56, DR60) + 16–bit (two’s complement) signed displacement value
Dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60
n
@WRj +dis16
j, jd, js
DRk
DRkd
DRks
@DRk
@DRk +dis16
k, kd, ks
16
n
Rev. A
– September 21, 1998
TSC87251G1A
7.2. Size and Execution Time for Instruction Families
Table 20. Summary of Add and Subtract Instructions
Add
Subtract
Add with Carry
Subtract with Borrow
Mnemonic
Binary Mode
<dest> <src>(1)
<dest>,
A, Rn
dest opnd ← dest opnd + src opnd
dest opnd ← dest opnd – src opnd
(A) ← (A) + src opnd + (CY)
(A) ← (A) – src opnd – (CY)
ADD <dest>, <src>
SUB <dest>, <src>
ADDC <dest>, <src>
SUBB <dest>, <src>
Source Mode
Comments
Register to ACC
Bytes
States
Bytes
States
1
1
2
2
2
1(2)
A, dir8
Direct address to ACC
2
1(2)
A, @Ri
Indirect address to ACC
1
2
2
3
A, #data
Immediate data to ACC
2
1
2
1
Rmd, Rms
Byte register to/from byte register
3
2
2
1
WRjd, WRjs
Word register to/from word register
3
3
2
2
DRkd, DRks
Dword register to/from dword register
3
5
2
4
Rm, #data
Immediate 8-bit data to/from byte register
4
3
3
2
WRj, #data16
Immediate 16-bit data to/from word register
5
4
4
3
DRk, #0data16
16-bit unsigned immediate data to/from dword register
5
6
4
5
3
2(2)
ADD
ADD / SUB
Rm, dir8
Direct address (on–chip RAM or SFR) to/from byte
register
4
3(2)
WRj, dir8
Direct address (on–chip RAM or SFR) to/from word
register
4
4
3
3
Rm, dir16
Direct address (64K) to/from byte register
5
3(3)
4
2(3)
WRj, dir16
Direct address (64K) to/from word register
5
4(4)
4
3(4)
Rm, @WRj
Indirect address (64K) to/from byte register
4
3(3)
3
2(3)
Rm, @DRk
Indirect address (16M) to/from byte register
4
4(3)
3
3(3)
A, Rn
Register to/from ACC with carry
1
1
2
2
A, dir8
Direct address (on–chip RAM or SFR) to/from ACC
with carry
2
1(2)
2
1(2)
A, @Ri
Indirect address to/from ACC with carry
1
2
2
3
A, #data
Immediate data to/from ACC with carry
2
1
2
1
ADDC /
SUBB
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Rev. A
– September 21, 1998
17
TSC87251G1A
Table 21. Summary of Increment and Decrement Instructions
Increment
Increment
Decrement
Decrement
Mnemonic
dest opnd ← dest opnd + 1
dest opnd ← dest opnd + src opnd
dest opnd ← dest opnd – 1
dest opnd ← dest opnd – src opnd
INC <dest>
INC <dest>, <src>
DEC <dest>
DEC <dest>, <src>
Binary Mode
<dest> <src>(1)
<dest>,
Source Mode
Comments
Bytes
States
Bytes
States
A
ACC by 1
1
1
1
1
Rn
Register by 1
1
1
2
2
dir8
Direct address (on–chip RAM or SFR) by 1
2
2(2)
2
2(2)
@Ri
Indirect address by 1
1
3
2
4
INC
DEC
Rm, #short
Byte register by 1, 2, or 4
3
2
2
1
WRj, #short
Word register by 1, 2, or 4
3
2
2
1
INC
DRk, #short
Double word register by 1, 2, or 4
3
4
2
3
DEC
DRk, #short
Double word register by 1, 2, or 4
3
5
2
4
INC
DPTR
Data pointer by 1
1
1
1
1
INC
DEC
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 22. Summary of Compare Instructions
Compare
Mnemonic
CMP
CMP <dest>, <src>
dest opnd – src opnd
Binary Mode
<dest> <src>(1)
<dest>,
Source Mode
Comments
Bytes
States
Bytes
States
Rmd, Rms
Register with register
3
2
2
1
WRjd, WRjs
Word register with word register
3
3
2
2
DRkd, DRks
Dword register with dword register
3
5
2
4
Rm, #data
Register with immediate data
4
3
3
2
WRj, #data16
Word register with immediate 16-bit data
5
4
4
3
DRk, #0data16
Dword register with zero-extended 16-bit immediate
data
5
6
4
5
DRk, #1data16
Dword register with one-extended 16-bit immediate data
5
6
4
5
Rm, dir8
Direct address (on–chip RAM or SFR) with byte register
4
3(1)
3
2(1)
WRj, dir8
Direct address (on–chip RAM or SFR) with word
register
4
4
3
3
Rm, dir16
Direct address (64K) with byte register
5
3(2)
4
2(2)
WRj, dir16
Direct address (64K) with word register
5
4(3)
4
3(3)
Rm, @WRj
Indirect address (64K) with byte register
4
3(2)
3
2(2)
Rm, @DRk
Indirect address (16M) with byte register
4
4(2)
3
3(2)
Notes:
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
18
Rev. A
– September 21, 1998
TSC87251G1A
Table 23. Summary of Logical Instructions (1/2)
Logical AND(1)
Logical OR(1)
Logical Exclusive OR(1)
Clear(1)
Complement(1)
Rotate Left
ANL <dest>, <src>
ORL <dest>, <src>
XRL <dest>, <src>
CLR A
CPL A
RL A
Rotate Left Carry
RLC A
Rotate Right
RR A
Rotate Right Carry
RRC A
Mnemonic
ANL
ORL
XRL
Binary Mode
<dest> <src>(2)
<dest>,
A, Rn
dest opnd ← dest opnd Λ src opnd
dest opnd ← dest opnd V src opnd
dest opnd ← dest opnd ∀ src opnd
(A) ← 0
(A) ← ∅ (A)
(A)n+1 ← (A)n, n= 0..6
(A)0 ← (A)7
(A)n+1 ← (A)n, n= 0..6
(CY) ← (A)7
(A)0 ← (CY)
(A)n–1 ← (A)n, n= 7..1
(A)7 ← (A)0
(A)n–1 ← (A)n, n= 7..1
(CY) ← (A)0
(A)7 ← (CY)
Source Mode
Comments
register to ACC
Bytes
States
Bytes
States
1
1
2
2
2
1(3)
A, dir8
Direct address (on–chip RAM or SFR) to ACC
2
1(3)
A, @Ri
Indirect address to ACC
1
2
2
3
A, #data
Immediate data to ACC
2
1
2
1
2
2(4)
dir8, A
ACC to direct address
2
2(4)
dir8, #data
Immediate 8–bit data to direct address
3
3(4)
3
3(4)
Rmd, Rms
Byte register to byte register
3
2
2
1
WRjd, WRjs
Word register to word register
3
3
2
2
Rm, #data
Immediate 8-bit data to byte register
4
3
3
2
WRj, #data16
Immediate 16-bit data to word register
5
4
4
3
Rm, dir8
Direct address to byte register
4
3(3)
3
2(3)
WRj, dir8
Direct address to word register
4
4
3
3
4
2(5)
Rm, dir16
Direct address (64K) to byte register
5
3(5)
WRj, dir16
Direct address (64K) to word register
5
4(6)
4
3(6)
Rm, @WRj
Indirect address (64K) to byte register
4
3(5)
3
2(5)
Rm, @DRk
Indirect address (16M) to byte register
4
4(5)
3
3(5)
CLR
A
Clear ACC
1
1
1
1
CPL
A
Complement ACC
1
1
1
1
RL
A
Rotate ACC left
1
1
1
1
RLC
A
Rotate ACC left through CY
1
1
1
1
RR
A
Rotate ACC right
1
1
1
1
RRC
A
Rotate ACC right through CY
1
1
1
1
Notes:
1. Logical instructions that affect a bit are in Table 29.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0–3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0–3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Rev. A
– September 21, 1998
19
TSC87251G1A
Table 24. Summary of Logical Instructions (2/2)
Shift Left Logical
SLL <dest>
Shift Right Arithmetic
SRA <dest>
Shift Right Logical
SRL <dest>
Swap
SWAP A
Mnemonic
SLL
SRA
<dest>0 ← 0
<dest>n+1 ← <dest>n, n= 0..msb–1
(CY) ← <dest>msb
<dest>msb ← <dest>msb
<dest>n–1 ← <dest>n, n= msb..1
(CY) ← <dest>0
<dest>msb ← 0
<dest>n–1 ← <dest>n, n= msb..1
(CY) ← <dest>0
A3:0 A7:4
Binary Mode
<dest> <src>(1)
<dest>,
Source Mode
Comments
Bytes
States
Bytes
States
Rm
Shift byte register left through the MSB
3
2
2
1
WRj
Shift word register left through the MSB
3
2
2
1
Rm
Shift byte register right
3
2
2
1
WRj
Shift word register right
3
2
2
1
Rm
Shift byte register left
3
2
2
1
WRj
Shift word register left
3
2
2
1
A
Swap nibbles within ACC
1
2
1
2
SRL
SWAP
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions
Multiply
Divide
MUL AB
MUL <dest>, <src>
DIV AB
Divide
DIV <dest>, <src>
Decimal-adjust ACC
for Addition (BCD)
DA A
Mnemonic
MUL
DIV
DA
(B:A) ← (A)×(B)
extended dest opnd ← dest opnd × src opnd
(A) ← Quotient ((A) ⁄ (B))
(B) ← Remainder ((A) ⁄ (B))
ext. dest opnd high ← Quotient (dest opnd ⁄ src opnd)
ext. dest opnd low ← Remainder (dest opnd ⁄ src opnd)
IF [[(A)3:0 > 9] ∨ [(AC)= 1]]
THEN (A)3:0 ← (A)3:0 + 6 !affects CY;
IF [[(A)7:4 > 9] ∨ [(CY)= 1]]
THEN (A)7:4 ← (A)7:4 + 6
Binary Mode
<dest> <src>(1)
<dest>,
Source Mode
Comments
Bytes
States
Bytes
States
AB
Multiply A and B
1
5
1
5
Rmd, Rms
Multiply byte register and byte register
3
6
2
5
WRjd, WRjs
Multiply word register and word register
3
12
2
11
AB
Divide A and B
1
10
1
10
Rmd, Rms
Divide byte register and byte register
3
11
2
10
WRjd, WRjs
Divide word register and word register
3
21
2
20
A
Decimal adjust ACC
1
1
1
1
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
20
Rev. A
– September 21, 1998
TSC87251G1A
Table 26. Summary of Move Instructions (1/3)
Move to High word
Move with Sign extension
Move with Zero extension
Move Code
Move eXtended
Mnemonic
dest opnd31:16 ← src opnd
dest opnd ← src opnd with sign extend
dest opnd ← src opnd with zero extend
(A) ← src opnd
dest opnd ← src opnd
MOVH <dest>, <src>
MOVS <dest>, <src>
MOVZ <dest>, <src>
MOVC A, <src>
MOVX <dest>, <src>
Binary Mode
<dest> <src>(1)
<dest>,
Source Mode
Comments
Bytes
States
Bytes
States
MOVH
DRk, #data16
16-bit immediate data into upper word of dword register
5
3
4
2
MOVS
WRj, Rm
Byte register to word register with sign extension
3
2
2
1
MOVZ
WRj, Rm
Byte register to word register with zeros extension
3
2
2
1
A, @A +DPTR
Code byte relative to DPTR to ACC
1
6(3)
1
6(3)
A, @A +PC
Code byte relative to PC to ACC
1
6(3)
1
6(3)
MOVC
MOVX
ACC(2)
A, @Ri
Extended memory (8-bit address) to
1
4
1
5
A, @DPTR
Extended memory (16-bit address) to ACC(2)
1
3(4)
1
3(4)
@Ri, A
ACC to extended memory (8-bit address)(2)
1
4
1
4
@DPTR, A
ACC to extended memory (16-bit address)(2)
1
4(3)
1
4(3)
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. Extended memory addressed is in the region specified by DPXL (reset value= 01h).
3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
Table 27. Summary of Move Instructions (2/3)
Move(1)
Mnemonic
dest opnd ← src opnd
MOV <dest>, <src>
Binary Mode
<dest> <src>(2)
<dest>,
Bytes
MOV
Source Mode
Comments
States
Bytes
States
A, Rn
Register to ACC
1
1
2
2
A, dir8
Direct address (on–chip RAM or SFR) to ACC
2
1(3)
2
1(3)
A, @Ri
Indirect address to ACC
1
2
2
3
A, #data
Immediate data to ACC
2
1
2
1
Rn, A
ACC to register
1
1
2
2
3
2(3)
Rn, dir8
Direct address (on–chip RAM or SFR) to register
2
1(3)
Rn, #data
Immediate data to register
2
1
3
2
2
2(3)
dir8, A
ACC to direct address
2
2(3)
dir8, Rn
Register to direct address
2
2(3)
3
3(3)
dir8, dir8
Direct address to direct address
3
3(4)
3
3(4)
3
4(3)
dir8, @Ri
Indirect address to direct address
2
3(3)
dir8, #data
Immediate data to direct address
3
3(3)
3
3(3)
@Ri, A
ACC to indirect address
1
3
2
4
3
4(3)
@Ri, dir8
Direct address to indirect address
2
3(3)
@Ri, #data
Immediate data to indirect address
2
3
3
4
DPTR, #data16
Load Data Pointer with a 16-bit constant
3
2
3
2
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions from the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. Apply note 3 for each dir8 operand.
Rev. A
– September 21, 1998
21
TSC87251G1A
Table 28. Summary of Move Instructions (3/3)
Move(1)
Mnemonic
MOV
dest opnd ← src opnd
MOV <dest>, <src>
<dest> <src>(2)
<dest>,
Binary Mode
Source Mode
Comments
Bytes
States
Bytes
States
Rmd, Rms
Byte register to byte register
3
2
2
1
WRjd, WRjs
Word register to word register
3
2
2
1
DRkd, DRks
Dword register to dword register
3
3
2
2
Rm, #data
Immediate 8-bit data to byte register
4
3
3
2
WRj, #data16
Immediate 16-bit data to word register
5
3
4
2
DRk, #0data16
zero-ext 16bit immediate data to dword register
5
5
4
4
DRk, #1data16
one-ext 16bit immediate data to dword register
5
5
4
4
3
2(3)
Rm, dir8
Direct address to byte register
4
3(3)
WRj, dir8
Direct address to word register
4
4
3
3
DRk, dir8
Direct address to dword register
4
6
3
5
4
2(4)
Rm, dir16
Direct address (64K) to byte register
5
3(4)
WRj, dir16
Direct address (64K) to word register
5
4(5)
4
3(5)
4
5(6)
DRk, dir16
Direct address (64K) to dword register
5
6(6)
Rm, @WRj
Indirect address (64K) to byte register
4
3(4)
3
2(4)
3
3(4)
Rm, @DRk
Indirect address (16M) to byte register
4
4(4)
WRjd, @WRjs
Indirect address (64K) to word register
4
4(5)
3
3(5)
WRj, @DRk
Indirect address (16M) to word register
4
5(5)
3
4(5)
3
3(3)
dir8, Rm
Byte register to direct address
4
4(3)
dir8, WRj
Word register to direct address
4
5
3
4
dir8, DRk
Dword register to direct address
4
7
3
6
4
3(4)
dir16, Rm
Byte register to direct address (64K)
5
4(4)
dir16, WRj
Word register to direct address (64K)
5
5(5)
4
4(5)
4
6(6)
dir16, DRk
Dword register to direct address (64K)
5
7(6)
@WRj, Rm
Byte register to indirect address (64K)
4
4(4)
3
3(4)
3
4(4)
@DRk, Rm
Byte register to indirect address (16M)
4
5(4)
@WRjd, WRjs
Word register to indirect address (64K)
4
5(5)
3
4(5)
@DRk, WRj
Word register to indirect address (16M)
4
6(5)
3
5(5)
4
5(4)
Rm, @WRj +dis16
Indirect with 16–bit dis (64K) to byte register
5
6(4)
WRj, @WRj +dis16
Indirect with 16–bit dis (64K) to word register
5
7(5)
4
6(5)
4
6(4)
Rm, @DRk +dis24
Indirect with 16–bit dis (16M) to byte register
5
7(4)
WRj, @WRj +dis24
Indirect with 16–bit dis (16M) to word register
5
8(5)
4
7(5)
@WRj +dis16, Rm
Byte register to indirect with 16–bit dis (64K)
5
6(4)
4
5(4)
4
6(5)
@WRj +dis16, WRj
Word register to indirect with 16–bit dis (64K)
5
7(5)
@DRk +dis24, Rm
Byte register to indirect with 16–bit dis (16M)
5
7(4)
4
6(4)
5
8(5)
4
7(5)
@DRk +dis24, WRj
Word register to indirect with 16–bit dis (16M)
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions unique to the C251 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).
22
Rev. A
– September 21, 1998
TSC87251G1A
Table 29. Summary of Bit Instructions
Clear Bit
Set Bit
Complement Bit
AND Carry with Bit
AND Carry with Complement of Bit
OR Carry with Bit
OR Carry with Complement of Bit
Move Bit to Carry
Move Bit from Carry
Mnemonic
CLR
SETB
CPL
dest opnd ← 0
dest opnd ← 1
dest opnd ← ∅ bit
(CY) ← (CY) ∧ src opnd
(CY) ← (CY) ∧ ∅ src opnd
(CY) ← (CY) ∨ src opnd
(CY) ← (CY) ∨ ∅ src opnd
(CY) ← src opnd
dest opnd ← (CY)
CLR <dest>
SETB <dest>
CPL <dest>
ANL CY, <src>
ANL CY, /<src>
ORL CY, <src>
ORL CY, /<src>
MOV CY, <src>
MOV <dest>, CY
Binary Mode
<dest> <src>(1)
<dest>,
Source Mode
Comments
Bytes
States
Bytes
States
CY
Clear carry
1
1
1
1
bit51
Clear direct bit
2
2(3)
2
2(3)
bit
Clear direct bit
4
4(3)
3
3(3)
CY
Set carry
1
1
1
1
2
2(3)
bit51
Set direct bit
2
2(3)
bit
Set direct bit
4
4(3)
3
3(3)
CY
Complement carry
1
1
1
1
2
2(3)
bit51
Complement direct bit
2
2(3)
bit
Complement direct bit
4
4(3)
3
3(3)
CY, bit51
And direct bit to carry
2
1(2)
2
1(2)
CY, bit
And direct bit to carry
4
3(2)
3
2(2)
CY, /bit51
And complemented direct bit to carry
2
1(2)
2
1(2)
CY, /bit
And complemented direct bit to carry
4
3(2)
3
2(2)
CY, bit51
Or direct bit to carry
2
1(2)
2
1(2)
CY, bit
Or direct bit to carry
4
3(2)
3
2(2)
CY, /bit51
Or complemented direct bit to carry
2
1(2)
2
1(2)
CY, /bit
Or complemented direct bit to carry
4
3(2)
3
2(2)
CY, bit51
Move direct bit to carry
2
1(2)
2
1(2)
CY, bit
Move direct bit to carry
4
3(2)
3
2(2)
bit51, CY
Move carry to direct bit
2
2(3)
2
2(3)
bit, CY
Move carry to direct bit
4
4(3)
3
3(3)
ANL
ORL
MOV
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0–3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0–3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Rev. A
– September 21, 1998
23
TSC87251G1A
Table 30. Summary of Exchange, Push and Pop Instructions
Exchange bytes
Exchange Digit
Push
XCH A, <src>
XCHD A, <src>
PUSH <src>
Pop
POP <dest>
Mnemonic
(A) src opnd
(A)3:0 src opnd3:0
(SP) ← (SP) +1; ((SP)) ← src opnd;
(SP) ← (SP) + size (src opnd) – 1
(SP) ← (SP) – size (dest opnd) + 1;
dest opnd ← ((SP)); (SP) ← (SP) –1
Binary Mode
<dest> <src>(1)
<dest>,
Bytes
XCH
XCHD
Source Mode
Comments
States
Bytes
States
A, Rn
ACC and register
1
3
2
4
A, dir8
ACC and direct address (on–chip RAM or SFR)
2
3(3)
2
3(3)
A, @Ri
ACC and indirect address
1
4
2
5
A, @Ri
ACC low nibble and indirect address (256 bytes)
1
4
2
5
dir8
Push direct address onto stack
2
2(2)
2
2(2)
#data
Push immediate data onto stack
4
4
3
3
#data16
Push 16-bit immediate data onto stack
5
5
4
5
Rm
Push byte register onto stack
3
4
2
3
WRj
Push word register onto stack
3
5
2
4
DRk
Push double word register onto stack
3
9
2
8
dir8
Pop direct address (on–chip RAM or SFR) from stack
2
3(2)
2
3(2)
Rm
Pop byte register from stack
3
3
2
2
WRj
Pop word register from stack
3
5
2
4
DRk
Pop double word register from stack
3
9
2
8
PUSH
POP
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 31. Summary of Conditional Jump Instructions (1/2)
Jump conditional on status
Mnemonic
JC
<dest> <src>(1)
<dest>,
rel
(PC) ← (PC) + size (instr);
IF [cc] THEN (PC) ← (PC) + rel
Jcc rel
Binary Mode(2)
Source Mode(2)
Bytes
States
Bytes
States
2
1/4(3)
2
1/4(3)
2
1/4(3)
Comments
Jump if carry
JNC
rel
Jump if not carry
2
1/4(3)
JE
rel
Jump if equal
3
2/5(3)
2
1/4(3)
2
1/4(3)
JNE
rel
Jump if not equal
3
2/5(3)
JG
rel
Jump if greater than
3
2/5(3)
2
1/4(3)
3
2/5(3)
2
1/4(3)
2
1/4(3)
JLE
rel
Jump if less than, or equal
JSL
rel
Jump if less than (signed)
3
2/5(3)
JSLE
rel
Jump if less than, or equal (signed)
3
2/5(3)
2
1/4(3)
2
1/4(3)
2
1/4(3)
JSG
rel
Jump if greater than (signed)
3
2/5(3)
JSGE
rel
Jump if greater than or equal (signed)
3
2/5(3)
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
24
Rev. A
– September 21, 1998
TSC87251G1A
Table 32. Summary of Conditional Jump Instructions (2/2)
Jump if bit
JB <src>, rel
Jump if not bit
JNB <src>, rel
Jump if bit and clear
JBC <dest>, rel
Jump if accumulator is zero
JZ rel
Jump if accumulator is not zero
JNZ rel
Compare and jump if not equal
CJNE <src1>, <src2>, rel
Decrement and jump if not zero
DJNZ <dest>, rel
Mnemonic
<dest> <src>(1)
<dest>,
bit51, rel
JB
JNB
bit, rel
JZ
JNZ
Bytes
States
Bytes
States
Jump if direct bit is set
3
2/5(3)(6)
3
2/5(3)(6)
5
4/7(3)(6)
Jump if direct bit of 8-bit address location is set
4
3/6(3)(6)
3
2/5(3)(6)
Jump if direct bit is not set
3
bit, rel
Jump if direct bit of 8-bit address location is not set
5
4/7(3)(6)
4
3/6(3)
3
4/7(5)(6)
3
4/7(5)(6)
4
6/9(5)(6)
Jump if direct bit is set & clear bit
bit, rel
Jump if direct bit of 8-bit address location is set and clear
5
7/10(5)(6)
rel
Jump if ACC is zero
2
2/5(6)
2
2/5(6)
2
2/5(6)
rel
Jump if ACC is not zero
2
2/5(6)
A, dir8, rel
Compare direct address to ACC and jump if not equal
3
2/5(3)(6)
3
2/5(3)(6)
3
2/5(6)
3
2/5(6)
4
3/6(6)
Compare immediate to ACC and jump if not equal
Rn, #data, rel
Compare immediate to register and jump if not equal
3
2/5(6)
@Ri, #data, rel
Compare immediate to indirect and jump if not equal
3
3/6(6)
4
4/7(6)
2
2/5(6)
3
3/6(6)
3
3/6(4)(6)
3
3/6(4)(6)
Rn, rel
DJNZ
Source Mode(2)
bit51, rel
A, #data, rel
CJNE
Binary Mode(2)
Comments
2/5(3)(6)
bit51, rel
JBC
(PC) ← (PC) + size (instr);
IF [src opnd= 1] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [src opnd= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [dest opnd= 1] THEN
dest opnd ← 0
(PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [(A)= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [(A) ≠ 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [src opnd1 < src opnd2] THEN (CY) ← 1
IF [src opnd1 ≥ src opnd2] THEN (CY) ← 0
IF [src opnd1 ≠ src opnd2] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr); dest opnd ← dest opnd –1;
IF [∅ (Z)] THEN (PC) ← (PC) + rel
dir8, rel
Decrement register and jump if not zero
Decrement direct address and jump if not zero
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR.
6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
Rev. A
– September 21, 1998
25
TSC87251G1A
Table 33. Summary of unconditional Jump Instructions
Absolute jump
Extended jump
Long jump
Short jump
Jump indirect
No operation
Mnemonic
AJMP
EJMP
SJMP
JMP
Binary Mode
<dest> <src>(1)
<dest>,
addr11
Source Mode
Comments
Absolute jump
Bytes
States
Bytes
States
2
3(2)(3)
2
3(2)(3)
4
5(2)(4)
addr24
Extended jump
5
6(2)(4)
@DRk
Extended jump (indirect)
3
7(2)(4)
2
6(2)(4)
3
6(2)(4)
2
5(2)(4)
3
5(2)(4)
@WRj
LJMP
(PC) ← (PC) +2; (PC)10:0 ← src opnd
(PC) ← (PC) + size (instr); (PC)23:0 ← src opnd
(PC) ← (PC) + size (instr); (PC)15:0 ← src opnd
(PC) ← (PC) +2; (PC) ← (PC) +rel
(PC)23:16 ← FFh; (PC)15:0 ← (A) + (DPTR)
(PC) ← (PC) +1
AJMP <src>
EJMP <src>
LJMP <src>
SJMP rel
JMP @A +DPTR
NOP
Long jump (indirect)
addr16
Long jump (direct address)
3
5(2)(4)
rel
Short jump (relative address)
2
4(2)(4)
2
4(2)(4)
Jump indirect relative to the DPTR
1
5(2)(4)
1
5(2)(4)
No operation (Jump never)
1
1
1
1
@A +DPTR
NOP
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 3 to the number of states if the destination address is external.
Table 34. Summary of Call and Return Instructions
Absolute call
ACALL <src>
Extended call
ECALL <src>
Long call
LCALL <src>
Return from subroutine
Extended return from subroutine
Return from interrupt
RET
ERET
RETI
Trap interrupt
TRAP
Mnemonic
ACALL
ECALL
LCALL
(PC) ← (PC) +2; push (PC)15:0;
(PC)10:0 ← src opnd
(PC) ← (PC) + size (instr); push (PC)23:0;
(PC)23:0 ← src opnd
(PC) ← (PC) + size (instr); push (PC)15:0;
(PC)15:0 ← src opnd
pop (PC)15:0
pop (PC)23:0
IF [INTR= 0] THEN pop (PC)15:0
IF [INTR= 1] THEN pop (PC)23:0; pop (PSW1)
(PC) ← (PC) + size (instr);
IF [INTR= 0] THEN push (PC)15:0
IF [INTR= 1] THEN push (PSW1); push (PC)23:0
Binary Mode
<dest> <src>(1)
<dest>,
Source Mode
Comments
Bytes
States
Bytes
States
2
9(2)(3)
addr11
Absolute subroutine call
2
9(2)(3)
@DRk
Extended subroutine call (indirect)
3
14(2)(3)
2
13(2)(3)
5
14(2)(3)
4
13(2)(3)
2
9(2)(3)
addr24
Extended subroutine call
@WRj
Long subroutine call (indirect)
3
10(2)(3)
addr16
Long subroutine call
3
9(2)(3)
3
9(2)(3)
1
7(2)
RET
Return from subroutine
1
7(2)
ERET
Extended subroutine return
3
9(2)
2
8(2)
1
7(2)(4)
1
7(2)(4)
2
12(4)
1
11(4)
RETI
TRAP
Return from interrupt
Jump to the trap interrupt vector
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR= 1.
26
Rev. A
– September 21, 1998
TSC87251G1A
8. EPROM Programming
8.1. Internal ROM Features
The internal ROM of the TSC87251G1A products contains five different areas:
Code Memory
Configuration Bytes
Lock Bits
Encryption Array
Signature Bytes
8.1.1. EPROM/OTPROM Devices
All the Internal ROM but the Signature Bytes of the TSC87251G1A products is made of EPROM cells. The Signature
Bytes of the TSC87251GxD products are made of Mask ROM.
The TSC87251G1A products are programmed and verified in the same manner as TEMIC’s TSC87251G1 and
TSC87251A1A, using a SINGLE–PULSE algorithm, which programs at VPP= 12.75V using only one 100 µs pulse
per byte. This results in a programming time of less than 5 seconds for the 16 Kbytes on–chip code memory.
The EPROM of TSC87251G1A products in Window CQPJ is erasable by Ultra–Violet radiation (UV). UV erasure set
all the EPROM memory cells to one and allows a reprogramming. The quartz window must be covered with an opaque
label when the device is in operation. This is not so much to protect the EPROM array from inadvertent erasure, as
to protect the RAM and other on–chip logic. Allowing light to impinge on the silicon die during device operation may
cause a logical malfunction.
Note:
Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000Å. Since sunlight and fluorescent light have
wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room–level fluorescent lighting) could
cause inadvertent erasure.
The TSC87251G1A products in plastic packages are One Time Programmable (OTP). Then an EPROM cell cannot
be reset by UV once programmed to zero.
8.1.2. Security Features
In some microcontrollers applications, it is desirable that the user program code be secured from unauthorized access.
The TSC87251G1A offers two kinds of protection for program code stored in the on–chip array:
Program code in the on–chip Code Memory is encrypted when read out for verification if the Encryption Array is
programmed.
A three–level lock bit system restricts external access to the on–chip code memory.
8.1.3. Lock Bit System
The TSC87251G1A products implement 3 levels of security for User’s program as described in Table 35.
The first level locks the programming of the User’s internal Code Memory, the Configuration Bytes and the Encryption
Array.
The second level locks the verifying of the User’s internal Code Memory. It is always possible to verify the Configuration Bytes and the Lock Bits. It is never possible to verify the Encryption Array.
The third level locks the external execution.
Rev. A
– September 21, 1998
27
TSC87251G1A
Table 35. Lock bits Programming
Level
Lock bits
LB[2:0]
Internal
Execution
External
Execution
Verification
Programming
External
PROM read
(MOVC)
0
000
Enable
Enable
Enable(1)
Enable
Enable(2)
1
001
Enable
Enable
Enable1)
Disable
Disable
2
011
Enable
Enable
Disable
Disable
Disable
3
111
Enable
Disable
Disable
Disable
Disable
Reserved
Other
x
x
x
x
x
Notes:
1. Returns encrypted data if Encryption Array is programmed.
2. Returns non encrypted data.
Level 1 should be set before programming Level 2; Level 2 should be set before programming Level 3.
The security level may be verified according to Table 36.
Table 36. Lock bits Verifying
Level
Lock bits Data(1)
0
xxxxx000
1
xxxxx001
2
xxxxx01x
3
xxxxx1xx
Note:
1. x means don’t care.
8.1.4. Encryption Array
The TSC87251G1A products include a 128–byte Encryption Array located in non–volatile memory outside the
memory address space. During verification of the on–chip code memory, the seven low–order address bits also address
the Encryption Array. As the byte of the code memory is read, it is exclusive–NOR’ed (XNOR) with the key byte from
the Encryption Array. If the Encryption Array is not programmed (still all 1s), the user program code is placed on the
data bus in its original, unencrypted form. If the Encryption Array is programmed with key bytes, the user program
code is encrypted and cannot be used without knowledge of the key byte sequence.
To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified.
Cautions:
1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In order to fully protect the user program code, the lock bit
level 1 (see Table 1) must always be set when encryption is used.
2. If the encryption feature is implemented, the portion of the on–chip code memory that does not contain program code should be filled with
“random” byte values to prevent the encryption key sequence from being revealed.
8.2. Signature Bytes
The TSC87251G1A products contain factory–programmed Signature Bytes. These bytes are located in non–volatile
memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the procedure described in section 8.4., “Verify Algorithm”, using the verify signature mode (see Table 39). Signature byte values are listed in Table 37.
28
Rev. A
– September 21, 1998
TSC87251G1A
Table 37. Signature Bytes (Electronic ID)
Signature Address
Signature Data
Vendor
TEMIC
30h
58h
Architecture
C251
31h
40h
Memory
16K EPROM/OTPROM
60h
FBh
Revision
First (TSC8x251G1A)
61h
FFh
8.3. Programming Algorithm
Figure 8 shows the hardware setup needed to program the TSC87251G1A EPROM areas:
The chip has to be put under reset and maintained in this state until the completion of the programming sequence.
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state
until the completion of the programming sequence (see below).
The voltage on the EA# pin must be set to VDD.
The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied until
the completion of this programming operation.
The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB) and
the Least Significant Byte (LSB) of the address.
The programming data are applied on Port 2.
The EPROM Programming is done by raising the voltage on the EA# pin to VPP, then by generating a low level
pulse on ALE/PROG# pin.
The voltage on the EA# pin must be lowered to VDD before completing the programming operation.
It is possible to alternate programming and verifying operation (See paragraph 8.4.). Please make sure the voltage
on the EA# pin has actually been lowered to VDD before performing the verifying operation.
PSEN# and the other control signals have to be released to complete a sequence of programming operations or a
sequence of programming and verifying operations.
VDD
VDD
VDD
RST
VPP
100 µs pulses
Mode
EA#/VPP
ALE/PROG#
PSEN#
P0[7:0]
TSC87251G1A
A[7:0]
P3[7:0]
XTAL1
A[13:8]
P1[7:0]
Data
P2[7:0]
4 to 12 MHz
VSS/VSS1/VSS2
Figure 8. Setup for EPROM Programming
Rev. A
– September 21, 1998
29
TSC87251G1A
Table 38. Programming Modes
ROM Area(1)
PSEN# ALE/PROG#(2)
RST
EA#/VPP
P0
P2
P1(MSB) P3(LSB)
On–chip Code Memory
1
VPP
0
1 Pulse
68h
Data
16–bit Address
0000h-3FFFh (16K)
Configuration Bytes
1
VPP
0
1 Pulse
69h
Data
CONFIG0: 0080h
CONFIG1: 0081h
Lock Bits
1
VPP
0
1 Pulse
6Bh
X
LB0: 0001h
LB1: 0002h
LB2: 0003h
Encryption Array
1
VPP
0
1 Pulse
6Ch
Data
0000h-007Fh
Notes:
1. Signature Bytes are not user–programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 24 page 46.
8.4. Verify Algorithm
Figure 9 shows the hardware setup needed to verify the TSC87251G1A EPROM areas:
The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state
until the completion of the verifying sequence (see below).
The voltage on the EA# pin must be set to VDD and ALE must be set to a high level.
The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion of
this verifying operation.
The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.
Then device is driving the data on Port 2.
It is possible to alternate programming and verification operation (see paragraph 8.3.). Please make sure the voltage
on the EA# pin has actually been lowered to VDD before performing the verifying operation.
PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a
sequence of programming and verifying operations.
Table 39. Verifying Modes
ROM Area(1)
RST
EA#/VPP
PSEN#
ALE/PROG#
P0
P2
P1(MSB) P3(LSB)
On–chip code memory
1
1
0
1
28h
Data
16–bit Address
0000h-3FFFh (16K)
Configuration Bytes
1
1
0
1
29h
Data
CONFIG0: 0080h
CONFIG1: 0081h
Lock Bits
1
1
0
1
2Bh
Data
0000h
Signature Bytes
1
1
0
1
29h
Data
0030h, 0031h, 0060h, 0061h
Note:
1. To preserve the secrecy of on–chip code memory when encypted, the Encryption Array can not be verified.
30
Rev. A
– September 21, 1998
TSC87251G1A
VDD
VDD
VDD
RST
EA#/VPP
ALE/PROG#
PSEN#
Mode
P2[7:0]
Data
P0[7:0]
TSC87251G1A
A[7:0]
P3[7:0]
XTAL1
A[13:8]
4 to 12 MHz
P1[7:0]
VSS/VSS1/VSS2
Figure 9. Setup for EPROM Verifying
Rev. A
– September 21, 1998
31
TSC87251G1A
9. Absolute Maximum Rating and Operating Conditions
9.1. Absolute Maximum Rating
Table 40. Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . .
–65 to +150°C
Voltage on any other Pin to VSS . . . . . . . . . . .
–0.5 to +6.5 V
Voltage on EA#/VPP Pin to VSS . . . . . . . . . . .
0 to +13.0 V
IOL per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . .
15 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . .
1.5 W
9.2. Operating Conditions
Table 41. Operating Conditions
Ambient Temperature Under Bias
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . .
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0 to +70°C
–40 to +85°C
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 to 5.5 V
Note:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the
“operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
32
Rev. A
– September 21, 1998
TSC87251G1A
10. DC Characteristics – Commercial & Industrial
Table 42. DC Characteristics; VDD= 4.5 to 5.5 V, TA= –40 to +85°C
Symbol
Parameter
Min
Input Low Voltage
(except EA#, SCL, SDA)
VIL1(5)
Typical(4)
Max
Units
–0.5
0.2VDD - 0.1
V
Input Low Voltage
(SCL, SDA)
–0.5
0.3VDD
V
VIL2
Input Low Voltage
(EA#)
0
0.2VDD - 0.3
V
VIH
Input high Voltage
(except XTAL1, RST, SCL, SDA)
0.2VDD + 0.9
VDD + 0.5
V
0.7VDD
VDD + 0.5
V
VIL
VIH1(5)
Input high Voltage
(XTAL1, RST, SCL, SDA)
Test Conditions
VOL
Output Low Voltage
(Ports 1, 2, 3)
0.3
0.45
1.0
V
IOL= 100 µA(1)(2)
IOL= 1.6 mA(1)(2)
IOL= 3.5 mA(1)(2)
VOL1
Output Low Voltage
(Ports 0, ALE, PSEN#,Port 2 in Page
Mode during External Address)
0.3
0.45
1.0
V
IOL= 200 µA(1)(2)
IOL= 3.2 mA(1)(2)
IOL= 7.0 mA(1)(2)
VOH
Output high Voltage
(Ports 1, 2, 3, ALE, PSEN#)
VDD –0.3
VDD –0.7
VDD –1.5
V
IOH= –10 µA(3)
IOH= –30 µA(3)
IOH= –60 µA(3)
VOH1
Output high Voltage
(Port 0, Port 2 in Page Mode during
External Address)
VDD –0.3
VDD –0.7
VDD –1.5
V
IOH= –200 µA
IOH= –3.2 mA
IOH= –7.0 mA
VRST+
Reset threshold on
3.7
VRST–
Reset threshold off
3.3
VRET
VDD data retention limit
1.8
V
IIL0
Logical 0 Input Current
(Ports 1, 2, 3)
- 50
µA
VIN= 0.45 V
ILI
Input Leakage Current
(Port 0)
± 10
µA
0.45 V < VIN < VDD
ITL
Logical 1-to-0 Transition Current
(Ports 1, 2, 3)
- 650
µA
VIN= 2.0 V
225
kW
pF
TA= 25°C
35
65
mA
FOSC= 12 MHz
45
80
mA
FOSC= 16 MHz
10
15
mA
FOSC= 12 MHz
15
20
mA
FOSC= 16 MHz
10
20
µA
VRET < VDD < 5.5 V
13
V
TA= 0 to +40°C
75
mA
TA= 0 to +40°C
RRST
CIO
IDD
RST Pull–Down Resistor
Idle Mode Current
IPD
Power–Down Current
VPP
Programming Supply Voltage
IPP
Programming Supply Current
– September 21, 1998
170
V
10
Operating Current
IDL
Rev. A
40
Pin Capacitance
V
12,5
33
TSC87251G1A
Notes:
1. Under steady–state (non–transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Maximum IOL per 8–bit port:
Port 0 . . . . . . . 26 mA
Ports 1-3 . . . . . 15 mA
Maximum Total IOL for all:
Output Pins . . . 71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low–level outputs of ALE and Ports 1, 2, and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In applications where
capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a
Schmitt Trigger or CMOS–level input logic.
3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
4. Typical values are obtained using VDD = 5 V and TA = 25°C with no guarantee.
They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the I 2C specification, so an input voltage below 0.3.VDD will be recognized as a logic 0 while an
input voltage above 0.7.VDD will be recognized as a logic 1.
80
IDD/IDL (mA)
60
40
20
0
2
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
4
6
8
10
12
14
16
Frequency at XTAL(1) (MHz)
Note:
1. The clock prescaler is not used: FOSC = FXTAL .
Figure 10. IDD/IDL versus Frequency; VDD= 4.5 to 5.5 V
34
Rev. A
– September 21, 1998
TSC87251G1A
10.1. DC Characteristics: IDD, IDL and IPD Test Conditions
VDD
IDD
VDD
VDD
VDD
P0
RST
EA#/VPP
TSC87251G1A
(NC)
Clock Signal
XTAL2
XTAL1
VSS
All other pins are unconnected
Figure 11. IDD Test Condition, Active Mode
VDD
IDL
VDD
VDD
P0
RST
EA#/VPP
TSC87251G1A
(NC)
Clock Signal
XTAL2
XTAL1
VSS
All other pins are unconnected
Figure 12. IDL Test Condition, Idle Mode
VDD
IPD
VDD
VDD
P0
RST
EA#/VPP
TSC87251G1A
(NC)
XTAL2
XTAL1
VSS
All other pins are unconnected
Figure 13. IPD Test Condition, Power–Down Mode
Rev. A
– September 21, 1998
35
TSC87251G1A
11. AC Characteristics – Commercial & Industrial
11.1. AC Characteristics – External Bus Cycles
Definition of symbols
Table 43. External Bus Cycles Timing Symbol Definitions
Signals
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
No Longer Valid
R
RD#/PSEN#
Z
Floating
W
WR#
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 44 lists AC timing parameters for the TSC87251G1A with no wait states. External wait states can be added by
extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE
wait state, and Note 3 marks parameters affected by one PSEN#/RD#/WR# wait state.
Figure 14 to Figure 19 show the bus cycles with the timing parameters.
36
Rev. A
– September 21, 1998
TSC87251G1A
Table 44. Bus Cycles AC Timings; VDD= 4.5 to 5.5 V, TA= –40 to 85°C
16 MHz
Symbol
FOSC Variable
Parameter
Min
Max
Min
Unit
Max
TOSC
1/FOSC
63
TLHLL
ALE Pulse Width
53
TOSC–10
ns(2)
TAVLL
Address Valid to ALE Low
43
TOSC–20
ns(2)
TLLAX
Address hold after ALE Low
43
TOSC–20
ns
RD#/PSEN# Pulse Width
45
TOSC–18
ns(3)
TRHRL
RD#/PSEN# High to RD#/PSEN# Low
53
TOSC–10
ns
TWLWH
WR# Pulse Width
45
TOSC–18
ns(3)
TLLRL(1)
ALE Low to RD#/PSEN# Low
53
TOSC–10
ns
ALE High to Address Hold
105
2×TOSC–20
ns(2)
TRLRH(1)
TLHAX
ns
ns(3)
TRLDV(1)
RD#/PSEN# Low to Valid Data
TRHDX(1)
Data Hold After RD#/PSEN# High
0
0
ns
TRHAX(1)
Address Hold After RD#/PSEN# High
0
0
ns
TRLAZ(1)
RD#/PSEN# Low to Address Float
2
2
ns
TRHDZ1
Instruction Float After RD#/PSEN# High
43
TOSC–20
ns
TRHDZ2
Data Float After RD#/PSEN# High
43
TOSC–20
ns
TRHLH1
RD#/PSEN# high to ALE High (Instruction)
48
TOSC–15
ns
TRHLH2
RD#/PSEN# high to ALE High (Data)
173
3×TOSC–15
ns
TWHLH
WR# High to ALE High
173
3×TOSC–15
43
TOSC–20
ns
TAVDV1
Address (P0) Valid to Valid Data In
190
3×TOSC–60
ns(2)(3)
TAVDV2
Address (P2) Valid to Valid Data In
273
4×TOSC–60
ns(2)(3)
TAVDV3
Address (P0) Valid to Valid Instruction In
128
3×TOSC–60
ns
TAXDX
Data Hold after Address Hold
0
0
ns
TAVRL(1)
Address Valid to RD# Low
101
2×TOSC–24
ns (2)
TAVWL1
Address (P0) Valid to WR# Low
101
2×TOSC–24
ns (2)
TAVWL2
Address (P2) Valid to WR# Low
158
3×TOSC–30
ns (2)
TWHQX
Data Hold after WR# High
43
TOSC–20
ns
TQVWH
Data Valid to WR# High
38
TOSC–25
ns(3)
TWHAX
WR# High to Address Hold
105
2×TOSC–20
ns
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2×TOSC.
3. If a wait state is added by extending RD#/PSEN#/WR#, add 2×TOSC .
Rev. A
– September 21, 1998
37
TSC87251G1A
Waveforms in Non–Page Mode
TLHLL(1)
ALE
TLLRL(1)
TRLRH(1)
TRHLH1
RD#/PSEN#
TRLDV(1)
TRLAZ
TLHAX(1)
TAVLL(1) TLLAX
A7:0
P0
TAVRL(1)
TAVDV1(1)
TRHDZ1
TRHDX
D7:0
Instruction In
TRHAX
TAVDV2(1)
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 14. External Bus Cycle: Code Fetch (Non–Page Mode)
ALE
TLHLL(1)
TLLRL(1)
TRLRH(1)
TRHLH2
RD#/PSEN#
TRLDV(1)
TRLAZ
TLHAX(1)
TAVLL(1) TLLAX
P0
A7:0
TRHDZ2
TRHDX
D7:0
Data In
TAVRL(1)
TAVDV1(1)
TRHAX
TAVDV2(1)
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 15. External Bus Cycle: Data Read (Non–Page Mode)
38
Rev. A
– September 21, 1998
TSC87251G1A
ALE
TLHLL(1)
TWLWH(1)
TWHLH
WR#
TLHAX(1)
TAVLL(1)
TQVWH
TLLAX
TWHQX
A7:0
P0
D7:0
Data Out
TAVWL1(1)
TWHAX
TAVWL2(1)
A15:8/A16/A17
P2/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 16. External Bus Cycle: DataWrite (Non–Page Mode)
Waveforms in Page Mode
ALE
TLHLL(1)
TLLRL(1)
TRLRH(1)
TRHRL
TRHLH1
RD#/PSEN#(3)
TRLDV(1)
TRLAZ
TLHAX(1)
TAVLL(1)
TLLAX
A15:8
P2
TAVRL(1)
TAVDV1(1)
TAVDV2(1)
P0/A16/A17
TRHDZ1
TRHDX
D7:0
D7:0
Instruction In
TAXDX
Instruction In
TAVDV3(1)
A7:0/A16/A17
A7:0/A16/A17
Page Miss(2)
Page hit(2)
TRHAX
Notes:
1. The value of this parameter depends on wait states. See Table 44.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch) requires one state (2×TOSC ); a page miss requires two
states (4×TOSC ).
3. During a sequence of page hits, PSEN# toggles between each byte fetching.
Figure 17. External Bus Cycle: Code Fetch (Page Mode)
Rev. A
– September 21, 1998
39
TSC87251G1A
ALE
TLHLL(1)
TLLRL(1)
TRLRH(1)
TRHLH2
RD#/PSEN#
TRLDV(1)
TRLAZ
TLHAX(1)
TAVLL(1) TLLAX
P2
TRHDZ2
TRHDX
A7:0
D7:0
Data In
TAVRL(1)
TRHAX
TAVDV1(1)
TAVDV2(1)
P0/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 18. External Bus Cycle: Data Read (Page Mode)
ALE
TLHLL(1)
TWLWH(1)
TWHLH
WR#
TLHAX(1)
TAVLL(1)
TLLAX
A7:0
P2
P0/A16/A17
TWHQX
D7:0
Data Out
TAVWL1(1)
TAVWL2
TQVWH
TWHAX
(1)
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 19. External Bus Cycle: DataWrite (Page Mode)
40
Rev. A
– September 21, 1998
TSC87251G1A
11.2. AC Characteristics – Serial Port in Shift Register Mode
Definition of symbols
Table 45. Serial Port Timing Symbol Definitions
Signals
Conditions
D
Data In
H
High
Q
Data Out
L
Low
X
Clock
V
Valid
X
No Longer Valid
Timings
Table 46. Serial Port AC Timing –Shift Register Mode; VDD= 4.5 to 5.5 V, TA= –40 to 85°C
16 MHz
Symbol
FOSC Variable
Parameter
Min
Max
Min
Unit
Max
TXLXL
Serial Port Clock Cycle Time
756
12×TOSC
ns
TQVXH
Output Data Setup to Clock Rising Edge
620
12×TOSC–136
ns
TXHQX
Output Data hold after Clock Rising Edge
510
10×TOSC–120
ns
TXHDX
Input Data Hold after Clock Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input Data Valid
500
10×TOSC–130
ns
Waveforms
TXLXL
TXD
TXHQX
TQVXH
RXD
(Out)
0
1
2
Valid
3
4
5
6
7
Set RI(1)
TXHDX
TXHDV
RXD
(In)
Set TI(1)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Note:
1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
Figure 20. Serial Port Waveforms – Shift Register Mode
Rev. A
– September 21, 1998
41
TSC87251G1A
11.3. AC Characteristics – SSLC: I2C Interface
Timings
Table 47. I2C Interface AC Timing; VDD= 4.5 to 5.5 V, TA= –40 to 85°C
Symbol
Parameter
INPUT
OUTPUT
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Min
Max
Min
Max
THD; STA
Start condition hold time
14×TCLCL (4)
4.0 µs (1)
TLOW
SCL low time
16×TCLCL (4)
4.7 µs (1)
THIGH
SCL high time
14×TCLCL (4)
4.0 µs (1)
TRC
SCL rise time
1 µs
– (2)
TFC
SCL fall time
0.3 µs
0.3 µs (3)
TSU; DAT1
Data set–up time
250 ns
20×TCLCL (4)– TRD
TSU; DAT2
SDA set–up time (before repeated START condition)
250 ns
1 µs (1)
TSU; DAT3
SDA set–up time (before STOP condition)
250 ns
8×TCLCL (4)
THD; DAT
Data hold time
0 ns
8×TCLCL (4) – TFC
TSU; STA
Repeated START set–up time
14×TCLCL (4)
4.7 µs (1)
TSU; STO
STOP condition set–up time
14×TCLCL (4)
4.0 µs (1)
TBUF
Bus free time
14×TCLCL (4)
4.7 µs (1)
TRD
SDA rise time
1 µs
– (2)
TFD
SDA fall time
0.3 µs
0.3 µs (3)
Notes:
1. At 100 kbit/s. At other bit–rates this value is inversely proportional to the bit–rate of 100 kbit/s.
2. Determined by the external bus–line capacitance and the external bus–line pull–up resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3×TCLCL will be filtered out. Maximum capacitance on bus–lines SDA and
SCL= 400 pF.
4. TCLCL= TOSC = one oscillator clock period.
Waveforms
START or repeated START condition
Repeated START condition
START condition
STOP condition
TRD
TSU;STA
SDA
(INPUT/OUTPUT)
0.7 VDD
0.3 VDD
TBUF
TFD
TRC
TFC
TSU;STO
SCL
(INPUT/OUTPUT)
0.7 VDD
0.3 VDD
TSU;DAT3
THD;STA
TLOW
THIGH
TSU;DAT1
THD;DAT
TSU;DAT2
Figure 21. I2C Waveforms
42
Rev. A
– September 21, 1998
TSC87251G1A
11.4. AC Characteristics – SSLC: SPI Interface
Definition of symbols
Table 48. SPI Interface Timing Symbol Definitions
Signals
Conditions
C
Clock
H
High
I
Data In
L
Low
O
Data Out
V
Valid
X
No Longer Valid
Timings
Table 49. SPI Interface AC Timing; VDD= 4.5 to 5.5 V, TA= –40 to 85°C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
Symbol
Parameter
Min
Max
Unit
Master mode(1)
TCHCH
Clock Period
4
TOSC
TCHCX
Clock High Time
1.6
TOSC
TCLCX
Clock Low Time
1.6
TOSC
TIVCL, TIVCH
Input Data Valid to Clock Edge
50
ns
TCLIX, TCHIX
Input Data Hold after Clock Edge
50
ns
TCLOV, TCHOV
Output Data Valid after Clock Edge
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
TILIH
Input Data Rise Time
2
µs
TIHIL
Input Data Fall Time
2
µs
TOLOH
Output Data Rise time
50
ns
TOHOL
Output Data Fall Time
50
ns
65
0
ns
ns
Notes:
1. Capacitive load on all pins= 100 pF in master mode.
Rev. A
– September 21, 1998
43
TSC87251G1A
Waveforms
SS#(1) (output)
TCHCH
SCK
(SSCPOL=0)
(output)
TCHCX
TCLCX
SCK
(SSCPOL=1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MISO
(input)
LSB IN
BIT 6
MSB IN
TCLOV
TCHOV
MOSI
(output)
Port Data
MSB OUT
TCLOX
TCHOX
LSB OUT
BIT 6
Port Data
Note:
1. SS# handled by software.
Figure 22. SPI Master Waveforms (SSCPHA= 0)
SS#(1) (output)
TCLCH
TCHCH
SCK
(SSCPOL=0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL=1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MISO
(input)
MSB IN
TCHOV
TCLOV
MOSI
(output)
Port Data
MSB OUT
BIT 6
LSB IN
TCHOX
TCLOX
BIT 6
LSB OUT
Port Data
Note:
1. SS# handled by software.
Figure 23. SPI Master Waveforms (SSCPHA= 1)
44
Rev. A
– September 21, 1998
TSC87251G1A
11.5. AC Characteristics – EPROM Programming and Verifying
Definition of symbols
Table 50. EPROM Programming & Verifying Timing Symbol Definitions
Signals
Conditions
A
Address
H
High
E
Enable: mode set on Port 0
L
Low
Q
Data Out
V
Valid
X
No Longer Valid
Z
Floating
Timings
Table 51. EPROM Programming and Verifying AC timings; VDD= 4.5 to 5.5 V, TA= 0 to 40°C
Symbol
Parameter
Min
Max
Unit
83.5
250
ns
TOSC
XTAL1 Frequency
TAVGL
Address Setup to PROG# low
48×TOSC
TGHAX
Address Hold after PROG# low
48×TOSC
TDVGL
Data Setup to PROG# low
48×TOSC
TGHDX
Data Hold after PROG#
48×TOSC
TEHSH
ENABLE High to VPP
48×TOSC
TSHGL
VPP Setup to PROG# low
10
s
TGHSL
VPP Hold after PROG#
10
s
TSLEL
ENABLE Hold after VPP
0
TGLGH
PROG# Width
90
TAVQV
Address to Data Valid
TAXQX
Address to Data Invalid
TELQV
ENABLE low to Data Valid
TEHQZ
Data Float after ENABLE
Rev. A
– September 21, 1998
110
s
48×TOSC
0
ns
48×TOSC
0
48×TOSC
45
TSC87251G1A
Waveforms
P1= A14:8
P3= A7:0
Address
TAVGL
TGHAX
P2= D7:0
Data
TDVGL
TGHDX
VPP
EA#/VPP
VDD
TSHGL
VSS
TGLGH
TGHSL
ALE/PROG#
TEHSH
TSLEL
Mode= 68h, 69h, 6Bh or 6Ch
P0
Figure 24. EPROM Programming Waveforms
Mode= 28h, 29h or 2Bh
P0
TELQV
P1= A15:8
P3= A7:0
TEHQZ
Address
TAXQX
TAVQV
P2= D7:0
Data
Figure 25. EPROM Verifying Waveforms
11.6. AC Characteristics – External Clock Drive and Logic Level References
Definition of symbols
Table 52. External Clock Timing Symbol Definitions
Signals
C
46
Clock
Conditions
L
Low
H
High
X
No Longer Valid
Rev. A
– September 21, 1998
TSC87251G1A
Timings
Table 53. External Clock AC Timings; VDD= 4.5 to 5.5 V, TA= –40 to +85°C
Symbol
FOSC
Parameter
Min
Max
Unit
24
MHz
Oscillator Frequency
TCHCX
High Time
10
ns
TCLCX
Low Time
10
ns
TCLCH
Rise Time
3
ns
TCHCL
Fall Time
3
ns
Waveforms
TCLCH
VDD – 0.5
VIH1
TCHCX
TCLCX
VIL
0.45 V
TCHCL
TCLCL
Figure 26. External Clock Waveform
INPUTS
VDD – 0.5
0.45 V
OUTPUTS
0.2 VDD + 0.9
VIH min
0.2 VDD – 0.1
VIL max
Note:
During AC testing, all inputs are driven at VDD –0.5 V for a logic 1 and 0.45 V for a logic 0.
Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 27. AC Testing Input/Output Waveforms
VLOAD
VLOAD + 0.1 V
Timing Reference Points
VLOAD – 0.1 V
VOH – 0.1 V
VOL + 0.1 V
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from
the loading VOH /VOL level occurs with IOL /IOH = ±20 mA.
Figure 28. Float Waveforms
Rev. A
– September 21, 1998
47
TSC87251G1A
12. Packages
12.1. List of Packages
PDIL 40
PLCC 44
CQPJ 44
12.2. PDIL 40 – Mechanical Outline
Figure 29: Plastic Dual In Line
Table 54: PDIL Package Size
MM
48
INCH
Min
Max
Min
Max
A
–
5.08
–
.200
A1
0.38
–
.015
–
A2
3.18
4.95
.125
.195
B
0.36
0.56
.014
.022
B1
0.76
1.78
.030
.070
C
0.20
0.38
.008
.015
D
50.29
53.21
1.980
2.095
E
15.24
15.87
.600
.625
E1
12.32
14.73
.485
.580
e
2.54 B.S.C.
.100 B.S.C.
eA
15.24 B.S.C.
.600 B.S.C.
eB
–
17.78
–
.700
L
2.93
3.81
.115
.150
D1
0.13
–
.005
–
Rev. A
– September 21, 1998
TSC87251G1A
12.3. PLCC 44 – Mechanical Outline
Figure 30: Plastic Lead Chip Carrier
Table 55: PLCC Package Size
MM
Min
Max
Min
Max
A
4.20
4.57
.165
.180
A1
2.29
3.04
.090
.120
D
17.40
17.65
.685
.695
D1
16.44
16.66
.647
.656
D2
14.99
16.00
.590
.630
E
17.40
17.65
.685
.695
E1
16.44
16.66
.647
.656
E2
14.99
16.00
.590
.630
e
Rev. A
INCH
1.27 BSC
.050 BSC
G
1.07
1.22
.042
.048
H
1.07
1.42
.042
.056
J
0.51
–
.020
–
K
0.33
0.53
.013
.021
Nd
11
11
Ne
11
11
– September 21, 1998
49
TSC87251G1A
12.4. CQPJ 44 with Window – Mechanical Outline
Figure 31: Ceramic Quad Pack J
Table 56: CQPJ Package size
MM
Min
Max
Min
Max
A
–
4.90
–
.193
C
0.15
0.25
.006
.010
D–E
17.40
17.55
.685
.691
D1 – E1
16.36
16.66
.644
.656
e
50
INCH
1.27 TYP
.050 TYP
f
0.43
0.53
.017
.021
J
0.86
1.12
.034
.044
Q
15.49
16.00
.610
.630
R
0.86 TYP
.034 TYP
N1
11
11
N2
11
11
Rev. A
– September 21, 1998
TSC87251G1A
13. Ordering Information
13.1. TSC87251G1A OTP (Step A)
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TEMIC Part Number
ROM
Description
TSC87251G1A–16CA
16K OTP ROM
16 MHz, Commercial 0° to 70°C, PDIL 40
TSC87251G1A–16CB
16K OTP ROM
16 MHz, Commercial 0° to 70°C, PLCC 44
TSC87251G1A–16IA
16K OTP ROM
16 MHz, Industrial –40° to 85°C, PDIL 40
TSC87251G1A–16IB
16K OTP ROM
16 MHz, Industrial –40° to 85°C, PLCC 44
13.2. TSC87251G1A EPROM – UV Window package (Step A)
High Speed Versions 4.5 to 5.5 V, Industrial
TEMIC Part Number
TSC87251G1A–16IC
ROM
Description
16K EPROM
16 MHz, Industrial –40° to 85°C, window CQPJ 44
13.3. TSC80251G1D ROMless (Step D)
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TEMIC Part Number (2)
ROM
Description
TSC80251G1D–24CA
ROMless
24 MHz, Commercial 0° to 70°C, PDIL 40
TSC80251G1D–24CB
ROMless
24 MHz, Commercial 0° to 70°C, PLCC 44
TSC80251G1D–24CED
ROMless
24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1)
TSC80251G1D–16CA
ROMless
16 MHz, Commercial 0° to 70°C, PDIL 40
TSC80251G1D–16CB
ROMless
16 MHz, Commercial 0° to 70°C, PLCC 44
TSC80251G1D–16CED
ROMless
16 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1)
TSC80251G1D–16IA
ROMless
16 MHz, Industrial –40° to 85°C, PDIL 40
TSC80251G1D–16IB
ROMless
16 MHz, Industrial –40° to 85°C, PLCC 44
Low Voltage Versions 2.7 to 5.5 V, Commercial
TEMIC Part Number (2)
ROM
Description
TSC80251G1D–L12CB
ROMless
12 MHz, Commercial, PLCC 44
TSC80251G1D–L12CED
ROMless
12 MHz, Commercial, VQFP 44, Dry pack (1)
Rev. A
– September 21, 1998
51
TSC87251G1A
13.4. TSC83251G1D Mask ROM (Step D)
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TEMIC Part Number (2)
ROM
Description
TSC251G1Dxxx–24CA
16K MaskROM
24 MHz, Commercial 0° to 70°C, PDIL 40
TSC251G1Dxxx–24CB
16K MaskROM
24 MHz, Commercial 0° to 70°C, PLCC 44
TSC251G1Dxxx–24CED
16K MaskROM
24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1)
TSC251G1Dxxx–16CA
16K MaskROM
16 MHz, Commercial 0° to 70°C, PDIL 40
TSC251G1Dxxx–16CB
16K MaskROM
16 MHz, Commercial 0° to 70°C, PLCC 44
TSC251G1Dxxx–16CED
16K MaskROM
16 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1)
TSC251G1Dxxx–16IA
16K MaskROM
16 MHz, Industrial –40° to 85°C, PDIL 40
TSC251G1Dxxx–16IB
16K MaskROM
16 MHz, Industrial –40° to 85°C, PLCC 44
Low Voltage Versions 2.7 to 5.5 V, Commercial
TEMIC Part Number (2)
ROM
Description
TSC251G1Dxxx–L12CB
16K MaskROM
12 MHz, Commercial 0° to 70°C, PLCC 44
TSC251G1Dxxx–L12CED
16K MaskROM
12 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1)
Notes:
1. Dry Pack mandatory for VQFP package.
2. xxx: means ROM code, is Cxxx in case of encrypted code.
13.5. Options (Please consult TEMIC sales)
G ROM code encryption
G Tape & Real or Dry Pack
G Known good dice
G Ceramic packages
G Extended temperature range: –55°C to +125°C
13.6. Starter Kit
TEMIC Part Number
Description
TSC80251–SK
TSC80251 Starter Kit
13.7. Product Marking
Mask ROM versions
TEMIC
Customer Part number
Temic Part number
 INTEL’97
YYWW . Lot Number
52
ROMless versions
OTP versions
TEMIC
Temic Part number
TEMIC
Temic Part number
 INTEL’97
YYWW . Lot Number
 INTEL’95
YYWW . Lot Number
Rev. A
– September 21, 1998