Preliminary SLD-3091FZ Pb RoHS Compliant & Green Package 30 Watt Discrete LDMOS FET in Ceramic Flanged Package Product Description Sirenza Microdevices’ SLD-3091FZ is a robust 30 Watt high performance LDMOS transistor designed for operation from 10 to 2200MHz. It is an excellent solution for applications requiring high linearity and efficiency at a low cost. The SLD-3091FZ is typically used in power amplifiers, repeaters, and radio amplifier applications. The power transistor is fabricated using Sirenza’s high performance XeMOS IITM process. Functional Schematic Diagram Product Features • • • • • • ESD Protection 30 Watt Output P1dB Single Polarity Supply Voltage High Gain: 18 dB at 915 MHz High Efficiency: 45% at 30W CW XeMOS II LDMOS Integrated ESD Protection, 1B Applications • • • • • Case Flange = Ground Base Station PA driver Repeaters Radio Amplifier Military Communication GSM, CDMA, RFID, Point-to-Point Key RF Specifications Parameter Units Min. Typ. Max. Frequency Symbol Frequency of Operation MHz 10 - 2200 Gain 30 Watt CW, 915 MHz dB Drain Efficiency at 30 Watt CW, 915 MHz % 45 Input Return Loss, 30 Watt Output Power, 915 MHz dB -15 3rd Order IMD at 30 Watt PEP (Two Tone), 915 MHz dBc -28 1dB Compression (P1dB), 915 MHz Watt 35 Thermal Resistance (Junction-to-Case) ºC/W 2.4 Efficiency IRL Linearity RTH Test Conditions VDS = 28.0V, IDQ = 300mA, TFlange = 25ºC 19 T Key DC Parameters Symbol Parameter Unit Typ. 1650 IDS=3mA Volt 3.3 1mA IDS current Volt 65 Ciss Input Capacitance (Gate to Source) VGS=0V, VDS=28V pF 66 Crss Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V pF 1.4 Coss Output Capacitance (Drain to Source) VGS=0V, VDS=28V pF 30 Drain to Source Resistance, VGS=10V, VDS=250mV Ω 0.2 VGSThreshold VDS Breakdown RDSon Forward Transconductance @ 425mA IDS Min mA / V gm Max The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Quality Specifications Parameter Description ESD Rating Human Body Model Rating 1B Pin Description Pin # Function Description 1 Gate Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the recommended maximum input power or voltage. 2 Drain Transistor RF output and drain bias voltage. Typical voltage is 28V. Flange Source, Gnd Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation. Pin Diagram Note 1: Gate voltage must be applied to the device concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly terminated on both input and output. ESD Protection Pin 2 Pin 1 Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in threshold voltage with LDMOS transistors. Note 3: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Case Flange = Ground Absolute Maximum Ratings Parameters Drain Voltage (VDS ) Value Unit 35 V Gate Voltage (VGS) 20 V RF Input Power +36 dBm Load Impedance for Continuous Operation Without Damage 10:1 VSWR Output Device Channel Temperature +200 ºC +270 ºC Lead Temperature During Solder Reflow Operating Temperature Range -20 to +90 ºC Storage Temperature Range -40 to +100 ºC Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Typical Performance Curves in 900 MHz Application Circuit 60 55 20 50 19 45 18 40 17 35 16 30 15 25 Gain Efficiency 13 20 15 12 10 11 5 10 10 20 30 40 40 -30 35 -35 30 -40 25 -45 20 -50 15 -55 10 Gain IM3 IM7 5 5 60 60 -5 -10 Gain (dB), Efficiency (%) Gain Efficiency IRL 25 30 20 -40 -50 10 -25 10 -30 945 0 Frequency (MHz) -10 -30 -20 935 0 30 20 925 Efficiency IM5 IRL -20 -15 303 S. Technology Court Broomfield, CO 80021 20 40 30 915 Gain IM3 IM7 50 Input Return Loss (dB) Gain (dB), Efficiency (%) 50 905 15 2 Tone Gain, Efficiency, Linearity and IRL vs Frequency Vdd=28V, Idq=0.3A, Pout=30W PEP, Delta F=1 MHz 0 895 10 Pout (W PEP) CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=0.3A, Pout=30W 0 885 -65 -70 0 50 Pout (W) 40 -60 Efficiency IM5 0 0 0 -25 885 895 905 915 925 935 -60 945 Frequency (MHz) Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-104668 Rev C IMD(dBc), IRL (dB) 14 Gain (dB), Efficiency (%) 21 45 Efficiency (%) Gain (dB) 22 2 Tone Gain, Efficiency, Linearity vs Pout Vdd=28V, Idq=0.3A, Freq=912 MHz, Delta F=1 MHz IMD (dBc) CW Gain, Efficiency vs Pout Vdd=28V, Idq=0.3A, Freq=912 MHz Preliminary SLD-3091FZ 30 Watt LDMOS FET Typical Performance Curves in 900 MHz Application Circuit over Temperature CW Gain vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=920 MHz Efficiency vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz 22 50 21 40 20 Efficiency (%) Gain (dB) 19 18 17 16 t-=85 t=25 15 30 t-=85 t=25 t=-25 20 10 t=-25 14 13 0 0 10 20 30 40 0 10 Pout (W) 20 30 40 Pout (W) IMD3 vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz 2 tone Efficiency vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz -20 40 -25 35 -30 30 Efficiency (%) IMD3 (dBc) -35 -40 -45 -50 t-=-25 t=25 -55 25 20 t-=-25 15 t=25 10 t=-85 t=-85 -60 5 -65 0 -70 0 5 10 15 20 5 10 15 20 Pout (W avg) Pout (W avg) 303 S. Technology Court Broomfield, CO 80021 0 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Impedance Data Frequency (MHz) Zsource Zload 850 0.9 - j 0.7 2.6 - j 0.5 895 0.8 - j 0.7 2.4 - j 0.4 960 0.7 - j 0.9 2.3 - j 0.1 Impedances Referenced to Wirebond/PCB Interface. Device under test Input Matching Network Z source Output Matching Network Z load Zsource and Zload are the optimal impedances presented to the SLD-3091FZ when operating at 28V, Idq=300mA, Pout=30 W PEP 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET 900 MHz Application Circuit Pin Descriptions - 900 MHz Application Circuit Connector Pin # Function Description J1 Coax RF in J2 Coax RF out J3 1 Gnd DC ground for D package module. Also connected to RF ground. J3 2 Gnd DC ground for D package module. Also connected to RF ground. J3 3 VGS Gate voltage for the SLD3091FZ. Nominally +4Vdc. J3 4 VDS Drain voltage for the SLD3091FZ. Nominally +28Vdc. J3 5 VDS Drain voltage for the SLD3091FZ. Nominally +28Vdc. RF input to test fixture (50 Ohm system) RF output to test fixture (50 Ohm system) Bill of Materials - 900 MHz Application Circuit 303 S. Technology Court Broomfield, CO 80021 Component Description Manufacturer PCB Rogers 4350, er=3.5 Thickness=30 mils Rogers J1, J2 Connector, SMA END 0.037” Johnson J3 MTA Post Header, 5 Pin, Rectangle, Polarized, Surface Mount AMP C2 Capacitor, Lytic 22F, 35V Panasonic C3, C11 Cap, 0.1mF, 100V, 10%, 1206 Johanson C5, C13 Cap, 1000pF, 100V, 10%, 1206 Johanson C7 Capacitor, Lytic 220uF, 50V Panasonic C1,C4,C6, C8,C19 CAP, 68PF,250V,5%,0603 ATC C10,C12, C14 CAP, 12PF,250V,1%,0603 ATC C15,C16 CAP, 10PF,250V,1%,0603 ATC C17 CAP, 7.5 PF, 250V,0603 ATC C18 CAP, 27PF,250V,5%,0603 ATC C2 CAP, 0.22UF, 50V, CERAMIC, X7R, 1206, Kemet C9 CAP, 4.3 PF, 250V, 0603 ATC R2 RES, 560, 1/16W, 5%, 0402 Panasonic R1 RES, 0.0, 1/16W, 5%, 0402 Panasonic Mounting Screws 4-40 X 0.250” Various Phone: (800) SMI-MMIC 6 http://www.sirenza.com EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET 900 MHz Application Circuit Heatsink To receive Gerber files, DXF drawings, and assembly recommendations for the test board with fixture, contact applications support at [email protected]. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 7 http://www.sirenza.com EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Package Outline NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. ADHESIVE FROM LID MAY EXTEND A MAXIMUM OF 0.020" BEYOND EDGE OF LID. 4. LID MAY BE MISALIGNED TO THE BODY OF THE PACKAGE BY A MAXIMUM OF 0.008" IN ANY DIRECTION. DIM INCHES MILLIMETERS MIN MAX MIN MAX A 0.225 0.235 5.72 B 0.004 0.006 0.102 0.152 C D 0.149 0.178 3.78 4.52 0.077 0.087 1.96 2.21 E 0.355 0.365 9.02 9.27 F 0.210 0.220 5.33 5.59 G H 0.795 0.805 20.19 20.45 J 5.97 0.697 0.703 17.70 17.86 DIA 0.130 DIA 3.30 PIN 1. DRAIN PIN 2. GATE PIN 3. SOURCE 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 8 http://www.sirenza.com EDS-104668 Rev C