W E N Applications • Analog and Digital Wireless Systems • 3G, Cellular, PCS • Fixed Wireless, Pager Systems Gain 1 2 3 4 5 6 D Frequency (GHz) FO R Gmax Test C onditions, 25C VDS=7V, IDQ=345mA D evice C haracteristics Test Frequency U nits Min Typ Max ZS=ZS*, ZL=ZL* 0.90 GHz 1.96 GHz 2.14 GHz dB dB dB - 22.9 17.4 16.6 - (unless otherw ise noted) Inserti on Gai n N S 21 Maxi mum Avai lable Gai n [1] M M E Gmax Gai n Power Gai n OIP3 Output Thi rd Order Intercept Poi nt P 1dB Output 1dB C ompressi on Poi nt PCHAN N +33.4 dBm P1dB +46.5 dBm OIP3 +26 dBm IS-95 Channel Power +11.5 dB Gain • +23.7 dBm W-CDMA Channel Power • High Drain Efficiency (>50% at P1dB) 0 Symbol Product Features • High Linearity Performance at 1.96 GHz D E Gain, Gmax (dB) Typical Gain Performance (7V,345mA) 40 35 30 25 20 15 10 5 0 0.05-3 GHz, 2 Watt GaAs HFET IG Output power at 1dB compression is +33.4 dBm when biased for Class AB operation at 7V,345mA at 1.96 GHz. The +46.5 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems. SHF-0589 S Sirenza Microdevices’ SHF-0589 is a high performance AlGaAs/ GaAs Heterostructure FET (HFET) housed in a low-cost surface-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. D E Product Description [2] [2] [2] ZS=ZL= 50 Ohms 0.90 GHz dB 14.1 15.7 17.3 Appli cati on C i rcui t 1.96 GHz dB m 10.3 11.5 12.7 Appli cati on C i rcui t 1.96 GHz dB m 44 46.5 - Appli cati on C i rcui t 1.96 GHz dB m 31.9 33.4 - IS-95 C hannel Power (-45dBc AC PR) Appli cati on C i rcui t 1.96 GHz dB m - 26.2 NF Noi se Fi gure Appli cati on C i rcui t 1.96 GHz dB - 3.7 - IDSS Saturated D rai n C urrent VDS= VDSP, VGS= 0V mA 816 1176 1536 VDS= VDSP, VGS= -0.25V C O [2] Tranconductance Pi nch-Off Voltage R E gm VP [1] BVGS Gate-Source Breakdown Voltage BVGD Gate-D rai n Breakdown Voltage 576 792 1008 V -3.0 -1.9 -1.0 IGS= 4.8mA, drai n open V - -17 -15 IGD= 4.8mA, VGS= -5.0V V - -22 -17 C /W - 23 - V - - 8.0 Thermal Resi stance juncti on-to-lead V DS Operati ng Voltage [3] drai n-source IDQ Operati ng C urrent [3] drai n-source, qui escent PDISS Power D i ssi pati on N O T Rth [1] [1] mS VDS= 2.0V, IDS= 2.4mA [3] o mA - - 480 C - - 2.4 [1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain TJ<140C at TL=85C. VDS * IDQ< 2.4W is recommended for continuous reliable operation. The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved. 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-101242 Rev F SHF-0589 2 Watt HFET Symbol Value Drain Current IDS 640 Forward Gate Current IGSF 4.8 Unit mA mA IG Parameter MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the bias condition should also satisfy the following expression: N Absolute Maximum Ratings IGSR 4.8 mA Drain-to-Source Voltage VDS 9.0 V Gate-to-Source Voltage VGS <-5 or >0 V PDC = IDS * VDS (W) TJ = Junction Temperature (°C) TL = Lead Temperature (pin 4) (°C) RTH = Thermal Resistance (°C/W) RF Input Power PIN 800 mW Operating Lead Temperature TL See Graph D E °C Storage Temperature Range Tstor -40 to +165 °C PDISS See Graph W TJ 165 °C N Channel Temperature E Power Dissipation W where: S Reverse Gate Current PDC < (TJ - TL) / RTH FO Power Derating Curve D E D 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 N Operational (Tj<140C) ABS MAX (Tj<165C) M M E Total Dissipated Power (W) R Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1. -40 -10 20 50 80 110 140 170 Lead Temperature (C) Design Considerations and Trade-offs R E C O 1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-topart precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is recommended to maintain acceptable performance (RF and thermal). 2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB). N O T 3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET’s performance. Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each device to eliminate the effects of pinchoff process variation. 4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage should be increased to 8V to maximize P1dB. For small signal operation OIP3 may be improved by reducing the voltage and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V bias condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipation limit (shown on page 1). 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-101242 Rev F SHF-0589 2 Watt HFET Isolation Gain 1 2 3 4 5 N IG 6 GHz 0.5 2.0 5 GHz 4 GHz 4 GHz 3 GHz 2 GHz 0.0 2 GHz 0.2 S 6 GHz 5 GHz 3 GHz 0.2 1 GHz 0.5 50 MHz 1.0 2.0 5.0 5.0 inf S22 1 GHz 0.2 6 N 0 1.0 D E Gmax S11, S22 vs Frequency W 0 -5 -10 -15 -20 -25 -30 -35 -40 Frequency (GHz) 50 MHz 5.0 E Gain & Isolation 40 35 30 25 20 15 10 5 0 Isolation (dB) Gain, Gmax (dB) De-embedded S-Parameters (ZS=ZL=50 Ohms, VDS=7V, IDS=345mA, 25°C) S11 R 0.5 2.0 FO 1.0 Note: S-parameters are de-embedded to the device leads with Z S=Z L=50Ω. The data represents typical performace of the device. De-embedded s-parameters can be downloaded from our website (www.sirenza.com). D DC-IV Curves D E 1.2 0.8 0.6 M M E 0.4 VGS = -2.0 to 0V, 0.2V steps T=25° C N IDS (A) 1 0.2 0 C O 0 2 4 6 8 10 VDS (V) R E Typical Performance - Engineering Application Circuits -45dBc C h an n el P o w er (dBm) -55dBc C h an n el P o w er (dBm) VDS (V) IDQ (mA) P 1d B (dBm) 900 7 345 32.0 25.7 [4] 23.2 1960 7 345 33.4 26.2 [4] 2140 7 345 32.7 23.7 [5] N O T Freq (MHz ) OIP3[6] (dBm) Gain (dB) S11 (dB) S 22 (dB) NF (dB) [4] 45.0 16.3 -20 -10 3.6 23.2 [4] 46.5 11.5 -15 -12 3.7 20.5 [5] 46.4 11.1 -15 -12 4.4 [4] IS-95 CDMA Channel Power (9 Fwd Channels, 885kHz offset, 30kHz Adj Chan BW) [5] W-CDMA Channel Power (64 DPCH, 5MHz offset, 3.84MHz Adj Chan BW) [6] POUT= +15dBm per tone, 1MHz tone spacing 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-101242 Rev F SHF-0589 2 Watt HFET Caution: ESD sensitive Pin Description 2 Source 3 Drain 4 Source Reel Siz e Devices/Reel SHF-0589 7" 1000 IG Gate Part Number RF Input Part Symbolization The part will be symbolized with the “H5” designator and a dot signifying pin 1 on the top surface of the package. Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. S 1 Description RF Output Same as Pin 2 D E Function Mounting and Thermal Considerations Package Dimensions FO 2 H5 .096 .059 D E .016 .019 .118 1 R .177 .068 4 N E .161 D 1. Multiple solder-filled vias are required directly below the ground tab (pin 4). [CRITICAL] 2. Incorporate a large ground pad area with multiple plated-through vias around pin 4 of the device. [CRITICAL] 3. Use two point board seating to lower the thermal resistance between the PCB and mounting plate. Place machine screws as close to the ground tab (pin 4) as possible. [CRITICAL] 4. Use 2 ounce copper to improve the PCB’s heat spreading capability. [CRITICAL] 5. Thermal transfer paste should be used between the PCB and the mounting plate to improve heat spreading capability. [RECOMMENDED] W It is very important that adequate heat sinking be provided to minimize the device junction temperature. The following items should be implemented to maximize MTTF and RF performance. 3 Pin # N Part Number Ordering Information Appropriate precautions in handling, packaging and testing devices must be observed. .041 .015 M M E N DIMENSIONS ARE IN INCHES Ground Plane Plated Thru Holes (0.020" DIA) N O T R E C O Recommended Mounting Configuration for Optimum RF and Thermal Performance 522 Almanor Ave., Sunnyvale, CA 94085 SHF-0x89 Machine Screws Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-101242 Rev F