TI TPS2034D

 SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
D 33-mΩ (5-V Input) High-Side MOSFET
D
D
D
D
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
Switch
Short-Circuit and Thermal Protection
Overcurrent Logic Output
Operating Range . . . 2.7 V to 5.5 V
Logic-Level Enable Input
Typical Rise Time . . . 6.1 ms
Undervoltage Lockout
Maximum Standby Supply
Current . . . 10 µA
No Drain-Source Back-Gate Diode
Available in 8-pin SOIC and PDIP Packages
Ambient Temperature Range, −40°C to 85°C
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
UL Listed − File No. E169910
GND
IN
IN
EN
1
8
2
7
3
6
4
5
OUT
OUT
OUT
OC
description
The TPS203x family of power distribution switches is intended for applications where heavy capacitive loads
and short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS203x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present.
The TPS203x devices differ only in short-circuit current threshold. The TPS2030 limits at 0.3-A load, the
TPS2031 at 0.9-A load, the TPS2032 at 1.5-A load, the TPS2033 at 2.2-A load, and the TPS2034 at 3-A load
(see Available Options). The TPS203x is available in an 8-pin small-outline integrated-circuit (SOIC) package
and in an 8-pin dual-in-line (DIP) package and operates over a junction temperature range of −40°C to 125°C.
GENERAL SWITCH CATALOG
33 mΩ, single TPS201xA 0.2 A − 2 A
TPS202x
TPS203x
80 mΩ, single TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
80 mΩ, dual
TPS2042
TPS2052
TPS2046
TPS2056
0.2 A − 2 A
0.2 A − 2 A
600 mA
1A
500 mA
500 mA
250 mA
250 mA
260 mΩ
IN1
OUT
IN2
1.3 Ω
500 mA
500 mA
250 mA
250 mA
TPS2100/1
IN1 500 mA
IN2 10 mA
TPS2102/3/4/5
IN1
500 mA
IN2
100 mA
80 mΩ, triple
TPS2043
TPS2053
TPS2047
TPS2057
500 mA
500 mA
250 mA
250 mA
80 mΩ, quad
TPS2044
TPS2054
TPS2048
TPS2058
500 mA
500 mA
250 mA
250 mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999 − 2004 Texas Instruments Incorporated
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TI.COM
1
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
AVAILABLE OPTIONS
TA
−40°C
−40
C to 85
85°C
C
ENABLE
RECOMMENDED
MAXIMUM CONTINUOUS
LOAD CURRENT
(A)
TYPICAL SHORT-CIRCUIT
CURRENT LIMIT AT 25°C
(A)
SMALL OUTLINE
(D)†
PLASTIC DIP
(P)
0.2
0.3
TPS2030D
TPS2030P
0.6
0.9
TPS2031D
TPS2031P
1
1.5
TPS2032D
TPS2032P
1.5
2.2
TPS2033D
TPS2033P
2
3
TPS2034D
TPS2034P
Active high
PACKAGED DEVICES
† The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2030DR)
TPS2030 functional block diagram
Power Switch
†
CS
IN
OUT
Charge
Pump
EN
Current
Limit
Driver
OC
UVLO
Thermal
Sense
GND
†Current Sense
Terminal Functions
TERMINAL
NO.
D OR P
I/O
EN
4
I
Enable input. Logic high turns on power switch.
GND
1
I
Ground
2, 3
I
Input voltage
5
O
Overcurrent. Logic output active low
6, 7, 8
O
Power-switch output
NAME
IN
OC
OUT
2
DESCRIPTION
TI.COM
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
enable (EN)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic low is present on EN . A logic high input on EN restores bias
to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
overcurrent ( OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
TI.COM
3
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(IN) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Output voltage range, VO(OUT) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VI(IN) + 0.3 V
Input voltage range,VI(EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Continuous output current, IO(OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . 750 V
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
P
1175 mW
9.4 mW/°C
752 mW
611 mW
PACKAGE
recommended operating conditions
Input voltage
Continuous output current, IO
VI(IN)
VI(EN)
MAX
2.7
5.5
V
V
0
5.5
TPS2030
0
0.2
TPS2031
0
0.6
TPS2032
0
1
TPS2033
0
1.5
TPS2034
0
2
−40
125
Operating virtual junction temperature, TJ
4
MIN
TI.COM
UNIT
A
°C
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 5 V (unless otherwise noted)
power switch
TEST CONDITIONS†
PARAMETER
rDS(on)
tr
tf
Static drain-source on-state resistance
Rise time, output
Fall time, output
TYP
MAX
VI(IN) = 5 V,
TJ = 25°C,
IO = 1.8 A
MIN
33
36
VI(IN) = 5 V,
TJ = 85°C,
IO = 1.8 A
38
46
VI(IN) = 5 V,
TJ = 125°C,
IO = 1.8 A
44
50
VI(IN) = 3.3 V,
TJ = 25°C,
IO = 1.8 A
37
41
VI(IN) = 3.3 V,
TJ = 85°C,
IO = 1.8 A
43
52
VI(IN) = 3.3 V,
TJ = 125°C,
IO = 1.8 A
51
61
VI(IN) = 5 V,
TJ = 25°C,
IO = 0.18 A
30
34
VI(IN) = 5 V,
TJ = 85°C,
IO = 0.18 A
35
41
VI(IN) = 5 V,
TJ = 125°C,
IO = 0.18 A
39
47
VI(IN) = 3.3 V,
TJ = 25°C,
IO = 0.18 A
33
37
VI(IN) = 3.3 V,
TJ = 85°C,
IO = 0.18 A
39
46
VI(IN) = 3.3 V,
TJ = 125°C,
IO = 0.18 A
44
56
VI(IN) = 5.5 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω
6.1
VI(IN) = 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω
8.6
VI(IN) = 5.5 V,
CL = 1 µF,
VI(IN) = 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω
TJ = 25°C,
RL = 10 Ω
UNIT
mΩ
ms
3.4
ms
3
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input ( EN)
PARAMETER
VIH
VIL
TEST CONDITIONS
2.7 V ≤ VI(IN) ≤ 5.5 V
High-level input voltage
Low-level input voltage
TYP
MAX
2
0.8
2.7 V ≤ VI(IN) ≤ 4.5 V
0.5
II
Input current
EN = 0 V or EN = VI(IN)
Turnon time
CL = 100 µF, RL = 10 Ω
CL = 100 µF, RL = 10 Ω
UNIT
V
4.5 V ≤ VI(IN) ≤ 5.5 V
ton
toff
Turnoff time
MIN
−0.5
0.5
20
40
V
µA
ms
current limit
PARAMETER
IOS
Short-circuit output current
TEST CONDITIONS†
TJ = 25°C, VI = 5.5 V,
OUT connected to GND,
Device enable into short circuit
MIN
TYP
MAX
TPS2030
0.22
0.3
0.4
TPS2031
0.66
0.9
1.1
TPS2032
1.1
1.5
1.8
TPS2033
1.65
2.2
2.7
UNIT
A
TPS2034
2.2
3
3.8
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TI.COM
5
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 5 V (unless otherwise noted) (continued)
supply current
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
No Load on OUT
EN = 0
TJ = 25°C
−40°C ≤ TJ ≤ 125°C
0.3
Supply current, low-level output
1
75
No Load on OUT
EN = VI(IN)
TJ = 25°C
−40°C ≤ TJ ≤ 125°C
58
Supply current, high-level output
75
100
Leakage current
OUT connected to ground
EN = 0
−40°C ≤ TJ ≤ 125°C
10
10
UNIT
µA
A
A
µA
µA
undervoltage lockout
PARAMETER
TEST CONDITIONS
Low-level input voltage
MIN
TYP
2
Hysteresis
TJ = 25°C
MAX
2.5
100
UNIT
V
mV
overcurrent (OC)
PARAMETER
TEST CONDITIONS
Output low voltage
Off-state current†
IO = 10 mA,
VOL(OC)
VO = 5 V, VO = 3.3 V
† Specified by design, not production tested.
6
TI.COM
MIN
TYP
MAX
UNIT
0.4
V
1
µA
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
OUT
RL
tf
tr
CL
VO(OUT)
90%
10%
90%
10%
TEST CIRCUIT
50%
VI(EN)
50%
toff
ton
90%
VO(OUT)
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
Table of Timing Diagrams
FIGURE
Turnon Delay and Rise TIme
2
Turnoff Delay and Fall Time
3
Turnon Delay and Rise TIme with 1-µF Load
4
Turnoff Delay and Rise TIme with 1-µF Load
5
Device Enabled Into Short
6
TPS2030, TPS2031, TPS2032, TPS2033, and TPS2034, Ramped Load on Enabled Device
7, 8, 9, 10,
11
TPS2034, Inrush Current
12
7.9-Ω Load Connected to an Enabled TPS2030 Device
13
3.7-Ω Load Connected to an Enabled TPS2030 Device
14
3.7-Ω Load Connected to an Enabled TPS2031 Device
15
2.6-Ω Load Connected to an Enabled TPS2031 Device
16
2.6-Ω Load Connected to an Enabled TPS2032 Device
17
1.2-Ω Load Connected to an Enabled TPS2032 Device
18
1.2-Ω Load Connected to an Enabled TPS2033 Device
19
0.9-Ω Load Connected to an Enabled TPS2033 Device
20
0.9-Ω Load Connected to an Enabled TPS2034 Device
21
0.5-Ω Load Connected to an Enabled TPS2034 Device
22
TI.COM
7
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VI(EN) (5 V/div)
VI(EN) (5 V/div)
VI(EN)
VI(EN)
VI(IN) = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VO(OUT) (2 V/div)
VIN = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT)
0
2
4
6
8
10
12
14
16
18
VO(OUT)
20
2
0
4
6
8
12
14
16
18
20
t − Time − ms
t − Time − ms
Figure 3. Turnoff Delay and Fall Time
Figure 2. Turnon Delay and Rise Time
VI(EN) (5 V/div)
VI(EN) (5 V/div)
VI(EN)
VI(EN)
VO(OUT) (2 V/div)
VO(OUT) (2 V/div)
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT)
0
2
4
6
8
10
12
14
16
18
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT)
20
0
2
4
6
8
10
12
14
16
18
t − Time − ms
t − Time − ms
Figure 5. Turnoff Delay and Fall Time
With 1-µF Load
Figure 4. Turnon Delay and Rise Time
With 1-µF Load
8
10
TI.COM
20
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VO(OC) (5 V/div)
VI(EN)
VI(EN) (5 V/div)
VO(OC)
VI(IN) = 5 V
TA = 25°C
VI(IN) = 5 V
TA = 25°C
TPS2034
TPS2033
IO(OUT) (500 mA/div)
TPS2032
TPS2031
TPS2030
IO(OUT)
IO(OUT)
IO(OUT) (1 A/div)
0
1
2
3
4
5
6
7
8
9
0
10
20
40
60
80 100 120 140 160 180 200
t − Time − ms
t − Time − ms
Figure 7. TPS2030, Ramped Load on
Enabled Device
Figure 6. Device Enabled Into Short
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
TA = 25°C
VI(IN) = 5 V
TA = 25°C
IO(OUT) (1 A/div)
IO(OUT) (1 A/div)
IO(OUT)
IO(OUT)
0
20
40
60
80 100 120 140 160 180 200
0
t − Time − ms
20
40
60
80 100 120 140 160 180 200
t − Time − ms
Figure 8. TPS2031, Ramped Load on Enabled
Device
Figure 9. TPS2032, Ramped Load on
Enabled Device
TI.COM
9
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
TA = 25°C
VI(IN) = 5 V
TA = 25°C
IO(OUT) (1 A/div)
IO(OUT) (1 A/div)
IO(OUT)
IO(OUT)
0
20
40
60
0
80 100 120 140 160 180 200
20
40
60
80 100 120 140 160 180 200
t − Time − ms
t − Time − ms
Figure 11. TPS2034, Ramped Load on Enabled
Device
Figure 10. TPS2033, Ramped Load on
Enabled Device
VI(EN)
VO(OC) (5 V/div)
VI(EN) (5 V/div)
VO(OC)
IO(OUT) (200 mA/div)
470 µF
150 µF
II(IN) (500 mA/div)
II(IN)
RL = 10 Ω
TA = 25°C
47 µF
0
1
2
3
4
5
6
7
8
9
10
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
t − Time − ms
Figure 12. TPS2034, Inrush Current
10
VI(IN) = 5 V
RL = 7.9 Ω
TA = 25°C
IO(OUT)
Figure 13. 7.9-Ω Load Connected to an Enabled
TPS2030 Device
TI.COM
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
IO(OUT) (500 mA/div)
IO(OUT) (1 A/div)
IO(OUT)
IO(OUT)
0
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
Figure 15. 3.7-Ω Load Connected to an Enabled
TPS2031 Device
Figure 14. 3.7-Ω Load Connected to an Enabled
TPS2030 Device
VO(OC)
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
IO(OUT) (1 A/div)
IO(OUT) (1 A/div)
IO(OUT)
IO(OUT)
0
0
50 100 150 200 250 300 350 400 450 500
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
t − Time − µs
Figure 17. 2.6-Ω Load Connected to an Enabled
TPS2032 Device
Figure 16. 2.6-Ω Load Connected to an Enabled
TPS2031 Device
TI.COM
11
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
IO(OUT) (1 A/div)
IO(OUT) (2 A/div)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
IO(OUT)
IO(OUT)
0
100 200 300 400 500 600 700 800 900 1000
0
t − Time − µs
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
Figure 19. 1.2-Ω Load Connected to an Enabled
TPS2033 Device
Figure 18. 1.2-Ω Load Connected to an Enabled
TPS2032 Device
VO(OC) (5 V/div)
VO(OC) (5 V/div)
VO(OC)
VO(OC)
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
IO(OUT) (2 A/div)
IO(OUT) (5 A/div)
IO(OUT)
IO(OUT)
0
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
Figure 20. 0.9-Ω Load Connected to an Enabled
TPS2033 Device
12
0
TI.COM
Figure 21. 0.9-Ω Load Connected to an Enabled
TPS2034 Device
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VO(OC) (5 V/div)
VO(OC)
VI(IN) = 5 V
RL = 0.5 Ω
TA = 25°C
IO(OUT) (5 A/div)
IO(OUT)
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 22. 0.5-Ω Load Connected to an Enabled
TPS2034 Device
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
td(on)
td(off)
Turnon delay time
vs Output voltage
23
Turnoff delay time
vs Input voltage
24
tr
tf
Rise time
vs Load current
25
Fall time
vs Load current
26
Supply current (enabled)
vs Junction temperature
27
Supply current (disabled)
vs Junction temperature
28
Supply current (enabled)
vs Input voltage
29
Supply current (disabled)
vs Input voltage
30
vs Input voltage
31
vs Junction temperature
32
vs Input voltage
33
vs Junction temperature
34
IOS
rDS(on)
VI
Short-circuit current limit
Static drain-source on-state resistance
Input voltage
TI.COM
vs Input voltage
35
vs Junction temperature
36
Undervoltage lockout
37
13
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
TURNON DELAY TIME
vs
OUTPUT VOLTAGE
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
18
TA = 25°C
CL = 1 µF
7
t d(off) − Turn-off Delay Time − ms
t d(on) − Turn-on Delay Time − ms
7.5
6.5
6
5.5
5
4.5
TA = 25°C
CL = 1 µF
17.5
17
16.5
4
3.5
2.5
3
3.5
4
4.5
5
5.5
16
2.5
6
VI − Input Voltage − V
3
5
3.5
4
4.5
VI − Input Voltage − V
Figure 23
Figure 24
RISE TIME
vs
LOAD CURRENT
FALL TIME
vs
LOAD CURRENT
6.5
5.5
6
3.5
TA = 25°C
CL = 1 µF
TA = 25°C
CL = 1 µF
t f − Fall Time − ms
t r − Rise Time − ms
3.25
6
5.5
3
2.75
5
0
0.5
1
1.5
2
IL − Load Current − A
Figure 25
14
2.5
0
0.5
1
1.5
IL − Load Current − A
Figure 26
TI.COM
2
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (ENABLED)
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT (DISABLED)
vs
JUNCTION TEMPERATURE
5
VI(IN) = 5.5 V
Supply Current (Disabled) − µ A
Supply Current (Enabled) − µ A
75
65
VI(IN) = 5 V
55
VI(IN) = 4 V
45
VI(IN) = 3.3 V
VI(IN) = 5.5 V
VI(IN) = 5 V
4
3
2
1
VI(IN) = 4 V
VI(IN) = 3.3 V
0
VI(IN) = 2.7 V
VI(IN) = 2.7 V
35
−50 −25
0
25
75
50
100
125
−1
150
−50 −25
TJ − Junction Temperature − °C
0
25
75
50
100
125
150
TJ − Junction Temperature − °C
Figure 27
Figure 28
SUPPLY CURRENT (ENABLED)
vs
INPUT VOLTAGE
SUPPLY CURRENT (DISABLED)
vs
INPUT VOLTAGE
75
5
TJ = 85°C
Supply Current (Disabled) − µ A
Supply Current (Enabled) − µ A
TJ = 125°C
65
55
45
TJ = 25°C
TJ = 125°C
4
3
TJ = 85°C
2
1
TJ = 25°C
0
TJ = 0°C
TJ = 0°C
TJ = −40°C
TJ = −40°C
35
2.5
3
3.5
4
4.5
5
5.5
−1
6
2.5
VI − Input Voltage − V
3
3.5
4
4.5
5
5.5
6
VI − Input Voltage − V
Figure 29
Figure 30
TI.COM
15
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
SHORT-CIRCUIT CURRENT LIMIT
vs
INPUT VOLTAGE
SHORT-CIRCUIT CURRENT LIMIT
vs
JUNCTION TEMPERATURE
3.5
3.5
TPS2034
TPS2034
I OS − Short-Circuit Current Limit − A
I OS − Short-Circuit Current Limit − A
TA = 25°C
3
2.5
TPS2033
2
TPS2032
1.5
1
TPS2031
0.5
TPS2030
3
4
5
2.5
TPS2033
2
6
TPS2032
1.5
TPS2031
1
TPS2030
0.5
0
−50
0
2
3
−25
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
60
IO = 0.18 A
50
TJ = 125°C
40
TJ = 25°C
30
TJ = −40°C
3
4.5
5
3.5
4
VI − Input Voltage − V
5.5
6
75
100
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
60
IO = 0.18 A
50
40
VI = 2.7 V
VI = 3.3 V
30
20
−50 −25
VI = 5.5 V
0
25
50
75
100
TJ − Junction Temperature − °C
Figure 33
16
50
Figure 32
r DS(on) − Static Drain-Source On-State Resistance − m Ω
r DS(on) − Static Drain-Source On-State Resistance − m Ω
Figure 31
20
2.5
25
0
TJ − Junction Temperature − °C
VI − Input Voltage − V
Figure 34
TI.COM
125
150
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
60
IO = 1.8 A
50
TJ = 125°C
40
TJ = 25°C
TJ = −40°C
30
20
3
3.5
4
4.5
5
5.5
6
r DS(on) − Static Drain-Source On-State Resistance − m Ω
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
60
IO = 1.8 A
50
VI = 3.3 V
VI = 4 V
VI = 5.5 V
40
30
20
−50 −25
0
25
50
75
100
125
150
TJ − Junction Temperature − °C
VI − Input Voltage − V
Figure 35
Figure 36
UNDERVOLTAGE LOCKOUT
2.5
2.4
VI − Input Voltage − V
r DS(on) − Static Drain-Source On-State Resistance − m Ω
TYPICAL CHARACTERISTICS
Start Threshold
2.3
2.2
Stop Threshold
2.1
2
−50
0
50
100
150
TJ − Temperature − °C
Figure 37
TI.COM
17
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
APPLICATION INFORMATION
TPS2034
2,3
Power Supply
2.7 V to 5.5 V
10 kΩ
IN
0.1 µF
OUT
6,7,8
Load
0.1 µF
5
4
22 µF
OC
EN
GND
1
Figure 38. Typical Application
power supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load
is heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to
short-circuit transients.
overcurrent
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault
is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS203x senses the short and
immediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 13−22).
After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figures 7−11). The TPS203x is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connected
to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
18
TI.COM
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
APPLICATION INFORMATION
TPS203x
TPS203x
GND
OUT
IN
OUT
IN
OUT
EN
V+
Rpullup
OUT
IN
OUT
IN
OUT
EN
OC
V+
GND
Rpullup
Rfilter
OC
Cfilter
Figure 39. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
temperature of interest and read rDS(on) from Figures 33−36. Next, calculate the power dissipation using:
P
D
+r
DS(on)
I2
Finally, calculate the junction temperature:
T +P
J
D
R
qJA
)T
A
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS203x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal
to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The
protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal
sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch
continues to cycle in this manner until the load fault or input power is removed.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce
EMI and voltage overshoots.
TI.COM
19
SLVS190B − DECEMBER 1998 − REVISED MARCH 2004
APPLICATION INFORMATION
generic hot-plug applications (see Figure 40)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Because of the controlled rise times and fall times of the TPS203x series, these devices can
be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS203x also ensures the switch will be off after the card has been removed, and the switch will be off
during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion
of the card or module.
PC Board
TPS2034
Power
Supply
2.7 V to 5.5 V
1000 µF
Optimum
0.1 µF
GND
OUT
IN
OUT
IN
OUT
EN
Block of
Circuitry
OC
Overcurrent Response
Figure 40. Typical Hot-Plug Implementation
By placing the TPS203x between the VCC input and the rest of the circuitry, the input power will reach this device
first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at
the output of the device. This implementation controls system surge currents and provides a hot-plugging
mechanism for any device.
20
TI.COM
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS2030D
ACTIVE
SOIC
D
8
75
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2030DR
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2030P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
TPS2030PE4
ACTIVE
PDIP
P
8
50
None
Call TI
TPS2031D
ACTIVE
SOIC
D
8
75
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2031DR
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2031P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
TPS2031PE4
ACTIVE
PDIP
P
8
50
None
Call TI
TPS2032D
ACTIVE
SOIC
D
8
75
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2032DR
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2032P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
TPS2032PE4
ACTIVE
PDIP
P
8
50
None
Call TI
TPS2033D
ACTIVE
SOIC
D
8
75
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2033DR
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2033P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
TPS2033PE4
ACTIVE
PDIP
P
8
50
None
Call TI
TPS2034D
ACTIVE
SOIC
D
8
75
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2034DR
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS2034DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS2034P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
TPS2034PE4
ACTIVE
PDIP
P
8
50
None
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
Call TI
Call TI
Call TI
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2005
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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