TI TPS2014D

TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
D
D
D
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
95-mΩ Maximum (5-V Input) High-Side
MOSFET Switch
Short-Circuit Protection and Thermal
Protection
Logic Overcurrent Output
4-V to 7-V Operating Range
Enable Input Compatible With 3-V and 5-V
Logic
Controlled Rise and Fall Times Limit
Current Surges and Minimize EMI
Undervoltage Lockout Ensures That Switch
is Off at Start-Up
10-µA Maximum Standby Current
Available in Space-Saving 8-Pin SOIC and
8-Pin PDIP
0°C to 125°C Operating Junction
Temperature Range
12-kV Output, 6-kV Input ElectrostaticDischarge Protection
GND
IN
IN
EN
1
8
2
7
3
6
4
5
OUT
OUT
OUT
OC
description
The TPS2014 and TPS2015 power distribution switches are intended for applications where heavy capacitive
loads and short circuits are likely to be encountered. The high-side switch is a 95-mΩ n-channel MOSFET. The
switch is controlled by a logic enable that is compatible with 3-V and 5-V logic. Gate drive is provided by an
internal charge pump designed to control the power switch rise times and fall times to minimize current surges
during switching. The charge pump requires no external components and allows operation from supplies as low
as 4 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS20xx limits the output
current to a safe level by switching into a constant-current mode, and the overcurrent logic output is set to low.
Continuous heavy overloads and short circuits will increase the power dissipation in the switch and cause the
junction temperature to rise. A thermal protection circuit is implemented, which shuts the switch off to prevent
damage when the junction temperature exceeds its thermal limit. An undervoltage lockout is provided to ensure
the switch is in the off state at start-up.
The TPS2014 and TPS2015 differ only in short-circuit current limits. The TPS2014 is designed to limit at 1.2 A
load and the TPS2015 limits at 2 A (see the available options table). The TPS20xx is available in 8-pin
small-outline integrated circuit (SOIC) and 8-pin PDIP packages, and operates over a junction temperature
range of 0°C to 125°C.
AVAILABLE OPTIONS
TA
0°C TO 85°C
RECOMMENDED MAXIMUM
CONTINUOUS LOAD CURRENT
TYPICAL SHORT-CIRCUIT
SHORT CIRCUIT
CURRENT LIMIT AT 25°C
0.6 A
1A
PACKAGED DEVICES
CHIP FORM
(Y)
SOIC
(D)†
PDIP
(P)
1.2 A
TPS2014D
TPS2014P
TPS2014Y
2A
TPS2015D
TPS2015P
TPS2015Y
† The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2014DR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
functional block diagram
Power Switch
†
CS
IN
OUT
Charge
Pump
OC
EN
Current
Limit
Driver
UVLO
Thermal
Sense
GND
†Current Sense
TPS20xxY chip information
This chip, when properly assembled, displays characteristics similar to those of the TPS20xx. Ultrasonic
bonding may be used on the doped aluminium bonding pads. The chip may be mounted with conductive epoxy
or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(1)
(8)
GND
IN
(1)
(8)
(2)
(7)
(3)
IN
(2)
EN
OUT
OUT
TPS20xxY
(4)
(6)
(5)
OUT
OC
91
(3)
(7)
CHIP THICKNESS: 15 TYPICAl
BONDING PADS: 4 × 4 MINIMUM
(6)
(5)
(4)
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
74
2
TJ max = 150°C
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
Terminal Functions
TERMINAL
NAME
EN
GND
NO.
I/O
DESCRIPTION
4
I
Enable input. Logic low at EN turns the power switch on.
1
I
Ground
IN
2, 3
I
Input voltage
OC
5
O
OC is asserted active low during a fault condition.
6–8
O
Power switch output
OUT
detailed description
power switch
The power switch is an n-channel MOSFET with a maximum on-state resistance of 95 mΩ (VI(IN) = 5 V),
configured as a high-side switch.
charge pump
An internal 100-kHz charge pump supplies power to the driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 4 V and
requires very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range instead of the
microsecond or nanosecond range for a standard FET.
enable (EN)
A logic high on EN turns off the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current to less than 10 µA. A logic zero input restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OC)
OC is an open-drain logic output that is asserted (active low) when an overload or short circuit is encountered.
The output remains asserted until the overload or short-circuit condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET provides a much more efficient way to
measure current than conventional resistance methods. When an overload or short circuit is encountered, the
current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives
the power FET into its linear region, which switches the output into a constant current mode and simply holds
the current constant while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately to 180°C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
An internal voltage sense monitors the input voltage. When the input voltage is below 3.2 V nominal, a control
signal turns off the power switch.
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range, VO (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VI(IN) + 0.3 V
Input voltage range, VI at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
P
1175 mW
9.4 mW/°C
752 mW
235 mW
D
725 mW
5.8 mW/°C
464 mW
145 mW
recommended operating conditions
MIN
MAX
Input voltage, VI
4
5.5
V
Input voltage, VI at EN
0
5.5
V
TPS2014
0
0.6
TPS2015
0
1
0
125
Continuous output current,
current IO
Operating virtual junction temperature, TJ
UNIT
A
°C
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 0 V (unless otherwise noted)
power switch
TEST CONDITIONS†
PARAMETER
ron
On state resistance
On-state
TYP
MAX
VI = 5.5 V,
VI = 5 V,
TJ = 25°C
TJ = 25°C
MIN
75
95
80
95
VI = 4.5V,
VI = 4 V,
TJ = 25°C
TJ = 25°C
90
110
96
110
EN = VI,
0.001
1
EN = VI,
TJ = 25°C
0°C ≤ TJ ≤ 125°C
Ilk
lkg
Leakage current
current, output
tr
Rise time
time, output
VI = 5.5 V,
VI = 4 V,
TJ = 25°C
TJ = 25°C
CL = 1 µF
4
CL = 1 µF
3.8
tf
Fall time
time, output
VI = 5.5 V,
VI = 4 V,
TJ = 25°C
TJ = 25°C
CL = 1 µF
3.9
CL = 1 µF
3.5
10
UNIT
mΩ
µA
ms
ms
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
4
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 0 V (unless otherwise noted) (continued)
enable input (EN)
PARAMETER
TEST CONDITIONS
MIN
MAX
VIH
VIL
High-level input voltage
4 V ≤ VI ≤ 5.5 V
Low-level input voltage
4 V ≤ VI ≤ 5.5 V
II
tPLH
Input current
EN = 0 V or EN = VI
Propagation (delay) time, low to high output
CL = 1 µF
20
tPHL
Propagation (delay) time, high to low output
CL = 1 µF
40
2
–0.5
UNIT
V
0.8
V
0.5
µA
ms
current limit
TEST CONDITIONS†
PARAMETER
IOS
Short circuit output current
Short-circuit
25°C VI = 5.5
55V
TJ = 25°C,
MIN
TYP
MAX
TPS2014
0.66
1.2
1.8
TPS2015
1.1
2
3
UNIT
A
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
supply current
PARAMETER
TEST CONDITIONS
IDDL
level output
Supply current
current, low
low-level
EN = VI
TJ = 25°C
0°C ≤ TJ ≤ 125°C
IDDH
Supply current,
current high-level
high level output
EN = 0 V
TJ = 25°C
0°C ≤ TJ ≤ 125°C
MIN
TYP
MAX
0.015
10
73
10
100
100
UNIT
µA
µA
undervoltage lockout
PARAMETER
VIL
Low-level input voltage
MIN
TYP
MAX
2
3.2
4
MIN
TYP
MAX
UNIT
V
OC
PARAMETER
TEST CONDITIONS
IOS
Short-circuit output current
0°C ≤ TJ ≤ 125°C
5
VOL
Low-level output voltage
0°C ≤ TJ ≤ 125°C
0.3
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UNIT
mA
5
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 0 V (unless otherwise noted)
power switch
TEST CONDITIONS†
PARAMETER
ron
On state resistance
On-state
TPS2014Y, TPS2015Y
MIN
TYP
VI = 5.5 V,
VI = 5 V,
TJ = 25°C
TJ = 25°C
75
VI = 4.5V,
VI = 4 V,
TJ = 25°C
TJ = 25°C
90
EN = VI,
EN = VI,
TJ = 25°C
0°C ≤ TJ ≤ 125°C
MAX
80
UNIT
mΩ
96
0.001
Ilk
lkg
Leakage current
current, output
tr
Rise time
time, output
VI = 5.5 V,
VI = 4 V,
TJ = 25°C
TJ = 25°C
CL = 1 µF
4
CL = 1 µF
3.8
tf
Fall time
time, output
VI = 5.5 V,
VI = 4 V,
TJ = 25°C
TJ = 25°C
CL = 1 µF
3.9
CL = 1 µF
3.5
µA
10
ms
ms
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input (EN)
PARAMETER
TEST CONDITIONS
TPS2014Y, TPS2015Y
MIN
TYP
MAX
UNIT
VIH
VIL
High-level input voltage
4 V ≤ VI ≤ 5.5 V
2
V
Low-level input voltage
4 V ≤ VI ≤ 5.5 V
0.8
V
II
tPLH
Input current
EN = 0 V or EN = VI
0.5
µA
Propagation (delay) time, low to high output
CL = 1 µF
20
tPHL
Propagation (delay) time, high to low output
CL = 1 µF
40
ms
current limit
TEST CONDITIONS†
PARAMETER
IOS
Short circuit output current
Short-circuit
TJ = 25°C,
25°C VI = 5.5
55V
TPS2014Y, TPS2015Y
MIN
TYP
TPS2014
1.2
TPS2015
2
MAX
UNIT
A
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
supply current
PARAMETER
TEST CONDITIONS
IDDL
Supply current
current, low
low-level
level output
EN = VI
TJ = 25°C
0°C ≤ TJ ≤ 125°C
IDDH
Supply current,
current high-level
high level output
EN = 0 V
TJ = 25°C
0°C ≤ TJ ≤ 125°C
TPS2014Y, TPS2015Y
MIN
TYP
MAX
0.015
UNIT
µA
10
73
µA
100
undervoltage lockout
TPS2014Y, TPS2015Y
PARAMETER
VIL
6
MIN
Low-level input voltage
TYP
3.2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
V
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, EN = 0 V (unless otherwise noted) (continued)
OC
PARAMETER
TPS2014Y, TPS2015Y
TEST CONDITIONS
MIN
TYP
IOS
Short-circuit output current
0°C ≤ TJ ≤ 125°C
5
VOL
Low-level output voltage
0°C ≤ TJ ≤ 125°C
0.3
MAX
UNIT
mA
PARAMETER MEASUREMENT INFORMATION
Table of Timing Diagrams
FIGURE
1
Propagation Delay and Fall Time With 1-µF Load, VI(IN) = 5 V
2
TPS2014 Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5 V
3
TPS2015 Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5 V
4
TPS2014 Threshold Current, VI(IN) = 5 V
5
TPS2015 Threshold Current, VI(IN) = 5 V
6
TPS2014 (Enabled) into Short Circuit, VI(IN) = 5 V
7
TPS2015 (Enabled) into Short Circuit, VI(IN) = 5 V
8
6
4
2
0
6
4
2
0
0
1
2
3
4
5
6
7
8
9
–2
10
VO – Output Voltage – V
Enable Voltage – V
Propagation Delay and Rise Time With 1-µF Load, VI(IN) = 5 V
t – Time – ms
Figure 1. Propagation Delay and Rise Time With 1-µF Load, VI(IN) = 5 V
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
6
4
2
0
6
4
2
0
0
5
10
15
20
25
30
35
40
45
–2
50
VO – Output Voltage – V
Enable Voltage – V
PARAMETER MEASUREMENT INFORMATION
t – Time – ms
10
5
0
–5
2
–10
1
0
–1
0
2
4
6
8
10
12
14
16
18
–2
20
I O – Output Current – A
VO – Output Voltage – V
Figure 2. Propagation Delay and Fall Time With 1-µF Load, VI(IN) = 5 V
t – Time – ms
Figure 3. TPS2014 Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5 V
8
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
10
5
0
–5
3
–10
2
1
0
–1
0
2
4
6
8
10
12
14
16
18
I O – Output Current – A
VO – Output Voltage – V
PARAMETER MEASUREMENT INFORMATION
–2
20
t – Time – ms
6
4
2
0
4
–2
3
2
1
0
0
2
4
6
8
10
12
14
16
18
I O – Output Current – A
VO – Output Voltage – V
Figure 4. TPS2015 Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5 V
–1
20
t – Time – ms
Figure 5. TPS2014 Threshold Current, VI(IN) = 5 V
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
10
5
0
4
–5
4
3
2
1
0
0
20
40
60
I O – Output Current – A
VO – Output Voltage – V
PARAMETER MEASUREMENT INFORMATION
–1
80 100 120 140 160 180 200
t – Time – ms
Figure 6. TPS2015 Threshold Current, VI(IN) = 5 V
6
5
I O – Output Current – A
4
3
2
1
0
–1
–2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t – Time – ms
Figure 7. TPS2014 (Enabled) into Short Circuit, VI(IN) = 5 V
10
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
12
I O – Output Current – A
10
8
6
4
2
0
–2
–4
0
0.5
1
1.5
2.5
2
3
3.5
4
4.5
5
t – Time – ms
Figure 8. TPS2015 (Enabled) into Short Circuit, VI(IN) = 5 V
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Turn-On Delay Time vs Input Voltage
9
Turn-Off Delay Time vs Input Voltage
10
Rise Time vs Output Current
11
Fall Time vs Output Current
12
Supply Current, Output Enabled vs Junction Temperature
13
Supply Current, Output Enabled vs Junction Temperature
14
Supply Current, Output Enabled vs Input Voltage
15
Supply Current, Output Enabled vs Input Voltage
16
On-State Resistance vs Junction Temperature
17
On-State Resistance vs Input Voltage
18
Input Voltage to Output Voltage vs Input Voltage
19
Short-Circuit Output Current vs Input Voltage
20
Threshold Trip Current vs Input Voltage
21
Short-Circuit Output Current vs Junction Temperature
22
UVLO Trip Voltage vs Junction Temperature
23
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
TYPICAL CHARACTERISTICS
TURN-OFF DELAY TIME
vs
INPUT VOLTAGE
TURN-ON DELAY TIME
vs
INPUT VOLTAGE
5
20
TJ = 25°C
CL = 1 µF
TJ = 25°C
CL = 1 µF
18.4
t – Turn-Off Delay Time – ms
t – Turn-On Delay Time – ms
4.75
4.5
4.25
4
16.8
15.2
13.6
3.75
12
3.4
4
4.25
4.5
4.75
5
5.25
4
5.5
4.25
4.75
5
5.25
5.5
1.2
1.4
Figure 10
Figure 9
FALL TIME
vs
OUTPUT CURRENT
RISE TIME
vs
OUTPUT CURRENT
3.2
2.7
2.6
4.5
VI – Input Voltage – V
VI – Input Voltage – V
TJ = 25°C
CL = 1 µF
VI = 5 V
TJ = 25°C
CL = 1 µF
VI = 5 V
3
tf – Fall Time – ms
tr – Rise Time – ms
2.5
2.4
2.3
2.8
2.6
2.2
2.4
2.1
2
0.2
0.4
0.6
0.8
1
1.2
1.4
2.2
0.2
0.4
0.8
Figure 12
Figure 11
POST OFFICE BOX 655303
1
IO – Output Current – A
IO – Output Current – A
12
0.4
• DALLAS, TEXAS 75265
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
TYPICAL CHARACTERISTICS
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
7
90
I DD(OL) – Supply Current, Output Disabled – µ A
I DD(OH) – Supply Current, Output Enabled – µ A
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
IO = 0 A
85
5.5 V
80
75
5V
70
65
4.5 V
60
55
50
–50
4V
–25
0
25
50
75
100
125
6.5
VI = 5.5 V
6
5.5
VI = 5 V
5
VI = 4.5 V
4.5
4
VI = 4 V
3.5
3
–50
–25
0
50
100
75
125
Figure 14
Figure 13
SUPPLY CURRENT, OUTPUT DISABLED
vs
INPUT VOLTAGE
SUPPLY CURRENT, OUTPUT ENABLED
vs
INPUT VOLTAGE
90
I DD(OL) – Supply Current, Output Disabled – µ A
I DD(OH) – Supply Current, Output Enabled – µ A
25
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
85
80
75
70
125°C
65
–40°C
60
6.8
6.4
6
TJ = 125°C
5.6
5.2
4.8
TJ = 25°C
4.4
4
3.6
55
4
4.25
4.5
4.75
5
5.25
5.5
4
4.25
4.5
4.75
5
5.25
5.5
VI – Input Voltage – V
VI – Input Voltage – V
Figure 15
Figure 16
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
TYPICAL CHARACTERISTICS
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
ON-STATE RESISTANCE
vs
INPUT VOLTAGE
130
100
TJ = 25°C
120
r ON – On-State Resistance – Ω
r ON – On-State Resistance – Ω
95
110
100
VI = 4 V
90
VI = 5.5 V
80
70
90
85
80
75
60
50
–50
70
–25
0
25
50
75
100
125
4
4.3
TJ – Junction Temperature – °C
Figure 17
5
5.3
5.5
SHORT-CIRCUIT OUTPUT CURRENT
vs
INPUT VOLTAGE
0.24
2.15
IO = 1.5 A
I OS – Short-Circuit Output Current – A
VI to V O – Input Voltage to Output Voltage – V
4.8
Figure 18
INPUT VOLTAGE TO OUTPUT VOLTAGE
vs
INPUT VOLTAGE
0.2
0.16
IO = 1 A
0.12
IO = 600 mA
0.08
IO = 200 mA
0.04
0
2.05
1.95
TSP2015
1.85
1.75
1.65
1.55
TSP2014
1.45
1.35
4
4.25
4.5
4.75
5
5.25
5.5
4
VI – Input Voltage – V
4.25
4.5
4.75
Figure 20
POST OFFICE BOX 655303
5
VI – Input Voltage – V
Figure 19
14
4.5
VI – Input Voltage – V
• DALLAS, TEXAS 75265
5.25
5.5
TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
TYPICAL CHARACTERISTICS
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
2.4
5
4.8
I OS – Short-Circuit Output Current – A
4.4
4.2
4
3.8
3.6
TPS2014
3.4
3.2
3
4
4.3
4.6
4.9
5.2
2.2
2
TPS2015
1.8
1.6
TPS2014
1.4
1.2
1
–50
5.5
–25
0
25
50
75
100
125
TJ – Junction Temperature – °C
VI – Input Voltage – V
Figure 21
Figure 22
UVLO TRIP VOLTAGE
vs
JUNCTION TEMPERATURE
4.3
4
UVLO Trip Voltage – V
I OT – Threshold Trip Current – A
TPS2015
4.6
3.7
3.4
3.1
2.8
2.5
2.2
–50
–25
0
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 23
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
APPLICATION INFORMATION
TPS2014
2
Power Supply
4V–5V
3
0.1 µF
IN
IN
OUT
OUT
OUT
10 kΩ
Overcurrent Output
Load Enable
5
4
External Load
8
7
6
+
0.1 µF
22 µF
OC
EN
GND
1
Figure 24. Typical Application
power supply considerations
The TPS20xx has multiple inputs and outputs that must be connected in parallel to minimize voltage drop and
prevent unnecessary power dissipation.
A 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended. A high-value
electrolytic capacitor is also desirable when the output load is heavy or has large paralleled capacitors.
Bypassing the output with a 0.1-µF ceramic capacitor improves the immunity of the device to electrostatic
discharge (ESD).
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike sense resistors and polyfuses, sense FETs
do not increase series resistance to the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Shutdown only occurs when
the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figures 7 and 8). The TPS20xx senses the short and
immediately switches into a constant-current output.
Under the second condition, the short occurs while the device is enabled. At the instant the short occurs, very
high currents flow for a short time before the current-limit circuit can react (see Figures 3 and 4). After the
current-limit circuit has tripped, the device limits normally.
Under the third condition, the load has been gradually increased beyond the recommended operating current.
The current is permitted to rise until the current-limit threshold is reached (see Figures 5 and 6). The TPS20xx
is capable of delivering current up to the current-limit threshold without damage. When the threshold has been
reached, the device switches into its constant-current mode.
16
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POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
APPLICATION INFORMATION
power dissipation and junction temperature
The low on-resistance of the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistance of these packages is high compared to that of power packages; it is good
design practice to check power dissipation and junction temperature. The first step is to find ron at the input
voltage and at the operating temperature. As an initial estimate, use the highest operating ambient temperature
of interest and read ron from Figure 17. Next calculate the power dissipation using:
P
D
+ ron
I2
Finally, calculate the junction temperature:
T
J
Where:
+ PD
R
qJA
) TA
TA = Ambient temperature
RθJA = Thermal resistance SOIC = 172°C/W, P = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection is provided to prevent damage to the IC when heavy-overload or a short-circuit fault is
present for an extended period of time. The fault forces the TPS20xx into constant current mode, which causes
the voltage across the high-side switch to increase. Under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to dangerously
high levels. The protection circuit senses the junction temperature of the switch and shuts it off. The switch
remains off until the junction temperature has dropped approximately 20°C. The switch continues to cycle in
this manner until the load fault or the input power is removed.
undervoltage lockout
An undervoltage lockout is provided to ensure that the power switch is in the off state at power up. Whenever
the input voltage falls below approximately 3.2 V, the power switch quickly turns off. This facilitates the design
of hot-insertion systems that may not have the ability to turn off the power switch before input power is removed.
Upon reapplication of the input voltage (if enabled), the power switch turns on with a controlled rise time to
reduce inrush current, EMI, and voltage overshoots.
For proper operation of the UVLO, the TPS20xx requires the voltage decay from 3 V to 2 V to take at least
200 µs. Capacitance is added to the input or output of the TPS20xx to increase this decay rate. Capacitance
is generally added to the output to lower inrush current due to input capacitance.
Universal Serial Bus (USB) applications
The USB specification provides for five different classes of devices based on their power sourcing and sinking
requirements. These classes of devices are: bus-powered hub, self-powered hub, lower power bus-powered
function, high power bus-powered function, and self-powered functions. The TPS20xx can provide power
distribution solutions for many of these devices.
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POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
APPLICATION INFORMATION
bus-powered and self-power hubs
Hubs provide data and power for downstream functions through output ports. Self-power hubs have internal
power supplies that furnish power to downstream functions. Each port is required to supply 500 mA continuous
to a downstream function. Each port must have overcurrent protection to meet the requlatory safety limit that
no single port can deliver more than 5 A. The self-power hub must also have a method to detect and report an
overcurrent condition to the USB host. The TPS20xx provides the required current-limiting function and has an
overcurrent logic output to inform the hub controller of the fault condition. The on-state resistance of the
TPS20xx is low enough to meet all USB voltage regulation requirements. The switch also provides the capability
to remove power from a faulted port.
Bus-powered hubs distribute power and data from an input port to downstream ports. Each output port is
required to supply 100 mA continuous. A bus-powered hub is not required to provide overcurrent protection
because it is provided by the upstream port. In order to power up in a low power state, the self-powered hub
must be able to switch power to its output ports. The TPS20xx can also provide this function.
TUSB2040
USB Port
Connector
USB
Controller
D1+
D+
D1-
DTPS2014
5
OVERCURRENT
LOAD ENABLE
Power Supply
4
OC
EN
OUT
OUT
OUT
10 kΩ
8
7
6
5V
+
120 µF
0.1 µF
GND
SN75240
3.3 V
2
5V
3
0.1 µF
IN
IN
GND
1
Figure 25. Typical USB Self-Powered Hub Application
low power bus-powered functions and high power bus-powered functions
Low-power and high-power bus-powered functions are powered by their input ports. If the load of the function
is more than the parallel combination of 44 Ω and 10 µF, it must implement inrush current limiting. The TPS20xx
provides this function with its controlled rise time during turn on.
18
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POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
APPLICATION INFORMATION
USB Port
Connector
Internal
Function
D+
D+
D-
DTPS2014
5
4
5V
OC
EN
OUT
OUT
GND
OUT
2
3
0.1 µF
8
7
6
5V
+
22 µF
0.1 µF
GND
IN
IN
GND
1
Figure 26. Typical USB Bus-Powered Function Application
ESD protection
All TPS20xx terminals incorporate ESD-protection circuitry designed to withstand a 6-kV human-body-model
discharge as defined in MIL-STD-883C. Additionally, the output is protected from discharges up to 12 kV.
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TPS2014, TPS2015
POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / B 03/95
NOTES: A.
B.
C.
D.
E.
20
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Four center pins are connected to die mount pad.
Falls within JEDEC MS-012
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POWER DISTRIBUTION SWITCHES
SLVS159B – DECEMBER 1996 – REVISED AUGUST 1997
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040082 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
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