TI SN74AC373DW

 SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
D
SN54AC373 . . . J OR W PACKAGE
SN74AC373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
2-V to 6-V VCC Operation
Inputs Accept Voltages to 6 V
Max tpd of 9.5 ns at 5 V
3-State Noninverting Outputs Drive Bus
Lines Directly
Full Parallel Access for Loading
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54AC373 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
VCC
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
2D
2Q
3Q
3D
4D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
LE
5Q
5D
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
8Q
D
D
D
D
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
PDIP − N
SN74AC373N
Tube
SN74AC373DW
Tape and reel
SN74AC373DWR
SOP − NS
Tape and reel
SN74AC373NSR
AC373
SSOP − DB
Tape and reel
SN74AC373DBR
AC373
Tube
SN74AC373PW
Tape and reel
SN74AC373PWR
CDIP − J
Tube
SNJ54AC373J
SNJ54AC373J
CFP − W
Tube
SNJ54AC373W
SNJ54AC373W
LCCC − FK
Tube
SNJ54AC373FK
SNJ54AC373FK
TSSOP − PW
−55°C
125°C
−55
C to 125
C
TOP-SIDE
MARKING
Tube
SOIC − DW
−40°C
85°C
−40
C to 85
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74AC373N
AC373
AC373
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
$'"! !$& ./0 && $## # ##'
"&# )#+# #'( && )# $'"! $'"!
$!#- '# #!#&, !&"'# #- && $##(
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1
11
C1
1D
3
2
1Q
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Input voltage
IOL
MAX
MIN
MAX
2
6
2
6
2.1
2.1
3.15
3.15
3.85
3.85
0
High-level output current
Low-level output current
∆t/∆v
MIN
0
Output voltage
IOH
SN74AC373
VCC = 4.5V
VCC = 5.5 V
Low-level input voltage
VI
VO
SN54AC373
0.9
1.35
1.35
1.65
1.65
0
0
VCC
VCC
VCC = 3 V
VCC = 4.5 V
−12
−12
−24
−24
VCC = 5.5 V
VCC = 3 V
−24
−24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
8
8
Input transition rise or fall rate
V
V
0.9
VCC
VCC
UNIT
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 µA
VOH
VOL
IOH = −12 mA
TA = 25°C
TYP
MAX
SN54AC373
SN74AC373
MIN
MIN
VCC
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.56
2.4
2.46
MAX
MAX
UNIT
V
4.5 V
3.86
3.7
3.76
IOH = −24 mA
5.5 V
4.86
4.7
4.76
3V
0.1
0.1
0.1
IOL = 50 µA
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
±0.1
±1
±1
µA
5.5 V
±0.25
±5
±2.5
µA
4
80
40
µA
IOL = 12 mA
IOL = 24 mA
II
IOZ
VI = VCC or GND
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
IO = 0
5.5 V
5V
POST OFFICE BOX 655303
4.5
• DALLAS, TEXAS 75265
V
pF
3
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54AC373
SN74AC373
MIN
MIN
MAX
MAX
UNIT
tw
tsu
Pulse duration, LE high
5.5
6.5
6
ns
Setup time, data before LE↓
5.5
6.5
6
ns
th
Hold time, data after LE↓
1
1
1
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54AC373
SN74AC373
MIN
MIN
MAX
MAX
UNIT
tw
tsu
Pulse duration, LE high
4
5
4.5
ns
Setup time, data before LE↓
4
5
4.5
ns
th
Hold time, data after LE↓
1
1
1
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
MIN
TA = 25°C
TYP
MAX
SN54AC373
SN74AC373
MIN
MAX
MIN
MAX
1.5
10
13.5
1
16.5
1.5
15
1.5
9.5
13.0
1
16
1.5
14.5
1.5
10
13.5
1
16.5
1.5
15
1.5
9.5
12.5
1
15
1.5
14
1.5
9
11.5
1
14
1
13
1.5
8.5
11.5
1
13.5
1
13
1.5
10
12.5
1
16
1
14.5
1.5
8
11.5
1
13
1
12.5
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
MIN
TA = 25°C
TYP
MAX
SN54AC373
SN74AC373
MIN
MAX
MIN
MAX
1.5
7
9.5
1
11.5
1.5
10.5
1.5
7
9.5
1
11.5
1.5
10.5
1.5
7.5
9.5
1
12
1.5
10.5
1.5
7
9.5
1
11
1.5
10.5
1.5
7
8.5
1
10.5
1
9.5
1.5
6.5
8.5
1
10
1
9.5
1.5
8
11
1
13.5
1
12.5
1.5
6.5
8.5
1
10.5
1
10
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
40
pF
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
500 Ω
LOAD CIRCUIT
VCC
50% VCC
Timing Input
0V
tw
tsu
3V
Input 50% VCC
50% VCC
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
50% VCC
0V
In-Phase
Output
50% VCC
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
tPLZ
50%VCC
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
≈VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
50% VCC
50% VCC
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
VCC
50% VCC
tPZL
tPHL
tPLH
50% VCC
0V
VOLTAGE WAVEFORMS
50% VCC
VCC
50% VCC
Data Input
0V
Input
th
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-87555012A
ACTIVE
LCCC
FK
20
1
TBD
5962-8755501RA
ACTIVE
CDIP
J
20
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
5962-8755501SA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
5962-8755501VRA
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
5962-8755501VSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
SN74AC373DBLE
OBSOLETE
SSOP
DB
20
SN74AC373DBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373DBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AC373NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AC373NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373NSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373PWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373PWLE
OBSOLETE
TSSOP
PW
20
SN74AC373PWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AC373PWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54AC373FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54AC373J
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
SNJ54AC373W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
TBD
TBD
Call TI
Call TI
Call TI
Call TI
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
24-Apr-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AC373DBR
DB
20
MLA
330
16
8.2
7.5
2.5
12
16
Q1
SN74AC373DWR
DW
20
MLA
330
24
10.8
13.0
2.7
12
24
Q1
SN74AC373NSR
NS
20
MLA
330
24
8.2
13.0
2.5
12
24
Q1
SN74AC373PWR
PW
20
MLA
330
16
6.95
7.1
1.6
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74AC373DBR
DB
20
MLA
333.2
333.2
28.58
SN74AC373DWR
DW
20
MLA
333.2
333.2
31.75
SN74AC373NSR
NS
20
MLA
333.2
333.2
31.75
SN74AC373PWR
PW
20
MLA
333.2
333.2
28.58
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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