TI OPA301AID

OPA300, OPA2300
OPA301, OPA2301
SBOS271B − MAY 2003 − REVISED JUNE 2005
Low-Noise, High-Speed, 16-Bit Accurate, CMOS
OPERATIONAL AMPLIFIER
FEATURES
D
D
D
D
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D
D
D
D
DESCRIPTION
High Bandwidth: 150MHz
16-Bit Settling in 150ns
Low Noise: 3nV/√Hz
Low Distortion: 0.003%
Low Power: 9.5mA (typ) on 5.5V
Shutdown to 5µA
Unity-Gain Stable
Excellent Output Swing:
(V+) − 100mV to (V−) + 100mV
Single Supply: +2.7V to +5.5V
Tiny Packages: MSOP and SOT23
The OPA300 and OPA301 series high-speed,
voltage-feedback, CMOS operational amplifiers are
designed for 16-bit resolution systems. The
OPA300/OPA301 series are unity-gain stable and
feature excellent settling and harmonic distortion
specifications. Low power applications benefit from low
quiescent current. The OPA300 and OPA2300 feature
a digital shutdown (Enable) function to provide
additional power savings during idle periods. Optimized
for single-supply operation, the OPA300/OPA301
series offer superior output swing and excellent
common-mode range.
APPLICATIONS
D
D
D
D
The OPA300 and OPA301 series op amps have
150MHz of unity-gain bandwidth, low 3nV/√Hz voltage
noise, and 0.1% settling within 30ns. Single-supply
operation from 2.7V (±1.35V) to 5.5V (±2.75V) and an
available shutdown function that reduces supply
current to 5µA are useful for portable low-power
applications. The OPA300 and OPA301 are available in
SO-8 and SOT-23 packages. The OPA2300 is available
in MSOP-10, and the OPA2301 is available in SO-8 and
MSOP-8. All versions are specified over the industrial
temperature range of −40°C to +125°C.
16-Bit ADC Input Drivers
Low-Noise Preamplifiers
IF/RF Amplifiers
Active Filtering
130pF
(mica)
1820Ω
fS = 1.25MSPS
f = 10kHz
5V
1820Ω
VIN
10Ω
130pF
(mica)
ADS8401
OPA30x
1.5nF
Typical Application
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2003−2005, Texas Instruments Incorporated
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SBOS271B − MAY 2003 − REVISED JUNE 2005
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
OPA300
SO-8
D
300A
OPA300
SOT23-6
DBV
A52
OPA301
SO-8
D
301A
OPA301
SOT23-5
DBV
AUP
OPA2300
MSOP−10
DGS
C01
OPA2301A
OPA2301
SO−8
D
OPA2301
MSOP−8
DGK
C02
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
ELECTROSTATIC DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
Power Supply V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Signal Input Terminals(2), Voltage . . . . . . . . . . . 0.5V to (V+) + 0.5V
Current . . . . . . . . . . . . . . . . . . . . . ±10mA
Open Short-Circuit Current(3) . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
ESD Ratings
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . 500V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) Input terminals are diode clamped to the power-supply rails. Input
signals that can swing more than 0.5V beyond the supply rails
should be current limited to 10mA or less.
(3) Short-circuit to ground; one amplifier per package.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PIN ASSIGNMENTS
Top View
OPA300
OPA300
1
8
Enable
−In
2
7
V+
V− 2
+In
3
6
VOUT
+In 3
V−
4
5
Out 1
A52
NC(1)
MSOP, SO, SOT
OPA2300
6
V+
Out A 1
5
Enable
−In A 2
4
−In
+In A 3
NC(1)
10 V+
A
B
V− 4
9
Out B
8
−In B
7
+In B
6
Enable B
8
V+
7
Out B
6
−In B
5
+In B
SOT23−6 (2)
Enable A 5
SO−8
OPA301
MSOP−10
OPA301
OPA2301
NC(1)
1
8
NC(1)
−In
2
7
V+
+In
3
6
VOUT
V−
4
5
NC(1)
Out 1
5
V+
Out A 1
V− 2
A
+In 3
4
−In
−In A 2
+In A 3
SOT23−5
B
V− 4
SO−8
SO−8, MSOP−8
NOTE: (1) Not connected. (2) SOT23-6 pin 1 oriented as shown with reference to package marking.
2
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SBOS271B − MAY 2003 − REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS: VS = 2.7V to 5.5V
Boldface limits apply over the temperature range, TA = −40°C to +125°C.
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, VOUT = VS/2, and VCM = VS/2, unless otherwise noted.
OPA300, OPA301
OPA2300, OPA2301
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
Over Temperature
Drift
vs. Power Supply
Channel Separation, dc
f = 5MHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
INPUT BIAS CURRENT
Input Bias Current
Input Offset Current
TEST CONDITIONS
VOS
MIN
VS = 5V
dVOS/dT
PSRR
VCM
CMRR
(V−) − 0.2
66
OPEN-LOOP GAIN
Open−Loop Voltage Gain
Over Temperature
en
in
NTSC, RL = 150Ω
NTSC, RL = 150Ω
AOL
Over Temperature
UNITS
1
5
7
mV
mV
µV/°C
µV/V
VS = 5V, RL = 2kΩ, 0.1V < VO < 4.9V
VS = 5V, RL = 2kΩ, 0.1V < VO < 4.9V
VS = 5V, RL = 100Ω, 0.5V < VO < 4.5V
VS = 5V, RL = 100Ω, 0.5V < VO < 4.5V
95
90
95
90
200
dB
dB
(V+) − 0.9
V
dB
±5
±5
pA
pA
80
±0.1
±0.5
IB
IOS
INPUT IMPEDANCE
Differential
Common-Mode
NOISE
Input Voltage Noise, f = 0.1Hz to 1MHz
Input Voltage Noise Density, f > 1MHz
Input Current Noise Density, f < 1kHz
Differential Gain Error
Differential Phase Error
MAX
2.5
50
140
100
VS = 2.7V to 5.5V, VCM < (V+) –0.9V
(V−) − 0.2V < VCM < (V+) – 0.9V
TYP
1013 || 3
1013 || 6
Ω || pF
Ω || pF
40
3
1.5
0.01
0.1
µVPP
nV/√Hz
fA/√Hz
%
°
106
dB
dB
dB
dB
106
OUTPUT
Voltage Output Swing from Rail
Short-Circuit Current
Capacitive Load Drive
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time, 0.01%
0.1%
Overload Recovery Time
Total Harmonic Distortion + Noise
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
Quiescent Current (per amplifier)
Over Temperature
RL = 2kΩ, AOL > 95dB
RL = 100Ω, AOL > 95dB
ISC
CLOAD
GBW
SR
tS
THD+N
SHUTDOWN
tOFF
tON
VL (shutdown)
VH (amplifier is active)
IQSD (per amplifier)
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance
SO-8, MSOP−8, MSOP-10
SOT23-5, SOT23-6
150
80
90
30
30
0.003
G = +1
VS = 5V, 2V Step, G = +1
Gain = −1
VS = 5V, VO = 3VPP, G = +1, f = 1kHz
VS
IQ
75
100
300
500
70
See Typical Characteristics
2.7
IO = 0
MHz
V/µs
ns
ns
ns
%
5.5
2.7 to 5.5
9.5
12
13
V
V
mA
mA
(V−) + 0.8
(V+) + 0.2
10
ns
µs
V
V
µA
40
5
(V−) − 0.2
(V−) + 2.5
3
−40
−55
−60
+125
+125
+150
θJA
150
200
mV
mV
mA
°C
°C
°C
°C/W
°C/W
°C/W
3
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SBOS271B − MAY 2003 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS
All specifications at TA = 25°C, VS = 5V, and RL = 150Ω connected to VS/2 unless otherwise noted.
INVERTING GAIN
SMALL−SIGNAL FREQUENCY RESPONSE
NONINVERTING GAIN
SMALL−SIGNAL FREQUENCY RESPONSE
3
3
VO = 0.1VPP
RF = 310Ωfor G > 1
G=1
Normalized Gain (dB)
Normalized Gain (dB)
0
−3
G=5
G=2
−9
G = 10
1M
G = −10
−9
−15
10M
100M
1M
1G
10M
1G
SMALL−SIGNAL STEP RESPONSE
Output Voltage (10mV/div)
Output Voltage (500mV/div)
LARGE−SIGNAL STEP RESPONSE
VOUT
Time (50ns/div)
Time (5ns/div)
LARGE−SIGNAL ENABLE/DISABLE RESPONSE
Enable Pin
Normalized Gain (dB)
Output Voltage (500mV/div)
100M
Frequency (Hz)
Frequency (Hz)
Amplifier
Output
0.1dB GAIN FLATNESS FOR VARIOUS RF
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
Time (100µs/div)
4
G = −2
G = −5
−6
−12
VO = 0.1VPP
RF = 310Ωfor G > 1
−15
G = −1
−3
Gain = 2
VO = 0.1VPP
RF = 825Ω
RF = 450Ω
RF = 205Ω
1
10
Frequency (MHz)
100
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SBOS271B − MAY 2003 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VS = 5V, and RL = 150Ω connected to VS/2 unless otherwise noted.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−60
HARMONIC DISTORTION vs NONINVERTING GAIN
−50
RL = 200Ω
f = 1MHz
RF = 310Ω
G=2
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−50
THD
−70
2nd−Harmonic
−80
3rd−Harmonic
−90
−100
VO = 2VPP
RL = 200Ω
f = 1MHz
RF = 310Ω
−60
−70
THD
2nd−Harmonic
−80
3rd−Harmonic
−90
−100
−110
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1
10
Gain (V/V)
Output Voltage (VPP)
HARMONIC DISTORTION vs INVERTING GAIN
−70
THD
2nd−Harmonic
3rd−Harmonic
−80
−90
−100
−60
−70
VO = 2VPP
RL = 200Ω
Gain = 2
RF = 310Ω
THD
−80
2nd−Harmonic
−90
3rd−Harmonic
−100
−110
−110
1
10
−60
−120
100k
1M
10M
Gain (V/V)
Frequency (Hz)
HARMONIC DISTORTION vs LOAD RESISTANCE
INPUT VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
10k
THD
−70
2nd−Harmonic
−75
VO = 2VPP
f = 1MHz
Gain = 2
RF = 310Ω
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)
−65
−80
−85
−90
HARMONIC DISTORTION vs FREQUENCY
−50
Harmonic Distortion (dBc)
VO = 2VPP
RL = 200Ω
f = 1MHz
RF = 310Ω
−60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−50
3rd−Harmonic
Current Noise
1k
Voltage Noise
100
10
−95
−100
100
1k
Load Resistance (Ω)
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
5
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SBOS271B − MAY 2003 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VS = 5V, and RL = 150Ω connected to VS/2 unless otherwise noted.
FREQUENCY RESPONSE FOR VARIOUS RL
Gain = 1
VO = 0.1VPP
FREQUENCY RESPONSE vs CAPACITIVE LOAD
3
Normalized Gain (dB)
3
−3
Gain (dB)
CLOAD = 1pF, RS = 75Ω
RLOAD = 1kΩ
RLOAD = 150Ω
−9
RLOAD = 50Ω
−15
−3
CLOAD = 5pF
RS = 55Ω
−9
CLOAD = 10pF
RS = 40Ω
−15
CLOAD = 47pF
RS = 30Ω
RS
−21
−21
10M
100M
CL
−27
10M
500
100M
Frequency (Hz)
OPEN−LOOP GAIN AND PHASE vs FREQUENCY
100
PSRR V+
PSRR V−
80
CMRR
60
Gain (dB)
PSRR (dB)
CMRR (dB)
70
50
40
30
20
10
0
10k
100k
1M
500
Frequency (Hz)
COMMON−MODE REJECTION RATIO AND
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
90
CLOAD = 100pF
RS = 20Ω
10M
100M
1G
110
100
90
80
70
60
50
40
30
20
10
0
−10
100
0
Gain
−30
Phase
−60
−90
Phase (_)
9
−120
−150
−180
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
COMPOSITE VIDEO
DIFFERENTIAL GAIN AND PHASE
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
5.0
1.0
VS = 5V
4.0
Output Voltage (V)
0.8
dP (_ )
dG (%)
25_C
0.6
dP
0.4
−40_ C
3.0
−55_C
125_C 85_ C
2.0
25_ C
1.0
0.2
dG
0
0
1
2
3
Number of 150Ω Loads
6
4
0
10
20
30
40
50
Output Current (mA)
60
70
80
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SBOS271B − MAY 2003 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VS = 5V, and RL = 150Ω connected to VS/2 unless otherwise noted.
INPUT BIAS CURRENT vs TEMPERATURE
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
1
2.7
VS = 2.7V
2.4
Input Bias Current (pA)
Output Voltage (V)
2.1
1.8
1.5
125_ C 85_C 25_ C −40_C −55_ C
1.2
0.9
0.6
0.1
0.3
0.01
0
0
10
20
30
40
50
60
70
−40
80
−20
0
20
40
60
80
100
120
140
Temperature (_ C)
Output Current (mA)
QUIESCENT CURRENT vs TEMPERATURE
INPUT BIAS CURRENT vs COMMON−MODE VOLTAGE
12
2
VS = ±2.5V
Input Bias Current (pA)
Quiescent Current (mA)
11
10
9
8
1
0
−1
7
−2
6
−40
−20
0
20
40
60
80
100
120
−3
140
−2
Temperature (_ C)
POWER−SUPPLY REJECTION RATIO AND
COMMON−MODE REJECTION RATIO vs TEMPERATURE
0
1
2
SHORT−CIRCUIT CURRENT vs TEMPERATURE
100
80
95
60
Short−Circuit Current (mA)
VS = 5.5V
90
PSRR
PSRR (dB)
CMRR (dB)
−1
Common−Mode Voltage (V)
85
80
CMRR
75
70
40
20
0
−20
−60
60
−40
−80
−40
0
20
40
60
80
Temperature (_C)
100
120
140
VS = 5V
VS = 2.7V
−40
65
−20
VS = 3.5V
VS = 5.5V
−20
0
20
40
60
80
100
120
140
Temperature (_C)
7
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SBOS271B − MAY 2003 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VS = 5V, and RL = 150Ω connected to VS/2 unless otherwise noted.
OUTPUT IMPEDANCE vs FREQUENCY
QUIESCENT CURRENT vs SUPPLY VOLTAGE
1000
12
Output Impedance, ZO (Ω)
Quiescent Current (mA)
11
10
9
8
7
100
G=2
10
G=1
1
0.1
6
0.01
5
2.5
3
3.5
4
4.5
5
10k
5.5
100k
1M
10M
100M
Frequency (Hz)
Supply Voltage (V)
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
OPEN−LOOP GAIN vs TEMPERATURE
5
120
RLOAD = 2kΩ
VS = 5V
Open−Loop Gain (dB)
Output Voltage (VPP)
4
3
VS = 2.7V
2
110
RLOAD = 2kΩ
100
RLOAD = 100Ω
90
1
0
1
10
80
−40
100
−20
0
20
Frequency (MHz)
0.2
20
0.1
18
0
−0.1
16
Percent of Amplifiers
Output Error (%)
60
80
100
120
140
4
5
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
OUTPUT SETTLING TIME TO 0.1%
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
14
12
10
8
6
4
−0.8
2
−0.9
−1.0
0
0
20
40
60
Time (ns)
8
40
Temperature (_C)
80
100
−5
−4
−3
−2
−1
0
1
Offset Voltage (mV)
2
3
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SBOS271B − MAY 2003 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VS = 5V, and RL = 150Ω connected to VS/2 unless otherwise noted.
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
Percent of Amplifiers
20
15
10
5
0
−10 −8
−6
−4
−2
0
2
4
6
8
10
Offset Voltage Drift (µV/_C)
9
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SBOS271B − MAY 2003 − REVISED JUNE 2005
APPLICATIONS INFORMATION
The OPA300 and OPA301 series of single-supply
CMOS op amps are designed to interface with
high-speed 16-bit analog-to-digital converters (ADCs).
Featuring wide 150MHz bandwidth, fast 150ns settling
time to 16 bits, and high open loop gain, this series
offers excellent performance in a small SO-8 and tiny
SOT23 packages.
PCB LAYOUT
As with most high-speed operational amplifiers, board
layout requires special attention to maximize AC and
DC performance. Extensive use of ground planes, short
lead lengths, and high-quality bypass capacitors will
minimize leakage that can compromise signal quality.
Guard rings applied with potential as near to the input
pins as possible help minimize board leakage.
INPUT AND ESD PROTECTION
THEORY OF OPERATION
The OPA300 and OPA301 series op amps use a classic
two-stage topology, shown in Figure 1. The differential
input pair is biased to maximize slew rate without
compromising stability or bandwidth. The folded
cascode adds the signal from the input pair and
presents a differential signal to the class AB output
stage. The class AB output stage allows rail- to-rail
output
swing,
with
high-impedance
loads
(> 2kΩ), typically 100mV from the supply rails. With 10Ω
loads, a useful output swing can be achieved and still
maintain high open-loop gain. See the typical
characteristic Output Voltage Swing vs Output Current.
All OPA300/OPA301 series op amps’ pins are staticprotected with internal ESD protection diodes tied to the
supplies, as shown in Figure 2. These diodes will
provide overdrive protection if the current is externally
limited to 10mA, as stated in the Absolute Maximum
Ratings. Any input current beyond the Absolute
Maximum Ratings, or long-term operation at maximum
ratings, will shorten the lifespan of the amplifier.
+V
External
Pin
Internal
Circuitry
+VS
−V
Figure 2. ESD Protection Diodes
VOUT
+
VIN
−
VBIAS
Figure 1. OPA30x Classic Two-Stage Topology
OPERATING VOLTAGE
OPA300/OPA301 series op amp parameters are fully
specified from +2.7V to +5.5V. Supply voltages higher
than 5.5V (absolute maximum) can cause permanent
damage to the amplifier. Many specifications apply from
–40°C to +125°C. Parameters that vary significantly
with operating voltages or temperature are shown in the
Typical Characteristics.
10
ENABLE FUNCTION
The shutdown function of the OPA300 and OPA2300 is
referenced to the negative supply voltage of the
operational amplifier. A logic level HIGH enables the op
amp. A valid logic HIGH is defined as 2.5V above the
negative supply applied to the enable pin. A valid logic
LOW is defined as < 0.8V above the negative supply
pin. If dual or split power supplies are used, care should
be taken to ensure logic input signals are properly
referred to the negative supply voltage. If this pin is not
connected to a valid high or low voltage, the internal
circuitry will pull the node high and enable the part to
function.
The logic input is a high-impedance CMOS input. For
battery-operated applications, this feature may be used
to greatly reduce the average current and extend
battery life. The enable time is 10µs; disable time is 1µs.
When disabled, the output assumes a high-impedance
state. This allows the OPA300 to be operated as a gated
amplifier, or to have its output multiplexed onto a
common analog output bus.
"##$ %"##
"#&$ %"#&
www.ti.com
SBOS271B − MAY 2003 − REVISED JUNE 2005
DRIVING CAPACITIVE LOADS
DRIVING A 16-BIT ADC
When using high-speed operational amplifiers, it is
extremely important to consider the effects of
capacitive loading on amplifier stability. Capacitive
loading will interact with the output impedance of the
operational amplifier, and depending on the capacitor
value, may significantly decrease the gain bandwidth,
as well as introduce peaking. To reduce the effects of
capacitive loading and allow for additional capacitive
load drive, place a series resistor between the output
and the load. This will reduce available bandwidth, but
permit stable operation with capacitive loading.
Figure 3 illustrates the recommended relationship
between the resistor and capacitor values.
The OPA300/OPA301 series feature excellent
THD+noise, even at frequencies greater than 1MHz,
with a 16-bit settling time of 150ns. Figure 4 shows a
total single supply solution for high-speed data
acquisition. The OPA300/OPA301 directly drives the
ADS8401, a 1.25 mega sample per second (MSPS)
16-bit data converter. The OPA300/OPA301 is
configured in an inverting gain of 1, with a 5V single
supply. Results of the OPA300/OPA301 performance
are summarized in Table 1.
130pF
(mica)
100
Series Resistance (Ω)
1820Ω
75
fS = 1.25MSPS
f = 10kHz
5V
1820Ω
VIN
50
10Ω
130pF
(mica)
ADS8401
OPA30x
1.5nF
25
Figure 4. The OPA30x Drives the 16-Bit ADS8401
0
1
10
100
Capacitive Load (pF)
Figure 3. Recommended RS and CL Combinations
Amplifiers configured in unity gain are most susceptible
to stability issues. The typical characteristic, Frequency
Response vs Capacitive Load, describes the relationship between capacitive load and stability for the
OPA300/OPA301 series. In unity gain, the
OPA300/OPA301 series is capable of driving a few
picofarads of capacitive load without compromising
stability. Board level parasitic capacitance can often fall
into the range of a picofarad or more, and should be
minimized through good circuit-board layout practices
to avoid compromising the stability of the
OPA300/OPA301. For more information on detecting
parasitics during testing, see the Application Note
Measuring Board Parasitics in High-Speed Analog
Design (SBOA094), available at the TI web site
www.ti.com.
PARAMETER
RESULTS (f = 10kHz)
THD
−99.3dB
SFDR
101.2dB
THD+N
84.2dB
SNR
84.3dB
Table 1. OPA30x Performance Results Driving a
1.25MSPS ADS8401
11
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA2300AIDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2300AIDGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2300AIDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2300AIDGSTG4
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AID
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AIDGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AIDGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AIDGKT
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AIDGKTG4
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AIDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2301AIDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
OPA300AID
ACTIVE
SOIC
D
8
100
TBD
CU NIPDAU
Level-3-235C-168 HR
OPA300AIDBVR
ACTIVE
SOT-23
DBV
6
3000
TBD
CU SNPB
Level-2-240C-1 YEAR
OPA300AIDBVT
ACTIVE
SOT-23
DBV
6
250
TBD
CU SNPB
Level-2-240C-1 YEAR
OPA300AIDR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-3-235C-168 HR
OPA301AID
ACTIVE
SOIC
D
8
100
TBD
CU NIPDAU
Level-3-240C-168 HR
OPA301AIDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
CU NIPDAU
Level-1-235C-UNLIM
OPA301AIDBVT
ACTIVE
SOT-23
DBV
5
250
TBD
CU NIPDAU
Level-1-235C-UNLIM
OPA301AIDR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-3-240C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2005
temperature.
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