SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) 21:3 Data Channel Compression at up to 163 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI 21 Data Channels Plus Clock In Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant Data Inputs ESD Protection Exceeds 6 kV SN75LVDS84 Has Falling Clock-Edge Triggered Inputs, SN75LVDS85 Has Rising Clock-Edge-Triggered Inputs Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range: 31 MHz to 68 MHz No External Components Required for PLL Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the DS90C561 D4 VCC D5 D6 GND D7 D8 VCC D9 D10 GND D11 D12 NC D13 D14 GND D15 D16 D17 VCC D18 D19 GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 D3 D2 GND D1 D0 NC LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D20 NC – Not Connected description The SN75LVDS84 and SN75LVDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86. When transmitting, data bits D0 – D20 are each loaded into registers of the SN75LVDS84 upon the falling edge and into the registers of the SN75LVDS85 on the rising edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. AVAILABLE OPTIONS† LATCHING CLOCK EDGE FALLING RISING SN75LVDS84DGG SN75LVDS84DGGR SN75LVDS85DGG SN75LVDS85DGGR † The R suffix indicates taped and reeled packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 description (continued) The SN75LVDS84 or SN75LVDS85 require no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The SN75LVDS84 and SN75LVDS85 are characterized for operation over ambient free-air temperatures of 0_C to 70_C. functional block diagram 7 D0 – D6 Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD Y0P Y0M CLK 7 Parallel-Load 7-Bit Shift Register Y1P A,B, ...G D7 – D13 SHIFT/LOAD Y1M CLK 7 D14 – D20 Parallel-Load 7-Bit Shift Register Y2P A,B, ...G SHIFT/LOAD Y2M CLK Control Logic SHTDN 7× Clock/PLL CLKIN 7×CLK CLKOUTP CLK CLKOUTM CLKINH SN75LVDS84 only 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS D0 CLKIN (’LVDS85) CLKIN (’LVDS84) CLKOUT SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 ÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏ ÏÏ Previous Cycle ÏÏÏ ÏÏÏ ÏÏ ÏÏ ÏÏ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Current Cycle Next Cycle Y0 D0–1 D6 D5 D4 D3 D2 D1 D0 D6+1 Y1 D7–1 D13 D12 D11 D10 D9 D8 D7 D13+1 Y2 D14–1 D20 D19 D18 D17 D16 D15 D14 D20+1 Figure 1. Load and Shift Timing Sequences schematics of input and output EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH OUTPUT VCC VCC D or SHTDN 5Ω 50 Ω YnP or YnM 10 kΩ 7V 7V 300 kΩ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Output voltage range, VO (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range, VI (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING DGG 1316 mW 13.1 mW/°C 726 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. recommended operating conditions MIN NOM Supply voltage, VCC 3 3.3 High-level input voltage, VIH 2 Operating free-air temperature, TA UNIT 3.6 V V Low-level input voltage, VIL Differential load impedance, ZL MAX 0.8 V 90 132 Ω 0 70 °C MAX UNIT 14.7 32.4 ns 0.4 tc 0.6 tc ns 5 ns timing requirements MIN tc tw Input clock period tt tsu Transition time, input signal th Hold time, data, D0 – D27 valid after CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2) 4 Pulse duration, high-level input clock Setup time, data, D0 – D27 valid before CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NOM 3 ns 1.5 ns SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT |VOD| Input threshold voltage ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) VOC(PP) Steady-state common-mode output voltage IIH IIL High-level input current IOS Short circuit output current Short-circuit IOZ High-impedance output current ICC(AVG) MIN TYP† MAX 1.4 Differential steady-state output voltage magnitude Peak-to-peak common-mode output voltage RL = 100 Ω, Ω See Figure 3 See Figure 3 247 1.125 Quiescent supply current (average) 454 mV 50 mV V 150 mV 20 µA ±10 µA VO(Yn) = 0 VOD = 0 ±24 mA ±12 mA VO = 0 to VCC Disabled, All inputs at GND ±10 µA 280 µA VIH = VCC VIL = 0 Low-level input current V 1.375 80 UNIT Enabled, RL = 100 Ω (4 places) Gray-scale pattern (see Figure 4), VCC = 3.3 V, tc = 15.38 ns 68 80 mA Enabled, RL = 100 Ω, (4 places) Worst-case pattern (see Figure 5), tc = 15.38 ns 75 100 mA CI Input capacitance † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 pF 5 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER td0 Delay time, CLKOUT↑ to serial bit position 0 td1 Delay time, CLKOUT↑ to serial bit position 1 td2 Delay time, CLKOUT↑ to serial bit position 2 TEST CONDITIONS MIN TYP† – 0.2 0 * 0.2 2 t * 0.2 7 c td3 Delay time, CLKOUT↑ to serial bit position 3 td4 Delay time, CLKOUT↑ to serial bit position 4 * 0.2 4 t * 0.2 7 c td5 Delay time, CLKOUT↑ to serial bit position 5 5t 7 c td6 Delay time, CLKOUT↑ to serial bit position 6 tsk(o) Output skew, t n td7 Delay time, CLKIN↓ to CLKOUT↑ ∆ tc(o) C cle time, time Output O tp t clock jitter§ ( ) Cycle 1t 7 c 3t 7 c * 0.2 6 t * 0.2 7 c * n7 tc 0.2 ) 0.2 2 t ) 0.2 7 c 3 t ) 0.2 7 c 4 t ) 0.2 7 c 5 t ) 0.2 7 c 1t 7 c tc = 15.38 15 38 ns (± 0.2%), 0 2%) |Input clock jitter| < 50 ps‡, See Figure 6 MAX 6t 7 c – 0.2 UNIT ns ns ns ns ns ns ) 0.2 ns 0.2 ns tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 4.2 ns tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns, See Figure 7 ± 70 ps tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns, See Figure 7 ± 187 ps 4t 7 c ns tw Pulse duration, high-level output clock tt Transition time, differential output voltage (tr or tf) See Figure 3 ten Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 8 1 ms tdis Disable time, SHTDN↓ to off state (CLKOUT low) See Figure 9 250 ns 260 700 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ |Input clock jitter| is the magnitude of the change in the input clock period. § Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1500 ps SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Dn CLKIN (’LVDS84) tsu ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ th CLKIN (’LVDS85) NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Definition 49.9 Ω ± 1% (2 Places) YP VOD VOC YM CL = 10 pF Max (2 Places) NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. (a) SCHEMATIC 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure 3. Test Load and Voltage Definitions for LVDS Outputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION CLKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 All others NOTES: A. The 16-grayscale test-pattern test device power consumption for a typical display pattern. B. VIH = 2 V and VIL = 0.8 V C. SN75LVDS84 shown (CLKIN is inverted for SN75LVDS85). Figure 4. 16-Grayscale Test-Pattern Waveforms tc CLKIN Even Dn Odd Dn NOTES: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. B. VIH = 2 V and VIL = 0.8 V C. SN75LVDS84 shown (CLKIN is inverted for SN75LVDS85). Figure 5. Worst-Case Test-Pattern Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION td7 CLKIN (’LVDS84) CLKIN (’LVDS85) ÏÏ ÎÎ ÏÏÏ ÏÏ ÎÎ ÏÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ CLKOUT td0 Yn td1 td2 td3 td4 td5 td6 ≈ 2.5 V CLKIN VOD(H) CLKOUT or Yn 1.4 V 0V ≈ 0.5 V VOD(L) td7 td0 – td6 Figure 6. Timing Definitions + Reference ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz – 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz – 4200 MHz OUTPUT RF Output Device Under Test CLKIN CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 7. Clock Jitter Test Setup POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 TYPICAL CHARACTERISTICS CLKIN Dn ten SHTDN ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Invalid Yn Valid NOTE A: SN75LVDS84 shown. Figure 8. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT NOTE A: SN75LVDS84 shown. Figure 9. Disable Time Waveforms AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 70 200 180 VCC = 3.6 V Zero-to-Peak Output Jitter – ps I CC – Average Supply Current – mA 75 65 60 VCC = 3.3 V 55 VCC = 3 V 50 Grayscale Data Pattern RL = 100 Ω TA = 25°C 45 40 30 160 140 120 100 80 60 40 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.3 V TA = 25°C 20 0 40 50 60 70 fclk – Clock Frequency – MHz 0 0.5 Figure 10 10 1 1.5 Figure 11 POST OFFICE BOX 655303 2 2.5 f(mod) – Modulation Frequency – MHz • DALLAS, TEXAS 75265 3 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 APPLICATION INFORMATION Host Graphics Controller 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK Cable Flat Panel Display SN75LVDS84 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKIN SN75LVDS86 Y0M 41 8 A0M 100 Ω Y0P Y1M 40 9 39 10 A0P A1M 100 Ω Y1P Y2M 38 11 35 14 A1P A2M 100 Ω Y2P CLKOUTM 34 15 33 16 A2P CLKINM 100 Ω CLKOUTP 32 17 CLKINP NOTES: A. The five 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 12. Color Host to LCD Panel Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 APPLICATION INFORMATION Host Graphics Controller 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK Cable Flat Panel Display SN75LVDS84 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKIN SN75LVDS82 Y0M 41 9 A0M 100 Ω Y0P Y1M 40 10 39 11 A0P A1M 100 Ω Y1P Y2M 38 12 35 15 A1P A2M 100 Ω Y2P CLKOUTM 34 16 33 A2P CLKINM 100 Ω CLKOUTP 32 CLKINP A3M 100 Ω A3P NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application† † See the FlatLink Designer’s Guide (SLLA012) for more application information. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS84, SN75LVDS85 FLATLINK TRANSMITTERS SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999 MECHANICAL INFORMATION DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated