NT7181 V 2.1 LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface NT7181 Specification V 2.1 NOVATEK MICROELECTRONICS CORP. 1 1 FEATURES ....................................................................................................................................................................... 3 2 GENERAL DESCRIPTION ............................................................................................................................................ 3 2.1 BLOCK DIAGRAMS ....................................................................................................................................................... 3 3 PIN CONFIGURATION .................................................................................................................................................. 4 4 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................. 5 4.1 4.2 RECOMMENDED OPERATING CONDITIONS.................................................................................................................... 5 TIMING REQUIREMENTS ............................................................................................................................................... 5 5 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS......................... 6 6 SWING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS .................................... 7 7 PARAMETER MEASUREMENT INFORMATION.................................................................................................... 8 8 APPLICATION INFORMATION ............................................................................................................................... 12 9 ORDERING INFORMATION ..................................................................................................................................... 14 10 PACKAGE INFORMATION ....................................................................................................................................... 15 2 1 Features ! Low profile 56 Lead TSSOP Package ! Clock edge Programmable for Transmitter ! Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz ! Supports Spread Spectrum Clock Generator ! Suggests to use for LCD monitor only ! No External Components Required for PLL ! 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput ! Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI ! 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential ! Operates From a Single 3.3V Supply With 250mW (Typ) 2 General Description The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphic controllers. The NT7181 transmitter can be programmed for rising edge strobe(RFB=1) or falling edge strobe(RFB=0) through the RFB pin. When transmitting, data bits D0 - D27 are each loaded into registers of the NT7181 on the rising edge or falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN. The NT7181 requires no external components and little or no control. The data bus appears the same at the input to the transmitting and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C. 2.1 Block Diagrams NT7181 CMOS / TTL INPUTS DATA (LVDS) 7 TD0-6 7 TD7-13 TD14-20 TD21-27 7 7 T0P T T L P A R A L L E L T0M T1P T1M T2P | T O | L V D S T2M (175 Mbit/s To 595 Mbit/s On Each LVDS Cnannel) T3P T3M (TRANSMIT CLOCK IN) (25 MHz To 85 MHz) TCLKP PLL TCLKM CLOCK (LVDS) (25 MHz To 85 MHz) POWER DOWN 3 3 Pin Configuration NT7181 VCC 1 56 TD4 TD5 2 55 TD3 TD6 3 54 TD2 TD7 4 53 GND GND 5 52 TD1 TD8 6 51 TD0 TD9 7 50 TD27 TD10 8 49 LVDSGND VCC 9 48 T0M TD11 10 47 T0P TD12 11 46 T1M TD13 12 45 T1P GND 13 44 LVDSVCC TD14 14 43 LVDSGND TD15 15 42 T2M TD16 16 41 T2P RFB 17 40 TCLKM TD17 18 39 TCLKP TD18 19 38 T3M TD19 20 37 T3P GND 21 36 LVDSGND TD20 22 35 PLLGND TD21 23 34 PLLVCC TD22 24 33 PLLGND TD23 25 32 PWDN VCC 26 31 CLKIN TD24 27 30 TD26 TD25 28 29 GND 4 4 Absolute Maximum Ratings Supply voltage range, VCC (see Note1)……………………………………………………..-0.3V to 4V Output voltage range, VO…..……………….…………………………………………………-0.3V to VCC +0.3V Input voltage range, VI……………………………….……………………….…………………………-0.3V to Vcc +0.3V Storage temperature range, Tstg……………………………………………………………-65°C to 150°C Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds………………………260°C Junction Temperature…………………………………………………………………………150°C # Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. 4.1 Recommended Operating Conditions Symbol VCC Parameter Supply voltage Min. Nom. Max. Unit 3.0 3.3 3.6 V VIH High-level input voltage 2 VIL Low-level input voltage ZL Differential load impedance 90 TA Operating free-air temperature 0 V 100 0.8 V 110 Ω 70 °C 4.2 Timing requirements Symbol Parameter Min. Nom. Max. Unit TC Cycle time, input clock 11.8 40 ns tW Pulse duration, high-level input clock 0.4tc 0.6tc ns tT Transition, 5 ns tsu Setup time, data, TD0 - TD27 valid before CLKIN↑or CLKIN ↓ (See Figure 1) th Hold time, data, , TD0 - TD27 valid after CLKIN↑or CLKIN ↓ (See Figure 1) Note: th is measured under the conditions of input clock jitter of 1.9ns at 65MHz. 5 5 ns 2.5 ns 5 Electrical Characteristics Over Recommended Operating Conditions Symbol lVODl Parameter Min. Differential Steady-state Output Voltage Magnitude △IVODI Change in the Steady-state Differential Output Voltage Magnitude between Opposite binary States VOC(SS) Steady-state Common-mode Output Voltage VOC(PP) Peak-to-peak Common-mode Output Voltage Typ. 240 1.125 Max. Unit 490 mV 35 mV 1.475 V 150 mV Test Conditions RL = 100Ω, See Figure 2 See Figure 2 80 IIH High-level Input Current 20 μA VIH = VCC IIL Low-level Input Current ±30 μA VIL = 0 IOS Short-circuit Output Current ±24 mA VO(TP) = 0 ±12 mA VOD = 0 ±1 μA VO = 0 to Vcc 280 uA Disables, All inputs at GND IOZ ICC High-impedance State Output Current 68 80 mA Enables, RL = 100Ω, Gray-scale pattern (see Figure 3), VCC = 3.3V, tc = 15.38ns 75 110 mA Enabled, RL = 100Ω, (4 places) Worst-case pattern (see Figure 4), tc = 15.38ns Quiescent Supply Current *All typical values are at VCC = 3.3V, TA = 25°C 6 6 Swing Characteristics Over Recommended Operating Conditions Symbol Parameter Min. td0 Delay Time, TCLK↓ to Serial Bit Position 0 td1 Delay Time, TCLK↓ to Serial Bit Position 1 Typ.* Max. Unit -0.4 0.3 ns 1.8 2.5 Conditions ns td2 Delay Time, TCLK↓ to Serial Bit Position 2 4.0 4.7 ns td3 Delay Time, TCLK↓ to Serial Bit Position 3 6.2 6.9 ns td4 Delay Time, TCLK↓ to Serial Bit Position 4 8.4 9.1 td5 Delay Time, TCLK↓ to Serial Bit Position 5 10.6 11.3 td6 Delay Time, TCLK↓ to Serial Bit Position 6 12.8 13.5 ns ns ns td7 Delay Time, CLKIN↑ or CLKIN ↓ to TCLK↑ tw Pulse Duration, High-Level Output Clock tt Transition Time, Differential Output Voltage (tr or tf) ten tdis tc = 15.38 ns (± 0.2%), |Input Clock Jitter| < 50 ps** See Figure 5 tc = 15.38 ns (± 0.2%), |Input Clock Jitter| < 50 ps ** See Figure 5 3.0 4.2 5.5 ns 0.35tc 4 tc 7 0.65tc ns 260 700 1500 ps See Figure 2 Enable Time, PWDN ↑ to Phase Lock (TCLK Valid) 10 ms See Figure 6 Disable Time, PWDN ↓ to Off State (TCLK Low) 100 ns See Figure 7 * All typical values are at VCC = 3.3V, TA = 25°C ** |Input Clock Jitter| is the magnitude of the change in the input clock period. 7 7 Parameter Measurement Information tsu th TDn CLKIN (RFB=0) CLKIN (RFB=1) Note A: All input timing is defined at 1.4V on an input signal with a 10%-to-90% rise or fall time of less than 5ns. Figure 1. Setup and Hold Time Definition 49.9Ω 1% (2 Places) TP VOD Voc TM CL = 10 pF Max (2 Places) (a) SCHEMATIC 100% 80% VOD(H) 0V VOD(L) 20% 0% tr tf VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure 2. Test Load and Voltage Definitions for VLDS Outputs 8 CLKIN TD0, 8, 16 TD1, 9, 17 TD2, 10, 18 TD3, 11, 19 TD24 - 27 All others Notes: A. The 16-grayscale test-pattern test device power consumption for a typical display pattern. B. VIH = 2V and VIL = 0.8V. Figure 3. 16-Grayscale Test-Pattern Waveforms tc CLKIN Even TDn Odd TDn Notes: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. B. VIH = 2V and VIL = 0.8V. Figure 4. Worst-Case Test-Pattern Waveforms 9 td7 CLKIN (RFB=0) CLKIN (RFB=1) TCLK td0 Tn TD7 TD6 TD4 TD3 TD2 TD1 TD0 TD7+1 TD6+1 td1 td2 td3 td4 td5 td6 ≅ 2.5V CLKIN VOD(H) TCLK or Tn 1.4V ≅ 0.5V 0.00V VOD(L) td0 - td6 td7 Figure 5. Timing Definitions 10 PWDN TCLK ten Invalid ≈≈ ≈≈ ≈ TDn ≈≈ ≈≈ ≈ CLKIN Figure 6. Enable Time Waveforms CLKIN tdis PWDN TCLK Figure 7. Disable Time Waveforms 11 Valid 8 Application Information Host Cable Flat Panel Dispaly Graphic Controller 12-BIT 18-BIT 24-BIT RED0 RED0 RED0 RED1 RED1 RED1 RED2 RED2 RED2 RED3 RED3 RED3 RSVD RED4 RED4 RSVD NA RED5 RED5 NA NA NA RED6 RED7 GREEN0 GREEN0 GREEN0 GREEN1 GREEN1 GREEN1 GREEN2 GREEN2 GREEN2 GREEN3 GREEN3 GREEN3 RSVD GREEN4 GREEN4 RSVD GREEN5 GREEN5 NA NA GREEN6 NA BLUE0 NA BLUE0 GREEN7 BLUE0 BLUE1 BLUE1 BLUE1 BLUE2 BLUE2 BLUE2 BLUE3 BLUE3 BLUE3 RSVD BLUE4 BLUE4 RSVD BLUE5 BLUE5 NA NA BLUE6 NA H_SYNC NA BLUE7 H_SYNC H_SYNC V_SYNC V_SYNC V_SYNC ENABLE ENABLE ENABLE NA CLOCK NA CLOCK RSVD CLOCK NT7181 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 THC63LVDF84A D0 T0M 9 48 D1 A1M 100Ω D2 D3 T0P 47 10 46 11 A1P D4 D6 D27 T1M D5 A2M 100Ω D7 D8 T1P 45 12 A2P 42 15 D9 D12 D13 T2M D14 A3M 100Ω D10 D11 T2P 41 16 38 19 A3P D15 D18 T3M D19 D20 A4M 100Ω D21 D22 16 D16 18 D17 T3P 27 D24 28 D25 TCLKM 37 20 40 17 A4P CLKINM 100Ω 30 D26 25 D23 31 CLKIN TCLKP 39 18 CLKINP Figure 12. Color Host to LCD Panel Application 12 Host Cable Flat Panel Dispaly Graphic Controller 12-BIT 18-BIT 24-BIT RED0 RED0 RED0 RED1 RED1 RED1 RED2 RED2 RED2 RED3 RED3 RED3 RSVD RED4 RED4 RSVD NA RED5 RED5 NA NA NA RED6 RED7 GREEN0 GREEN0 GREEN0 GREEN1 GREEN1 GREEN1 GREEN2 GREEN2 GREEN2 GREEN3 GREEN3 GREEN3 RSVD GREEN4 GREEN4 RSVD GREEN5 GREEN5 NA NA GREEN6 NA BLUE0 NA BLUE0 GREEN7 BLUE0 BLUE1 BLUE1 BLUE1 BLUE2 BLUE2 BLUE2 BLUE3 BLUE3 BLUE3 RSVD BLUE4 BLUE4 RSVD BLUE5 BLUE5 NA NA BLUE6 NA H_SYNC NA BLUE7 H_SYNC H_SYNC V_SYNC V_SYNC V_SYNC ENABLE ENABLE ENABLE NA CLOCK NA CLOCK RSVD CLOCK NT7181 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 D0 DS90CF386 T0M 9 48 D1 RxIN0- 100Ω D2 D3 T0P 47 10 46 11 RxIN0+ D4 D6 D27 T1M D5 RxIN1- 100Ω D7 D8 T1P 45 12 42 15 RxIN1+ D9 D12 D13 T2M D14 RxIN2- 100Ω D10 D11 T2P 41 16 38 19 RxIN2+ D15 D18 D19 T3M D20 100Ω D21 D22 T3P 16 D16 18 D17 27 D24 28 D25 30 D26 25 D23 31 CLKIN RxIN3- TCLKM 37 20 40 17 RxIN3+ RxCLKIN- 100Ω TCLKP 39 18 RxCLKIN+ Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application* 13 9 Ordering Information Part No. Package Packing NT7181F 56L TSSOP Tube NT7181FQ 56L TSSOP Tape on reel 14 10 Package Information TSSOP 56L Outline Dimensions unit : inches/mm 15