SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports 19 3 18 4 17 5 6 16 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 1Q 1D 2D 2Q 3Q 3D 4D 4Q 20 1D 1Q OE VCC 8Q 1 SN54LV373A . . . FK PACKAGE (TOP VIEW) 2D 2Q 3Q 3D 4D 19 8Q 18 8D 2 3 17 7D 16 7Q 4 5 15 6Q 14 6D 6 7 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 13 5D 12 5Q 8 9 10 11 8D 7D 7Q 6Q 6D 4Q GND LE 5Q 5D 2 20 LE 1 VCC SN74LV373A . . . RGY PACKAGE (TOP VIEW) SN54LV373A . . . J OR W PACKAGE SN74LV373A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND D OE D Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) GND D D Ioff Supports Partial-Power-Down Mode description/ordering information The ’LV373A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. ORDERING INFORMATION QFN − RGY TOP-SIDE MARKING Reel of 1000 SN74LV373ARGYR Tube of 25 SN74LV373ADW Reel of 2500 SN74LV373ADWR SOP − NS Reel of 2000 SN74LV373ANSR 74LV373A SSOP − DB Reel of 2000 SN74LV373ADBR LV373A Tube of 70 SN74LV373APW Reel of 2000 SN74LV373APWR Reel of 250 SN74LV373APWT TVSOP − DGV Reel of 2000 SN74LV373ADGVR LV373A VFBGA − GQN Reel of 1000 SN74LV373AGQNR LV373A CDIP − J Tube of 20 SNJ54LV373AJ SNJ54LV373AJ CFP − W Tube of 85 SNJ54LV373AW SNJ54LV373AW SOIC − DW −40°C to 85°C TSSOP − PW −55°C −55 C to 125 125°C C ORDERABLE PART NUMBER PACKAGE† TA LV373A LV373A LV373A LCCC − FK Tube of 55 SNJ54LV373AFK SNJ54LV373AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !"# #$# #%&!$# &&"# $ % '()$# $"* & #%&! '"%$# '"& " "&! % "+$ #&!"# $#$& ,$&&$#-* &# '&"#. " # #""$&)- #)" "#. % $)) '$&$!""&* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS407J − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. GQN PACKAGE (TOP VIEW) 1 2 3 terminal assignments 4 1 2 3 4 A A 1Q OE B 2D 7D VCC 1D 8Q B C C 3Q 2Q 6Q 7Q D D 4D 5D 3D 6D E E GND 4Q LE 5Q 8D FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 3 2 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q SCLS407J − APRIL 1998 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS407J − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV373A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL ∆t/∆v VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 2 5.5 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 High or low state 0 3-state 0 UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 Input transition rise or fall rate MAX 1.5 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current MIN 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current SN74LV373A 0 VCC 5.5 VCC × 0.3 5.5 0 0 V V VCC 5.5 V µA VCC = 2 V VCC = 2.3 V to 2.7 V −50 −50 −2 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V −8 −8 −16 −16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 16 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 200 200 100 100 VCC = 4.5 V to 5.5 V 20 20 mA µA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV373A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA VI = VCC or GND, VI or VO = 0 to 5.5 V Ci VI = VCC or GND IO = 0 MIN 3V 2.48 2.48 4.5 V 3.8 TYP MAX UNIT V 3.8 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V ±5 ±5 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 2.9 #%&!$# #"&# '& # " %&!$/" & ".# '$" % "/")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&/" " &. $#." & ##" "" '& , #"* 4 MAX VCC−0.1 2 2 V to 5.5 V IOL = 8 mA IOL = 16 mA ICC Ioff TYP SN74LV373A VCC−0.1 2 2.3 V IOL = 50 µA IOL = 2 mA VI = 5.5 V or GND VO = VCC or GND MIN 2 V to 5.5 V IOH = −8 mA IOH = −16 mA II IOZ VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2.9 V pF SCLS407J − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54LV373A MIN MAX SN74LV373A MIN MAX UNIT tw Pulse duration, LE high 6 6.5 6.5 ns tsu Setup time, data before LE↓ High or low 4.5 5 5 ns th Hold time, data after LE↓ High or low 1.5 1.5 1.5 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ SN54LV373A MIN MAX SN74LV373A MIN MAX UNIT 5 5 5 ns High or low 4 4 4 ns High or low 1 1 1 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu th Pulse duration, LE high SN54LV373A MIN MAX SN74LV373A MIN MAX UNIT 5 5 5 ns Setup time, data before LE↓ High or low 4 4 4 ns Hold time, data after LE↓ High or low 1 1 1 ns switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX temperature SN54LV373A range, SN74LV373A MIN MAX MIN MAX D Q 8.3* 15.2* 1* 17* 1 17 tpd LE Q 9.1* 15.7* 1* 19* 1 19 ten OE Q 8.9* 15.8* 1* 19* 1 19 tdis OE Q 6.2* 12.6* 1* 15* 1 15 D Q 10.4 18 1 21 1 21 tpd LE Q 11.1 18.6 1 22 1 22 ten OE Q 10.9 18.8 1 22 1 22 tdis tsk(o) OE Q 8.3 17.4 1 19 1 19 CL = 15 pF CL = 50 pF 2 UNIT ns ns 2 * On products compliant to MIL-PRF-38535, this parameter is not production tested. #%&!$# #"&# '& # " %&!$/" & ".# '$" % "/")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&/" " &. $#." & ##" "" '& , #"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCLS407J − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX temperature SN54LV373A range, SN74LV373A MIN MAX MIN MAX 13.5 D Q 5.8* 11.4* 1* 13.5* 1 LE Q 6.4* 11* 1* 13* 1 13 ten OE Q 6.3* 11.4* 1* 13.5* 1 13.5 tdis OE Q 4.7* 10* 1* 12* 1 12 D Q 7.3 14.9 1 17 1 17 tpd LE Q 7.8 14.5 1 16.5 1 16.5 ten OE Q 7.7 14.9 1 17 1 17 tdis tsk(o) OE Q 6 13.2 1 15 1 15 tpd CL = 15 pF CL = 50 pF 1.5 UNIT ns ns 1.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) D Q tpd LE Q ten OE Q tdis OE D tpd ten tdis tsk(o) OE Q LOAD CAPACITANCE free-air TA = 25°C MIN TYP MAX temperature SN54LV373A range, SN74LV373A MIN MAX MIN MAX 4.1* 7.2* 1* 8.5* 1 8.5 4.5* 7.2* 1* 8.5* 1 8.5 4.5* 8.1* 1* 9.5* 1 9.5 Q 3.3* 7.2* 1* 8.5* 1 8.5 Q 5.1 9.2 1 10.5 1 10.5 LE Q 5.5 9.2 1 10.5 1 10.5 OE Q 5.5 10.1 1 11.5 1 11.5 4 9.2 1 10.5 1 10.5 CL = 15 pF CL = 50 pF 1 UNIT ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV373A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.6 0.8 V Quiet output, minimum dynamic VOL −0.6 −0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH VIL(D) Low-level dynamic input voltage 2.9 High-level dynamic input voltage V 2.31 V 0.99 V VCC 3.3 V TYP UNIT 5V 19.5 NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS Outputs enabled CL = 50 pF, #%&!$# #"&# '& # " %&!$/" & ".# '$" % "/")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&/" " &. $#." & ##" "" '& , #"* 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 17.4 pF SCLS407J − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC VCC Output Control 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74LV373ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373AGQNR NRND GQN 20 1000 SNPB Level-1-240C-UNLIM SN74LV373ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty Addendum-Page 1 TBD Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Orderable Device Status (1) Package Type Package Drawing SN74LV373APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV373ARGYR ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV373ARGYRG4 ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV373AZQNR ACTIVE ZQN 20 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 19-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV373ADBR DB 20 MLA 330 16 8.2 7.5 2.5 12 16 Q1 SN74LV373ADGVR DGV 20 MLA 330 12 7.0 5.6 1.6 8 12 Q1 SN74LV373ADWR DW 20 MLA 330 24 10.8 13.0 2.7 12 24 Q1 SN74LV373AGQNR GQN 20 HIJ 330 12 3.3 4.3 1.5 8 12 Q1 SN74LV373AGQNR GQN 20 TAI 330 12 3.3 4.3 1.6 8 12 Q1 SN74LV373ANSR NS 20 MLA 330 24 8.2 13.0 2.5 12 24 Q1 SN74LV373APWR PW 20 MLA 330 16 6.95 7.1 1.6 8 16 Q1 SN74LV373ARGYR RGY 20 MLA 180 12 3.8 4.8 1.6 8 12 Q1 SN74LV373AZQNR ZQN 20 HIJ 330 12 3.3 4.3 1.5 8 12 Q1 SN74LV373AZQNR ZQN 20 TAI 330 12 3.3 4.3 1.6 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LV373ADBR DB 20 MLA 342.9 336.6 28.58 SN74LV373ADGVR DGV 20 MLA 338.1 340.5 20.64 31.75 SN74LV373ADWR DW 20 MLA 333.2 333.2 SN74LV373AGQNR GQN 20 HIJ 346.0 346.0 29.0 SN74LV373AGQNR GQN 20 TAI 338.1 340.5 20.64 SN74LV373ANSR NS 20 MLA 333.2 333.2 31.75 SN74LV373APWR PW 20 MLA 342.9 336.6 28.58 SN74LV373ARGYR RGY 20 MLA 190.0 212.7 31.75 SN74LV373AZQNR ZQN 20 HIJ 346.0 346.0 29.0 SN74LV373AZQNR ZQN 20 TAI 338.1 340.5 20.64 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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