SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 D 1.8-V and 5-V Performance D Low Offset (A Grade) D D D D D D D D D D Input Referred Voltage Noise (at 10 kHz) . . . 20 nV//Hz ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) Applications − Cordless/Cellular Phones − Consumer Electronics (Laptops, PDAs) − Audio Pre-Amp for Voice − Portable/Battery-Powered Electronic Equipment − Supply Current Monitoring − Battery Monitoring − Buffers − Filters − Drivers D − 1.25 mV Max (255C) − 1.7 mV Max (−405C to 1255C) Rail-to-Rail Output Swing Wide Common-Mode Input Voltage Range . . . −0.2 V to (V+ − 0.5 V) Input Bias Current . . . 1 pA (Typ) Input Offset Voltage . . . 0.3 mV (Typ) Low Supply Current . . . 70 µA/Channel Low Shutdown Current . . . 10 pA (Typ) Per Channel Gain Bandwidth . . . 2.3 MHz (Typ) Slew Rate . . . 0.9 V/µs (Typ) Turn-On Time From Shutdown . . . 5 µs (Typ) D TLV341 DBV (SOT-23) OR DCK (SC-70) PACKAGE (TOP VIEW) IN+ GND IN− 1 6 2 5 3 4 V+ SHDN OUT TLV342 D (SOIC) OR DGK (MSOP) PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ GND 1 8 2 7 3 6 4 5 TLV341 DRL (SOT-563) PACKAGE (TOP VIEW) V+ 2OUT 2IN− 2IN+ GND IN+ IN− TLV342 RUG (QFN) PACKAGE (TOP VIEW) 1 6 2 5 3 4 V+ SHDN OUT TLV342S RUG (QFN) PACKAGE (TOP VIEW) 1IN− 1IN+ 1 GND 10 1IN− 10 9 1OUT 1IN+ 1 2 8 NC GND 2 8 NC NC 3 7 V+ SHDN 3 7 V+ 2IN+ 4 2IN+ 4 5 6 2OUT 2IN− 5 9 1OUT 6 2OUT 2IN− NC − No internal connection NC − No internal connection TLV344 D (SOIC) OR PW (TSSOP) PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ V+ 2IN+ 2IN− 2OUT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2007, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 description/ordering information The TLV341, TLV342, and TLV344 are single, dual, and quad CMOS operational amplifiers, respectively, with low-voltage, low-power, and rail-to-rail output swing capabilities. The PMOS input stage offers an ultra-low input bias current of 1 pA (typ) and an offset voltage of 0.3 mV (typ). For applications requiring excellent dc precision, the A grade (TLV34xA) has a low offset voltage of 1.25 mV (max) at 25°C. These single-supply amplifiers are designed specifically for ultra-low-voltage (1.5-V to 5-V) operation, with a common-mode input voltage range that typically extends from −0.2 V to 0.5 V from the positive supply rail. Additional features include 20-nV/√Hz voltage noise at 10 kHz, 2.3-MHz unity-gain bandwidth, and 0.9-V/µs slew rate. The TLV341 (single) and TLV342 (dual) in the RUG package also offer a shutdown (SHDN) pin that can be used to disable the device. In shutdown mode, the supply current is reduced to 45 pA (typ). Offered in both the SOT-23 and smaller SC-70 packages, the TLV341 is suitable for the most space-constrained applications. The dual TLV342 is offered in the standard SOIC, MSOP, and QFN packages. An extended industrial temperature range from −40°C to 125°C makes the TLV34x suitable in a wide variety of commercial and industrial applications. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 ORDERING INFORMATION† TA MAX VIO (255C) SOT-23 – DBV Single SC-70 – DCK SOT-563 – DRL QFN – RUG Standard grade: 4 mV Dual SOIC – D MSOP/VSSOP – DGK SOIC – D Quad −40°C −40 C to 125 125°C C TSSOP – PW SOT-23 – DBV Single SC-70 – DCK SOIC – D A grade: 1.25 mV ORDERABLE PART NUMBER PACKAGE‡ Dual MSOP/VSSOP – DGK SOIC – D Quad TSSOP – PW TOP-SIDE MARKING§ Reel of 3000 TLV341IDBVR Reel of 250 TLV341IDBVT Reel of 3000 TLV341IDCKR Reel of 250 TLV341IDCKT Reel of 4000 TLV341IDRLR Y4_ Reel of 3000 TLV342IRUGR Y6E Reel of 3000 TLV342SIRUGR 2YE Tube of 75 TLV342ID Reel of 2500 TLV342IDR Reel of 2500 TLV342IDGKR Reel of 250 TLV342IDGKT Tube of 50 TLV344ID Reel of 2500 TLV344IDR Tube of 90 TLV344IPWR Reel of 2000 TLV344IPWR Reel of 3000 TLV341AIDBVR Reel of 250 TLV341AIDBVT Reel of 3000 TLV341AIDCKR Reel of 250 TLV341AIDCKT Tube of 75 TLV342AID Reel of 2500 TLV342AIDR Reel of 2500 TLV342AIDGKR Reel of 250 TLV342AIDGKT Tube of 50 TLV344AID Reel of 2500 TLV344AIDR Tube of 90 TLV344AIPWR Reel of 2000 TLV344AIPWR YC9_ Y4_ TY342 PREVIEW PREVIEW PREVIEW YCG_ Y5_ TY342A PREVIEW PREVIEW PREVIEW † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. § DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 symbol (each amplifier) V+ V+ − VO − VI + + C = 200 pF Sample Clock absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5 V Input voltage range, VI (either input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 5.5 V Package thermal impedance, θJA (see Notes 3 and 4): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97°C/W D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86°C/W DBV package . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W DGK package . . . . . . . . . . . . . . . . . . . . . . . . 172°C/W DRL package . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W RUG package . . . . . . . . . . . . . . . . . . . . . . . . 243°C/W Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values (except differential voltages and V+ specified for the measurement of IOS) are with respect to the network GND. 2. Differential voltages are at IN+ with respect to IN−. 3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability. 4. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions V+ TA MIN MAX Supply voltage (single-supply operation) 1.5 5.5 UNIT V Operating free-air temperature −40 125 °C ESD protection TEST CONDITIONS Human-Body Model Machine Model 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT 2000 V 200 V SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 electrical characteristics, V+ = 1.8 V, GND = 0, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted) PARAMETER TEST CONDITIONS TA 25°C Standard grade VIO IO 0.3 0.3 1.25 0°C to 125°C 0.3 1.5 −40°C to 125°C 0.3 1.7 Full range 1.9 Average temperature coefficient of input offset voltage IIO 1 375 3000 6.6 25°C 60 CMRR Common-mode rejection ratio 0 ≤ VICR ≤ 1.2 V Full range 50 75 Supply-voltage rejection ratio 1.8 V ≤ V+ ≤ 5 V 25°C kSVR Full range 65 VICR Common-mode input voltage range CMRR ≥ 60 dB 25°C 0 25°C 70 Full range 60 25°C 65 Full range 55 AV Large-signal voltage gain (see Note 5) RL = 10 kΩ to 1.35 V RL = 2 kΩ to 1.35 V 25°C Low level RL = 2 kΩ to 0.9 V Output swing (delta from supply rails) RL = 10 kΩ to 0.9 V 95 dB 1.2 V 110 dB 100 50 75 25 Full range 50 75 14 Full range 20 mV 25 25°C High level fA dB 22 25°C Low level pA 85 Full range 25°C High level VO 100 −40°C to 85°C 25°C mV mV/°C −40°C to 125°C Input offset current UNIT 4 25°C Input offset voltage Input bias current MAX 4.5 25°C IIB TYP† Full range A grade aV MIN 7 Full range 20 25 25°C 70 150 A mA ICC Supply current (per channel) IOS Output short-circuit current SR Slew rate RL = 10 kΩ, Note 6 25°C 0.9 V/ms GBW Unity-gain bandwidth RL = 100 kΩ, CL = 200 pF 25°C 2.2 MHz Fm Gm Phase margin RL = 100 kΩ, CL = 20 pF 25°C 55 ° Gain margin RL = 100 kΩ, CL = 20 pF 25°C 15 dB Vn In Equivalent input noise voltage f = 1 kHz 25°C 33 nV/√Hz Equivalent input noise current f = 1 kHz 25°C 0.001 pA/√Hz THD Total harmonic distortion f = 1 kHz, AV = 1, RL = 600 Ω, VI = 1 VPP 25°C 0.015 % Full range Sourcing 25°C Sinking 200 6 12 10 20 mA † Typical values represent the most likely parametric norm. NOTES: 5. GND + 0.2 V ≤ VO ≤ VCC+ − 0.2 V 6. Connected as voltage follower with 1.1-VPP step input. Number specified is the slower of the positive and negative slew rates. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 shutdown characteristics, V+ = 1.8 V, GND = 0, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted) PARAMETER TEST CONDITIONS ICC(SHDN) Supply current in shutdown mode (per channel) t(on) Amplifier turn-on time VSD Shutdown pin voltage range VSD = 0 V TA 25°C 0.01 25°C Shutdown mode POST OFFICE BOX 655303 TYP Full range ON mode 6 MIN • DALLAS, TEXAS 75265 25°C MAX UNIT 1 mA 1.5 mA ms 5 1.5 1.8 0 0.5 V SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 electrical characteristics, V+ = 5 V, GND = 0, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted) PARAMETER TEST CONDITIONS Standard grade VIO IO MIN 0.3 Input offset voltage Average temperature coefficient of input offset voltage IIO Input bias current Input offset current 0.3 1.25 0°C to 125°C 0.3 1.5 −40°C to 125°C 0.3 1.7 Full range 1.9 1 375 3000 6.6 75 0 ≤ VICR ≤ 4.4 V Full range 70 75 Supply-voltage rejection ratio 1.8 V ≤ V+ ≤ 5 V 25°C kSVR Full range 65 VICR Common-mode input voltage range CMRR ≥ 70 dB 25°C 0 −0.2 to 4.5 25°C 80 110 Full range 70 25°C 75 Full range 60 RL = 2 kΩ to 2.5 V 25°C Low level RL = 2 kΩ to 2.5 V VO RL = 10 kΩ to 2.5 V dB 4.4 V dB 105 60 85 25 Full range 60 85 18 Full range 30 mV 40 25°C High level 95 40 25°C Low level fA dB Full range 25°C High level Output swing (delta from supply voltage) pA 90 Common-mode rejection ratio Large-signal voltage gain (see Note 5) 200 −40°C to 85°C 25°C mV mV/°C −40°C to 125°C CMRR AV UNIT 4 25°C 25°C RL = 10 kΩ to 2.5 V MAX 4.5 25°C IIB TYP† Full range A grade aV TA 25°C 7 Full range 15 20 25°C 75 150 A mA ICC Supply current (per channel) IOS Output short-circuit current SR Slew rate RL = 10 kΩ, Note 6 25°C 1 V/ms GBW Unity-gain bandwidth RL = 10 kΩ, CL = 200 pF 25°C 2.3 MHz Fm Gm Phase margin RL = 100 kΩ, CL = 20 pF 25°C 55 ° Gain margin RL = 100 kΩ, CL = 20 pF 25°C 15 dB Vn In Equivalent input noise voltage f = 1 kHz 25°C 33 nV/√Hz Equivalent input noise current f = 1 kHz 25°C 0.001 pA/√Hz THD Total harmonic distortion f = 1 kHz, AV = 1, RL = 600 Ω, VI = 1 VPP 25°C 0.012 % Full range Sourcing 25°C Sinking 200 60 113 80 115 mA † Typical values represent the most likely parametric norm. NOTES: 5. GND + 0.2 V ≤ VO ≤ VCC+ − 0.2 V 6. Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 shutdown characteristics, V+ = 5 V, GND = 0, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted) PARAMETER TEST CONDITIONS ICC(SHDN) Supply current in shutdown mode (per channel) t(on) Amplifier turn-on time VSD Shutdown pin voltage range VSD = 0 V TA 25°C 0.01 Shutdown mode • DALLAS, TEXAS 75265 25°C MAX 1 1.5 25°C POST OFFICE BOX 655303 TYP Full range ON mode 8 MIN UNIT A mA ms 5 4.5 5 0 0.8 V SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS INPUT BIAS CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 130 1,000 V+ = 5 V 110 IIB − Input Bias Current − pA ICC − Supply Current − µA 120 125°C 100 90 85°C 80 25°C 70 60 −40°C 50 100 10 1 40 30 1.5 2 2.5 3 3.5 4 4.5 0.1 −40 −20 5 VCC − Supply Voltage − V 0 20 40 60 80 100 120 TA − Free-Air Temperature − °C Figure 2 Figure 1 OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE 35 7 RL = 2 kΩ VO − Output Swing From Supply Voltage − mV VO − Output Swing From Supply Voltage − mV OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE 30 Negative Swing 25 20 Positive Swing 15 10 1.5 2 140 2.5 3 3.5 4 4.5 5 RL = 10 kΩ 6.5 6 Negative Swing 5.5 5 4.5 4 Positive Swing 3.5 3 1.5 2 VCC − Supply Voltage − V 2.5 3 3.5 4 4.5 5 VCC − Supply Voltage − V Figure 3 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS SOURCE CURRENT vs OUTPUT VOLTAGE SOURCE CURRENT vs OUTPUT VOLTAGE 1000 1000 V+ = 2.7 V V+ = 5 V −40°C 100 −40°C IS − Source Current − mA IS − Source Current − mA 100 25°C 10 85°C 1 125°C 10 25°C 85°C 1 125°C 0.1 0.1 0.01 0.001 0.01 0.1 1 0.01 0.001 10 VO − Output Voltage Referenced to V+ (V) 0.01 Figure 5 V+ = 5 V 100 100 −40°C −40°C IS − Sink Current − mA IS − Sink Current − mA 1000 10 25°C 85°C 1 125°C 0.1 10 25°C 85°C 1 125°C 0.1 0.01 0.1 1 10 VO − Output Voltage Referenced to V− (V) 0.01 0.001 0.01 0.1 Figure 8 POST OFFICE BOX 655303 1 VO − Output Voltage Referenced to V− (V) Figure 7 10 10 SINK CURRENT vs OUTPUT VOLTAGE V+ = 2.7 V 0.01 0.001 1 Figure 6 SINK CURRENT vs OUTPUT VOLTAGE 1000 0.1 VO − Output Voltage Referenced to V+ (V) • DALLAS, TEXAS 75265 10 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS OFFSET VOLTAGE vs COMMON-MODE VOLTAGE OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 1 1 V+ = 5 V 0.5 0.5 0 0 VIO − Offset Voltage − mV VIO − Offset Voltage − mV V+ = 2.7 V −0.5 −1 125°C −1.5 85°C −2 25°C −0.5 −1 125°C 85°C −1.5 25°C −2 −40°C −40°C −2.5 −2.5 −3 −0.2 0.8 1.8 −3 −0.2 2.8 VIC − Common-Mode Voltage − V 0.8 1.8 2.8 3.8 Figure 9 INPUT VOLTAGE vs OUTPUT VOLTAGE 300 300 V+ /GND = ±1.35 V V+ /GND = ±2.5 V VI − Input Voltage − µV 200 VI − Input Voltage − µV 5.8 Figure 10 INPUT VOLTAGE vs OUTPUT VOLTAGE RL = 2 kΩ 100 0 RL = 10 kΩ 200 0 −100 −200 −200 −2 −1 0 1 VO − Output Voltage − V 2 3 RL = 2 kΩ 100 −100 −300 −3 4.8 VIC − Common-Mode Voltage − V −300 −1.5 RL = 10 kΩ −1 −0.5 0 0.5 1 1.5 VO − Output Voltage − V Figure 11 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS SLEW RATE vs TEMPERATURE SLEW RATE vs SUPPLY VOLTAGE 2.5 1.9 2.3 Falling Edge 1.7 SR − Slew Rate − V/µs 2.1 SR − Slew Rate − V/µs 1.5 1.3 Rising Edge 1.1 0.9 0.5 1.5 2 1.9 Falling Edge 1.7 1.5 1.3 Rising Edge 1.1 0.9 RL = 10 kΩ AV = 1 VI = 0.8 VPP for V+ < 2.7 V VI = 2 VPP for V+ > 2.7 V 0.7 RL = 10 kΩ AV = 1 VI = 2 VPP V+ = 2.7 V 0.7 2.5 3 3.5 4 VCC − Supply Voltage − V 4.5 0.5 −40 −20 5 0 20 40 60 80 100 120 140 VCC − Supply Voltage − V Figure 14 Figure 13 CMRR vs FREQUENCY SLEW RATE vs TEMPERATURE 100 2.5 2.3 1.9 90 70 Falling Edge 1.7 1.5 1.3 Rising Edge 60 50 30 0.9 20 0.7 10 0 20 40 60 80 100 120 140 VCC − Supply Voltage − V 2.7 V 40 1.1 0.5 −40 −20 5V 80 Gain − dB SR − Slew Rate − V/µs 2.1 RL = 10 kΩ AV = 1 VI = 2 VPP V+ = 5 V VI = V+ /2 RL = 5 kΩ 0 100 Figure 15 12 1K 10K 100K f − Frequency − Hz Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1M SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS INPUT VOLTAGE NOISE vs FREQUENCY PSRR vs FREQUENCY 100 220 +PSRR (2.7 V) 200 90 VI − Input Voltage Noise − nV/ Hz −PSRR (2.7 V) 80 Gain − dB 70 60 −PSRR (5 V) +PSRR (5 V) 50 40 30 20 10 0 100 180 160 140 120 100 80 5V 2.7 V 60 40 20 RL = 5 kΩ 0 1K 10K 100K f − Frequency − Hz 1M 10M 10 100 Figure 17 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE 10 RL = 600 Ω VO = 1 VPP for V+ = 2.7 V VO = 2.5 VPP for V+ = 5 V THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10K Figure 18 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 1K f − Frequency − Hz 1 5V AV = 10 2.7 V AV = 10 0.1 2.7 V AV = 1 0.01 5V AV = 1 0.001 0.0001 10 100 1K 10K f − Frequency − Hz 100K f = 10 kHz RL = 600 Ω 5V AV = 10 1 2.7 V AV = 10 0.1 5V AV = 1 0.01 0.001 2.7 V AV = 1 0.01 0.1 1 VO − Output Voltage − VPP 10 Figure 20 Figure 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS FREQUENCY RESPONSE vs TEMPERATURE 160 140 V+ = 5 V RL = 2 kΩ Phase 120 140 100 Gain − dB 80 −40°C Gain 60 80 −40°C 25°C 60 40 125°C 20 −20 40 25°C 125°C 0 Phase Margin − Deg 120 100 20 0 1 10 100 1K 10K f − Frequency − kHz Figure 21 FREQUENCY RESPONSE vs RL 140 120 140 Phase 120 100 80 RL = 600 Ω 60 RL = 2 kΩ Gain RL = 100 kΩ 80 60 40 RL = 100 kΩ 40 20 RL = 600 Ω RL = 2 kΩ 0 20 0 −20 1 10 100 f − Frequency − kHz Figure 22 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1K 10K Phase Margin − Deg 100 Gain − dB 160 V+ = 2.7 V Closed-Loop Gain = 60 dB SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS FREQUENCY RESPONSE vs RL 140 120 160 V+ = 5 V Closed-Loop Gain = 60 dB Phase 140 Gain − dB 100 80 RL = 600 Ω Gain 60 80 RL = 2 kΩ RL = 100 kΩ 60 40 RL = 100 kΩ 20 40 RL = 2 kΩ RL = 600 Ω 0 −20 Phase Margin − Deg 120 100 20 0 1 10 100 f − Frequency − kHz 1K 10K Figure 23 FREQUENCY RESPONSE vs CL 140 120 100 Phase V+ = 5 V RL = 600 Ω Closed-Loop Gain = 60 dB CL = 0 pF 100 80 Gain − dB 80 40 CL = 500 pF Gain CL = 1000 pF 60 20 0 40 CL = 0 pF 20 −40 0 CL = 500 pF −20 CL = 1000 pF −40 −20 Phase Margin − Deg 60 CL = 100 pF 1 10 100 f − Frequency − kHz 1K −60 CL = 100 pF 10K −80 Figure 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS LARGE-SIGNAL NONINVERTING RESPONSE SMALL-SIGNAL NONINVERTING RESPONSE Input Input TA = −40°C RL = 2 kΩ V+/GND = ±2.5 V −0.05 −0.1 0.05 −0.15 0 −0.2 −0.05 5 1 4 0 −1 3 2 TA = −40°C RL = 2 kΩ V+/GND = ±2.5 V 1 −3 0 −4 −5 −1 Output −0.1 4 µs/div" Output −2 −0.25 4 µs/div" LARGE-SIGNAL NONINVERTING RESPONSE SMALL-SIGNAL NONINVERTING RESPONSE 0.1 Input TA = 25°C RL = 2 kΩ V+/GND = ±2.5 V −0.05 −0.1 0.05 −0.15 0 −0.2 −0.05 VO − Output Voltage − V 0 VI − Input Voltage − V VO − Output Voltage − V 5 1 4 0 0.05 0.15 3 2 −1 TA = 25°C RL = 2 kΩ V+/GND = ±2.5 V 1 −3 0 −4 −1 4 µs/div" −0.25 −2 Figure 27 16 −2 −5 Output Output −0.1 2 6 Input 0.2 0.1 −6 Figure 26 Figure 25 0.25 −2 4 µs/div" Figure 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −6 VI − Input Voltage − V 0.1 VO − Output Voltage − V VO − Output Voltage − V 0 0.15 VI − Input Voltage − V 0.05 0.2 VI − Input Voltage − V 0.25 2 6 0.1 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS LARGE-SIGNAL NONINVERTING RESPONSE SMALL-SIGNAL NONINVERTING RESPONSE Input TA = 125°C RL = 2 kΩ V+/GND = ±2.5 V −0.05 −0.1 0.05 −0.15 0 −0.2 −0.05 VO − Output Voltage − V 5 1 4 0 −1 3 2 TA = 125°C RL = 2 kΩ V+/GND = ±2.5 V 1 −3 0 −4 −5 −1 Output Output −0.1 −0.25 4 µs/div" −2 4 µs/div" SMALL-SIGNAL INVERTING RESPONSE LARGE-SIGNAL INVERTING RESPONSE 0.1 6 0.05 5 1 4 0 2 Input 0.1 0.05 TA = −40°C RL = 2 kΩ V+/GND = ±2.5 V −0.05 −0.1 −0.15 0 −0.2 −0.05 VO − Output Voltage − V VO − Output Voltage − V 0 0.15 VI − Input Voltage − V Input 0.2 3 2 −1 TA = −40°C RL = 2 kΩ V+/GND = ±2.5 V 4 µs/div" −0.25 −2 1 −3 0 −4 −1 Output −0.1 −6 Figure 30 Figure 29 0.25 −2 VI − Input Voltage − V VO − Output Voltage − V 0 0.15 VI − Input Voltage − V 0.05 VI − Input Voltage − V Input 0.2 0.1 2 6 0.1 0.25 −5 Output −2 4 µs/div" −6 Figure 32 Figure 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SLVS568C − JANUARY 2005 − REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS LARGE-SIGNAL INVERTING RESPONSE SMALL-SIGNAL INVERTING RESPONSE 0.25 2 0.1 6 0.05 5 1 4 0 TA = 25°C RL = 2 kΩ V+/GND = ±2.5 V −0.05 −0.1 0.05 −0.15 0 −0.2 −0.05 VO − Output Voltage − V −1 3 2 TA = 25°C RL = 2 kΩ V+/GND = ±2.5 V 1 −3 0 −4 −5 −1 Output −0.1 Output −0.25 4 µs/div" −2 4 µs/div" LARGE-SIGNAL INVERTING RESPONSE SMALL-SIGNAL INVERTING RESPONSE Input Input TA = 125°C RL = 2 kΩ V+/GND = ±2.5 V −0.05 −0.1 0.05 −0.15 0 −0.2 −0.05 VO − Output Voltage − V VO − Output Voltage − V 0 VI − Input Voltage − V 0.05 0.15 5 1 4 0 −1 3 2 TA = 125°C RL = 2 kΩ V+/GND = ±2.5 V 1 −3 0 −4 −5 −1 −0.25 −6 −2 4 µs/div" 4 µs/div" Figure 36 Figure 35 18 −2 Output Output −0.1 2 6 0.1 0.2 0.1 −6 Figure 34 Figure 33 0.25 −2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VI − Input Voltage − V 0.1 VI − Input Voltage − V VO − Output Voltage − V 0 0.15 VI − Input Voltage − V Input Input 0.2 PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV341AIDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDCKT ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341AIDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDCKT ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV341IDRLR ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV341IDRLRG4 ACTIVE SOT DRL 6 TLV342AID ACTIVE SOIC D 8 75 TLV342AIDE4 ACTIVE SOIC D 8 TLV342AIDG4 ACTIVE SOIC D 8 TLV342AIDR ACTIVE SOIC D TLV342AIDRE4 ACTIVE SOIC TLV342AIDRG4 ACTIVE TLV342ID 4000 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV342IRUGR ACTIVE QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2007 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV341AIDBVR DBV 6 SITE 48 179 8 3.2 3.2 1.4 4 8 Q3 TLV341AIDBVT DBV 6 SITE 48 179 8 3.2 3.2 1.4 4 8 Q3 TLV341AIDCKR DCK 6 SITE 48 179 8 2.2 2.5 1.2 4 8 Q3 TLV341AIDCKT DCK 6 SITE 48 179 8 2.2 2.5 1.2 4 8 Q3 TLV341IDBVR DBV 6 SITE 48 179 8 3.2 3.2 1.4 4 8 Q3 TLV341IDBVT DBV 6 SITE 48 179 8 3.2 3.2 1.4 4 8 Q3 TLV341IDCKR DCK 6 SITE 48 179 8 2.2 2.5 1.2 4 8 Q3 TLV341IDCKT DCK 6 SITE 48 179 8 2.2 2.5 1.2 4 8 Q3 TLV341IDRLR DRL 6 SITE 35 180 9 1.78 1.78 0.69 4 8 Q3 TLV342AIDR D 8 SITE 27 330 12 6.4 5.2 2.1 8 12 Q1 TLV342IDGKR DGK 8 SITE 35 330 13 5.3 3.4 1.4 8 12 Q1 TLV342IDR D 8 SITE 27 330 12 6.4 5.2 2.1 8 12 Q1 TLV342IRUGR RUG 10 SITE 48 179 8 1.75 2.25 0.65 4 8 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TLV341AIDBVR DBV 6 SITE 48 220.0 205.0 50.0 TLV341AIDBVT DBV 6 SITE 48 220.0 205.0 50.0 TLV341AIDCKR DCK 6 SITE 48 220.0 205.0 50.0 TLV341AIDCKT DCK 6 SITE 48 220.0 205.0 50.0 TLV341IDBVR DBV 6 SITE 48 220.0 205.0 50.0 TLV341IDBVT DBV 6 SITE 48 220.0 205.0 50.0 TLV341IDCKR DCK 6 SITE 48 220.0 205.0 50.0 TLV341IDCKT DCK 6 SITE 48 220.0 205.0 50.0 TLV341IDRLR DRL 6 SITE 35 202.0 201.0 28.0 20.64 TLV342AIDR D 8 SITE 27 342.9 336.6 TLV342IDGKR DGK 8 SITE 35 358.0 335.0 35.0 TLV342IDR D 8 SITE 27 342.9 336.6 20.64 TLV342IRUGR RUG 10 SITE 48 220.0 205.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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