CS1501
Digital Power Factor Correction Control IC
Features & Description
Overview
Digital EMI Noise Shaping
The CS1501 is a high-performance digital power factor
correction (PFC) controller designed for switching mode power
supply (SMPS) applications. The CS1501 actively manages
the power factor correction while achieving high efficiency over
a wide load range.
Adaptive Digital Energy Controller
• Excellent Efficiency Under All Load and Line Conditions
• Zero-voltage Switching Topology
Minimal External Devices Required
The CS1501 adaptively controls the input AC current so that it
is in phase with the AC mains voltage and its waveform mimics
the input voltage waveform. The PFC controller executes
adaptive digital algorithms designed to shape the AC mains
input current waveform to be in phase with the input voltage
waveform.
Adaptive Digital Control Loop
Comprehensive Safety Features
• Undervoltage Lockout (UVLO)
• Output Overvoltage Protection
• Cycle-by-cycle Current Limiting
• Open/Short Loop Protection for IAC & IFB Pins
• Thermal Shutdown
Pin placement similar to traditional boundary mode (CRM)
Controllers
The CS1501 is equipped with a zero-current detection (ZCD)
circuit providing the PFC digital controller the capability to turn
on the MOSFET when the voltage across the drain and source
is near zero. Additionally, a current-sensing circuit is
incorporated for instantaneous overcurrent protection.
Ordering Information
Applications & Description
See page 15.
LCD and LED TVs
Notebooks
Server/Telecom
BR1
D1
LB
Vrect
BR1
VDD
R1
Vlink
R5
R6
R2
AC
Mains
R3
5 ZCD
C1
3
BR 1
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
CS1501
IAC
CS
2
R4
1
IFB
GD
STBY
BR 1
8
VDD
7
Q1
4
C2
Regulated
DC Output
GND
6
R7
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
JUN ’11
DS927PP6
CS1501
1. INTRODUCTION
V DD
V DD
Voltage
Regulator
600k
STBY
2
POR
VDD
15k
IFB
-
VDD (on )
VDD (off)
VDD
7
GD
6
GND
5
ZCD
VZ
Iref
24k
1
+
8
ADC
VDD
15k
IAC
Iref
24k
3
ADC
t LEB
CS
4
600
VCS(th)
-
+
+
t ZCB
CS
Threshold
CS Clamp
VCS(clamp ) -
Zero Crossing
Detect
+
-
V ZCD(th)
Figure 1. CS1501 Block Diagram
The CS1501 digital power factor correction (PFC) control IC is
designed to deliver the lowest system cost by reducing the
total number of system components and optimizing the EMI
noise signature, which reduces the conducted EMI filter
requirements. The CS1501 digital algorithm determines the
behavior of the boost converter during startup, normal
operation, and under fault conditions (overvoltage,
overcurrent, and overtemperature).
the PFC active-switching behavior and efficiency. The
auxiliary voltage is normalized using an external attenuator
and is connected to the ZCD pin, providing the CS1501 a
mechanism to detect the valley/zero crossings. The ZCD
comparator looks for the zero crossing on the auxiliary winding
and switches when the auxiliary voltage is below zero.
Switching in the valley of the oscillation minimizes the
switching losses and reduces EMI noise.
Figure 1 illustrates a high-level block diagram of the CS1501.
The PFC processor logic regulates the power transfer by
using an adaptive digital algorithm to optimize the PFC
active-switch (MOSFET) drive signal duty cycle and switching
frequency. The adaptive controller uses independent
analog-to-digital converter (ADC) channels when sensing the
feedback and feedforward analog signals required to
implement the digital PFC control algorithm.
The PFC controller uses a current sensor for overcurrent
protection. The boost inductor peak current is measured
across an external resistor in the switching circuit on a
cycle-by-cycle basis. An overcurrent fault is generated when
the sense voltage applied to the CS pin exceeds a predefined
reference voltage.
The AC mains rectified voltage (on pin IAC) and PFC output
link voltage (on pin IFB) are transformed by the PFC
processor logic and used to generate the optimum PFC
active-switch drive signal (GD) by calculating the optimal
switching frequency and tON time on a cycle-by-cycle basis.
An auxiliary winding is typically added to the PFC boost
inductor to provide zero-current detection (ZCD) information.
The ZCD acts as a demagnetization sensor used to monitor
2
The CS1501 includes a supervisor & protection circuit to
manage startup, shutdown, and fault conditions. The
protection circuit is designed to prevent output overvoltage as
a result of load and AC mains transients. The PFC power
converter main rectified voltage (Vrect) and output link voltage
(Vlink) are monitored for overvoltage faults which would lead to
shutdown of the PFC controller. The PFC overvoltage
protection is designed for auto-recovery, i.e. operation resumes
once the fault clears.
DS927PP6
CS1501
2. PIN DESCRIPTION
Link V oltage S ens e
IFB
S tandby
S TBY
Rec tifier V oltage S ens e
IAC
P FC Current S ens e
CS
1
2
3
4
8
7
6
5
V DD
IC S upply V oltage
GD
P FC Gate Driv er
GND
Ground
ZCD
P FC Zero-c urrent Detec t
8-lead S OIC
Figure 2. CS1501 Pin Assignments
Pin Name
Pin #
I/O
IFB
1
IN
Link Voltage Sense — A current proportional to the output link voltage of the PFC is
input into this pin. The current is measured with an ADC.
STBY
2
IN
Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state.
The input has an internal 600k pull-up resistor to the VDD pin.
IAC
3
IN
Rectifier Voltage Sense — A current proportional to the rectified line voltage is input
into this pin. The current is measured with an ADC.
CS
4
IN
PFC Current Sense — The current flowing in the PFC MOSFET is sensed through a
resistor. The resulting voltage is applied to this pin and digitized for use by the PFC
computational logic to limit the maximum current through the power FET.
ZCD
5
IN
Zero-current Detect — Boost Inductor demagnetization sensing input for zero-current
detection (ZCD) information. The pin is externally connected to the PFC boost inductor
auxiliary winding through an external resistor divider.
GND
6
PWR
Ground — Common reference. Current return for both the input signal portion of the IC
and the gate driver.
GD
7
OUT
PFC Gate Driver — The totem pole stage is able to drive the power MOSFET with a
peak current of 0.5A source and 1.0A sink.
PWR
IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the
gate driver. A storage capacitor is connected on this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. This
pin is clamped to a maximum voltage (Vz) by an internal zener function.
VDD
DS927PP6
8
Description
3
CS1501
3. CHARACTERISTICS AND SPECIFICATIONS
3.1
Electrical Characteristics
Typical characteristics conditions:
Minimum/Maximum characteristics conditions:
TJ = -40° to +125°C, VDD = 10V to 15V, GND = 0V
TA = 25°C, VDD = 13V, GND = 0V
All voltages are measured with respect to GND.
Unless otherwise specified, all current are positive when
flowing into the IC.
Parameter
Condition
Symbol
Min
Typ
Max
Unit
VDD Supply Voltage
After Turn-on
VDD
7.9
-
17.0
V
Turn-on Threshold Voltage
Operating Range
VDD Increasing
VDD(on)
9.8
10.2
10.5
V
Turn-off Threshold Voltage (UVLO)
VDD Decreasing
VDD(off)
7.9
8.1
8.3
V
UVLO Hysteresis
Zener Voltage
VHys
-
2.1
-
V
IDD = 20mA
VZ
17.0
17.9
18.7
V
VDD = VDD(on)
IST
-
68
80
A
CL = 1nF, fsw = 70kHz
IDD
-
1.5
1.7
mA
STBY < 0.8V
ISB
-
80
112
A
Iref
-
129
-
A
VDD Supply Current
Startup Supply Current
Operating Supply
Current 3
Standby Supply Current
Reference
Reference Current
PFC Gate Drive
Output Source Resistance
IGD = 100mA, VDD = 13V
ROH
-
9
-
Output Sink Resistance
IGD = -200mA, VDD = 13V
ROL
-
6
-
CL = 1nF, VDD = 13V
tr
-
32
45
ns
CL = 1nF, VDD = 13V
tf
-
15
25
ns
Output Voltage Low State
IGD = -200mA, VDD = 13V
Vol
-
0.9
1.3
V
Output Voltage High State
IGD = 100mA, VDD = 13V
Voh
11.3
11.8
-
V
VZCD(th)
-
50
-
mV
tZCB
-
200
-
ns
VZCD = 50mV
IZCD
-2
-1
2
mA
IZCD = 1mA
VCLP
-
VDD
-
V
IFB Current at Startup Mode
IIFB(startup)
-
116
-
A
IFB Current at Normal Mode
IIFB(norm)
-
129
-
A
Rise
Time 3
Fall Time 3
Zero-current Detection (ZCD)
ZCD Threshold
ZCD Blanking
ZCD Sink/Source Current
Upper Voltage Clamp
Overvoltage Protection (OVP)
OVP Threshold
Iref = 129A
IOVP
-
136
-
A
OVP Hysteresis
Iref = 129A
IOVP(Hy)
-
2
-
A
VCS(clamp)
-
1.0
-
V
Overcurrent Protection (OCP)
Current Sense Reference Clamp
Threshold on Current Sense
VCS(th)
-
0.5
-
V
Leading Edge Blanking
tLEB
-
300
-
ns
Delay to Output
tCS
-
60
350
ns
4
DS927PP6
CS1501
Parameter
Condition
Symbol
Min
Typ
Max
Unit
Input Brownout Protection Threshold
gate drive turns off
IBP(lower)
-
31.6
-
A
Input Brownout Recovery Threshold
gate drive turns on
IBP(upper)
-
39.6
-
A
Thermal Shutdown Threshold
TSD
134
147
159
°C
Thermal Shutdown Hysteresis
TSD(Hy)
-
9
-
°C
Logic Threshold Low
-
-
0.8
V
Logic Threshold High
VDD-0.8
-
-
V
Brownout Protection (BP)
Thermal
Protection 1
STBY Input 2
Notes: 1. Specifications guaranteed by design and are characterized and correlated using statistical process methods.
2.
3.
STBY is designed to be driven by an open collector. The input is internally pulled up with a 600k resistor.
For test purposes, load capacitance (CL) is 1nF and is connected as shown in the following diagram.
V DD
+15V
VDD
GD
CS
GND
DS927PP6
TP
Buffer
S1
R1
CL
1nF
R3
R2
GD OUT
S2
-15V
5
CS1501
3.2 Absolute Maximum Ratings
Pin
Symbol
8
VDD
1,3,4,5
-
1,3,4,5
-
7
VGD
7
Parameter
Value
Unit
VZ
V
Analog Input Maximum Voltage
-0.5 to VZ
V
Analog Input Maximum Current
50
mA
Gate Drive Output Voltage
-0.3 to VZ
V
IGD
Gate Drive Output Current
-1.0 / +0.5
A
-
PD
Total Power Dissipation @ TA = 50 °C
600
mW
-
JA
Junction-to-Ambient Thermal Impedance
107
°C/W
-
TA
Operating Ambient Temperature Range 1
-40 to +125
°C
-
TJ
Junction Temperature Operating Range
-40 to +125
°C
-
TStg
Storage Temperature Range
-65 to +150
°C
All Pins
ESD
2000
200
500
V
IC Supply Voltage
Electrostatic Discharge Capability
Human Body Model
Machine Model
Charged Device Model
Notes: 4. The CS1501 has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation voltage,
is defined in the VDD Supply Voltage section of the Characteristics and Specifications section on the previous page.
5. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power
dissipation at the rate of 50mW/ °C for variation over temperature.
WARNING:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
6
DS927PP6
CS1501
4. TYPICAL ELECTRICAL PERFORMANCE
3.5
2
1.8
Supply Current (mA)
3.
IDD (mA)
2.5
2.
1.5
Rising
1.
Falling
0.5
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0.
0
2
4
6
8
10
12
14
16
fSW(max) = 70kHz
Operating
Start-up
0
18
-50
VDD (V)
0
50
100
150
Temperature (oC)
Figure 4. Supply Current (ISB, IST, IDD) vs. Temp
Figure 3. Supply Current vs. Supply Voltage
11
3
10.5
Turn On
2
VDD (V)
UVLO Hysteresis
10
1
9.5
9
8.5
Turn Off
8
7.5
7
0
-40
0
40
80
-60
120
-10
Temperature (OC)
40
Temperature
Figure 5. UVLO Hysteresis vs. Temp
90
140
(OC)
Figure 6. Turn-on & Turn-off Threshold vs. Temp
0.5%
0.0%
Iref Drift
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-3.0%
-50
0
50
100
150
Temperature (oC)
Figure 7. Reference Current (Iref) Drift vs. Temp
DS927PP6
7
CS1501
106%
14
Vlink (Normalized at 25OC)
12
Zout (Ohm)
Source
10
8
6
VDD = 13 V
Isource = 100 mA
Sink
4
Isink = 200 mA
2
0
-60
-40
-20
0
20
40
60
80
100
120
Gate Resistor (ROH, ROL) Temp (oC)
OVP
104%
102%
100%
Normal
98%
96%
140
-50
0
50
Temperature
Figure 8. Gate Resistance (ROH, ROL) vs. Temp
100
150
(OC)
Figure 9. OVP vs. Temp
19
IDD = 20 mA
VZ (V)
18.5
18
17.5
17
-50
0
50
100
150
Temperature (oC)
Figure 10. VDD Zener Voltage vs. Temp
8
DS927PP6
CS1501
5. GENERAL DESCRIPTION
The CS1501 offers numerous features, options, and
functional capabilities to the designer of switching power
converters. This digital PFC control IC is designed to replace
legacy analog PFC controllers with minimal design effort.
One key feature of the CS1501 is its operating frequency
profile. Figure 11 illustrates how the frequency varies over one
half cycle of the line voltage in steady-state operation. When
power is first applied to the CS1501, it examines the line
voltage and adapts its operating frequency to the line voltage
as shown in Figure 11. The operating frequency is varied from
the peak to the trough of the AC input. During startup, the
control algorithm generates maximum power while operating
in critical conduction mode (CRM), providing an approximate
square-wave current envelop within every half-line cycle.
120
Switching Freq. (% of Max.)
80
60
Line Voltage (% of Max.)
20
0
0
45
90
135
180
Rectified Line Voltage Phase (Deg.)
Figure 11. Switching Frequency vs. Phase Angle
Figure 12 illustrates how the operating frequency (as a
percentage of maximum frequency) changes with output
power and the peak of the line voltage.
Vin < 181 VAC
40
DCM
IAC
t [ms]
Figure 13. DCM and quasi-CRM Operation with CS1501
The zero-current detection (ZCD) of the boost inductor is
achieved using an auxiliary winding. When the stored energy
of the inductor is fully released to the output, the voltage on the
ZCD pin decreases, triggering a new switching cycle. This
quasi-resonant switching allows the active switch to be turned
on with near-zero inductor current, resulting in a nearly
lossless switch event. This minimizes turn-on losses and EMI
noise created by the switching cycle. Power factor correction
control is achieved during light load by using on-time
modulation.
5.2 Startup vs. Normal Operation Mode
The CS1501 has two discrete operation modes: startup and
normal. Startup mode will be activated when Vlink is less than
90% of nominal value, VO(startup) and remains active until Vlink
reaches 100% of nominal value, as shown in Figure 14.
Startup mode is activated during initial system power-up. Any
Vlink drop to less than VO(startup), such as a load change, can
cause the system to enter startup mode until Vlink is brought
back into regulation.
100%
90%
Vin > 147 VAC
20
0
5
20
40
60
80
Normal
Mode
Startup Mode
50
46
Quasi CRM
Vlink
[V]
60
56
Burst Mode
F SW max (kHz)
70
DCM
ILB
Startup Mode
% of Max
100
Quasi CRM
Inductor Current
DCM
5.1 PFC Operation
40
input under full load, the PFC controller will function as a
quasi-CRM controller at the peak of the AC line cycle, as
shown in Figure 13.
Normal
Mode
100
% PO max
t [ms]
Figure 12. Max. Switching Frequency vs. Output Power
Figure 14. Startup and Normal Modes
When PO falls below 5%, the CS1501 changes to Burst Mode.
(Refer to Burst Mode section for more information.)
Startup mode is defined as a surge of current delivering
maximum power to the output regardless of the load. During
every active switch cycle, the 'ON' time is calculated to drive a
constant peak current over the entire line cycle. However, the
'OFF' time is calculated based on the DCM/CCM boundary
equation.
The CS1501 is designed to function as a DCM controller.
However, during peak periods, the controller may interchange
control methods and operate in a quasi-critical-conduction
mode (quasi-CRM) at low line. For example, at 90VAC main
DS927PP6
9
CS1501
5.3 Burst Mode
Burst mode is utilized to improve system efficiency when the
system output power (Po) is <5% of nominal. Burst mode is
implemented by intermittently disabling the PFC over a full
half-line period under light-load conditions, as shown in
Figure 15.
Solving Equation 2 for the PFC boost inductor, LB, gives the
following equation:
2
400V – 90V 2
L B = 90V ------------------------------------------------------------2 70kHz Po 400V
If a value of the boost inductor other than that obtained from
Equation 3 above is used, the total output power capability as
well as the minimum input voltage threshold will differ
according to Equation 2. Note that if the input voltage drops
below 90Vrms and the inductance value is <LB, the link
voltage Vlink will drop below 400V and fall out of regulation.
Po
[W]
Burst Threshold
Burst Mode
Active
L < L B
t [ms]
PFC
Disable
Vin
L = LB
FET
Vgs
Po(max)
Vin
[V]
[Eq.3]
L > LB
t [ms]
Figure 15. Burst Mode
90
5.4 Output Power and PFC Boost Inductor
In normal operating mode, the nominal output power is
estimated by the following equation.
V link – V in min 2
Po = V in min --------------------------------------------------------2 f max L B V link
2
[Eq.1]
where:
265
VAC(rms)
Figure 16. Relative Effects of Varying Boost Inductance
5.5 PFC Output Capacitor
The value of the PFC output capacitor should be chosen
based upon voltage ripple and hold-up requirements. To
ensure system stability with the digital controller, the
recommended value of the capacitor is within the range of
0.5F/watt to 2.0F/watt with a Vlink voltage of 400V.
Po
rated output power of the system
5.6 Output IFB Sense & Input IAC Sense
efficiency of the boost converter (estimated as 100%
by the PFC algorithm)
A current proportional to the PFC output voltage, Vlink, is
supplied to the IC on pin IFB and is used as a feedback control
signal. This current is compared against an internal
fixed-value reference current.
Vin(min) minimum RMS line voltage is 90V, measured after
the rectifier and EMI filter
nominal PFC output voltage (must be 400V)
Vlink
fmax
maximum switching frequency is 70kHz
LB
boost inductor specified by rated power requirement
<1
margin factor to guarantee rated output power (Po)
against boost inductor tolerances.
Equation 1 is provided for explanation purposes only. Using
substituted required design values for Vlink and fmax gives the
following equation:
The ADC is used to measure the magnitude of the IIFB current
through resistor RIFB. The magnitude of the IIFB current is then
compared to an internal reference current (Iref) of 129A.
V link
R5
IFB
R IFB
8
R6
V DD
CS1501
15k
400V – 90V 2
Po = 90V ------------------------------------------------------------2 70kHz L B 400V
2
[Eq.2]
Changing the value for the Vlink voltage is not recommended.
10
IFB
24k
1
Iref
ADC
Figure 17. IFB Input Pin Model
DS927PP6
CS1501
Resistor RIFB sets the feedback current and is calculated as
follows:
400V – V DD
V link – V DD
[Eq.4]
R IFB = ---------------------------- = -----------------------------I ref
129mA
losses. CS1501 uses an auxiliary winding on the PFC boost
inductor to implement zero-voltage switching.
Zero Crossing
Detection
ZCD
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.
A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the PFC control algorithm.
V rect
GD ‘ON’
ZCD_below _zero
R1
IAC
Figure 20. Zero-voltage Switch
R IAC
V DD
8
R2
CS1501
15k
IA C
24k
3
Iref
ADC
Figure 18. IAC Input Pin Model
Resistor RIAC sets the IAC current and is derived as follows:
R IAC = R IFB
[Eq.5]
For optimal performance, resistors RIAC & RIFB should use 1%
tolerance or better resistors for best Vlink voltage accuracy.
5.7 Valley Switching
The zero-current detection (ZCD) pin is monitored for
demagnetization in the auxiliary winding of the boost inductor
(LB). The ZCD circuit is designed to detect the VAux
valley/zero crossings by sensing the voltage transformed onto
the auxiliary winding of LB.
LB
During each switching cycle, when the boost diode current
reaches zero, the boost MOSFET drain-source voltage begins
oscillating at the resonant frequency of the boost inductor and
MOSFET parasitic output capacitance. The ZCD_below_zero
signal transitions from high to low just prior to a local minimum
of the MOSFET drain-source voltage oscillation. The
zero-crossing detect circuit ensures that a ZCD_below_zero
pulse will only be generated when the comparator output is
continuously high for a nominal time period (tZCB) of 200ns.
Therefore, any negative edges on the comparator's output
due to spurious glitches will not cause a pulse to be
generated. Due to the CS1501’s variable-frequency control,
the MOSFET switching cycle will not always be initiated at the
first resonant valley.
The external circuitry should be designed so that the current
(IZCD) at the ZCD pin is approximately 1.0 mA. The table
below depicts approximate values for R3 and R4 for a range
of boost-to-auxiliary inductor turns ratio, N.
Vlink
N:1
D2
FE T Drain
N
~R3
~R4
9
10
11
12
13
14
15
46k
42k
37.5k
35.5k
32k
29.5k
27.5k
1.75k
1.75k
1.75k
1.75k
1.75k
1.75k
1.75k
Table 1. Aux Inductor Turns Ratio vs. R3 and R4
IAux
CS1501
R3
IZ CD
5
+
VAux
ZCD
R4
Cp
+
V th( Z CD) -
ZCD_below_z ero
Demag
Comparator
Resistors R3 and R4 were calculated using Vlink = 400V and
Cp = 10pF.
Equation 6 is used to calculate the cut-off frequency defined
by the RC circuit at the ZCD pin.
f c = 1 2 R3 R4 C p
-
[Eq.6]
where:
Figure 19. ZCD Input Pin Model
fc
The objective of zero-voltage switching is to initiate each
MOSFET switching cycle when its drain-source voltage is at
the lowest possible voltage potential, thus reducing switching
The cut-off frequency, fc, needs to be 10x the ringing
frequency
Cp
Capacitance at the ZCD pin
DS927PP6
11
CS1501
5.8 Brownout Protection
5.9
The CS1501 brownout detection circuit monitors the peak of
the Vrect input voltage and disables the PWM switching when
it drops below a pre-determined threshold. Hysteresis and
minimum detection time are provided to avoid brownout
detection during short input transients. When brownout is
detected, the CS1501 enters standby mode. On recovery from
brownout, it re-enters normal operating mode.
The overvoltage protection (OVP) will trigger immediately and
stop the gate drive when the current into the IFB pin (IOVP)
exceeds 105% of the reference current (Iref) value. The IC
resumes gate drive switching when the measured current at IFB
drops below IOVP – IOVP(Hy). Equation 8 is used to calculate the
OVP threshold.
Current IAC is proportional to the AC input voltage Vrect , where
Vrect = RIAC xIAC and RIAC = R1+R2 in Figure 18 on page 11.
The digitized current applied to the IAC pin is monitored by the
brownout protection algorithm. When Vrect drops below the
brownout detection threshold, the CS1501 triggers a timer.
The IC asserts the brownout protection and stops the
gate-drive switching only if the timer exceeds 56ms. This is
the equivalent of 7 rectified line cycles at 60Hz.
During the brownout state, the device continues monitoring
the input line voltage. The device exits the brownout state
when IAC exceeds the brownout upper threshold for at least
56ms. Typical values for the lower (IBP(lower) ) and upper
(IBP(upper) ) brownout thresholds are 31.6A and 39.6A,
respectively.
The overpower protection may activate prior to brownout
protection, depending on the load.
TBrownout
Brownout
Thresholds
Upper
56 ms
56 ms
Lower
Start
Timer
Enter Standby
Start Timer
Exit Standby
Figure 21. Brownout Sequence
The maximum response time of the brownout protection
feature occurs at light-load conditions. It is calculated by
Equation 7.
8 ms
T Brownout = 8 ms + ------------ 128 V – V BP th + 56 ms [Eq.7]
5V
8
= 8 + --- 128 – 94.8 + 56 = 117ms
5
where:
VBP(th)
12
Brownout threshold voltage, VBP(th) = IBP(lower) xRIAC
Overvoltage Protection
V OVP = R IFB I OVP + V DD
5.10
[Eq.8]
Overcurrent Protection
To limit boost inductor current through the FET and to prevent
boost inductor saturation conditions, the CS1501 incorporates
a cycle-by-cycle peak inductor current limit circuit using an
external shunt resistor to ‘sense’ the FET source current
accurately. The overcurrent protection (OCP) circuit is
designed to monitor the current when the active switch is
turned on. The OCP circuit is enabled after the leading-edge
blanking time (tLEB). The shunt voltage is compared to a
reference voltage, Vcs(th), to determine whether an
overcurrent condition exists. The OCP circuit triggers
immediately, allowing the OCP algorithm to turn off the gate
driver.
The overcurrent protection circuit is also designed to monitor
for a catastrophic overcurrent occurrence by sensing sudden
and abnormal operating currents. A second OCP threshold,
Vcs(clamp), determines whether a severe overcurrent condition
exists. This immediately turns off the gate drive and the
system enters a restart mode. The CS1501 inhibits all
switching operations for approximately 1.6ms then attempts to
restart normal operation.
5.11
Overpower Protection
The CS1501 incorporates an internal Overpower Protection
(OPP) algorithm. This provides protection from overload
conditions. This algorithm uses the condition that output
power is a function of the boost inductor (Section 5.4).
Under moderate overload, Vlink may droop up to 10% while
maintaining rated power and PFC. Further increasing the load
current causes Vlink to drop below the startup threshold
(~360V). Below this threshold, the circuit changes its
operating mode to startup with more power available to raise
Vlink. As Vlink reaches its nominal value, startup mode is
canceled and power is now limited to the rated value. If the
overload is still present, this cycle will repeat.
If a sustained overload, or a repeated cycle of overload events
is detected for greater than 112 mS, the CS1501 shuts down
for 2.5 seconds, then attempts to restart.
DS927PP6
CS1501
5.12
Open/Short Loop Protection
If the PFC output sense resistor, RIFB, fails (open or short to
GND), the measured output voltage decreases at a slew rate of
about 2 V/s, which is determined by the ADC sampling rate.
The IC stops the gate drive when the measured output voltage is
lower than the measured line voltage. The IC resumes gate drive
switching when the current into the IFB pin becomes larger than
or equal to the current into the IAC pin and Vlink is greater than
the peak of the line voltage (Vrect(pk)). The maximum response
time of open/short loop protection for RIFB is about 150s.
5.14 Standby (STBY) Function
The standby (STBY) pin provides a means by which an
external signal can cause the CS1501 to enter a
non-operating, low-power state. The STBY input is intended to
be driven by an open-collector/open-drain device. Internal to
the pin, there is a pull-up resistor connected to the VDD pin as
shown in Figure 22. Since the pull-up resistor has a high
impedance, the user may need to provide a filter capacitor (up
to 1000pF) on this pin.
8
VDD
5.13 Internal Overtemperature Protection
An internal thermal sensor triggers a shutdown when the
temperature exceeds 135°C (nominal) on the silicon. The
sensor sends a signal to the core that supplies current to all
internal digital logic, cutting off power from them. Once the
temperature of the IC has dropped by 9°C (nominal), the
sensor resets, allowing power to the logic.
If the PFC input sense resistor RIAC fails (open or short to GND),
the current reference signal supplied to the IC on pin IAC falls to
zero.
600k
STBY
CS1501
2
<1 nF
See Text
6
GND
Figure 22. STBY Pin Connection
When the STBY pin is not used, it is recommended that the pin
be tied to VDD (pulled high).
DS927PP6
13
CS1501
5.15
Eq. #
Summary of Equations
Equation
Variables/Recommended Values
Output Power (page 10)
1
Po
Rated output power of the system.
Efficiency of the boost converter (estimated as
100% by the PFC algorithm).
Vin(min)
Minimum RMS line voltage is 90Vrms,
measured after the rectifier and EMI filter.
Vlink
Nominal PFC output voltage must be 400V.
fmax
Maximum switching frequency is 70kHz.
Output IFB Sense Resistor (page 11)
LB
Boost inductor specified by rated power
requirement.
400V – V DD
V link – V DD
R IFB = ----------------------------- = ------------------------------I ref
129A
Margin factor to guarantee rated output power
(Po) against boost inductor tolerances.
R IAC = R IFB
RIAC
Value of the IAC pin sense resistor(s).
Auxiliary Winding Cut-off Frequency (page 11)
RIFB
Value of the IFB pin sense resistor(s).
Iref
Value of the fixed, internal reference current.
fc
The cut-off frequency, fc, needs to be 10x the
ringing frequency or fc = 10MHz.
Cp
Capacitance at the ZCD pin. Cp <10pF.
VBP(th)
Brownout threshold voltage. VBP(th) = 94.8V.
Cout
Value of the output capacitor in microfarads.
fline(min)
Minimum line frequency.
PO
I LB rms = -----------------------------V in min
VDD
IC Supply Voltage.
Vlink Voltage Ripple
VOVP
OVP threshold.
PO
V link rip = -----------------------------------------------------------------------2 f line min V link C out
IOVP
Current into the IFB pin.
2 V link – V in min 2
Po = V in min --------------------------------------------------------2 f max L B V link
Output Power w/ recommended values (page 10)
2
2 400V – 90Vrms 2
Po = 90Vrms ------------------------------------------------------------2 70kHz L B 400V
Boost Inductor (page 10)
3
4
2 400V – 90Vrms 2
L B = 90Vrms ------------------------------------------------------------2 70kHz Po 400V
Input IAC Sense Resistor (page 11)
5
6
f c = 1 2 R3 R4 C p
Maximum Response Time for Brownout: (page 12)
7
8 ms
T Brownout = 8 ms + ------------ 128 V – V BP th + 56 ms
5V
Overvoltage Protection (page 12)
8
V OVP = R IFB I OVP + V DD
Boost Inductor Peak Current
9
4 PO
I LB pk = ------------------------------------------- V in min 2
Boost Inductor RMS Current
10
11
14
DS927PP6
CS1501
6. PACKAGE DRAWING
8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
A
L
e
DIM
A
A1
B
C
D
E
e
H
L
A1
INCHES
MIN
0.053
0.004
0.013
0.007
0.189
0.150
0.040
0.228
0.016
0°
MAX
0.069
0.010
0.020
0.010
0.197
0.157
0.060
0.244
0.050
8°
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.02
1.52
5.80
6.20
0.40
1.27
0°
8°
JEDEC # MS-012
7. ORDERING INFORMATION
Part #
Temperature Range
Package Description
CS1501-FSZ
-40°C to +125°C
8-lead SOIC, Lead (Pb) Free
8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Ratinga
Max Floor Lifeb
CS1501-FSZ
260°C
2
365 Days
a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
b. Stored at 30°C, 60% relative humidity.
DS927PP6
15
CS1501
9. REVISION HISTORY
Revision
Date
Changes
PP1
NOV 2010
Preliminary Release - Updated block diagram and General Description section.
PP2
DEC 2010
Updated Brownout Protection section, Overcurrent Protection section. Added
Current Sense Reference Clamp specification.
PP3
JAN 2011
Updated STBY pin and description.
PP4
APR 2011
Updated Characteristics and Specifications section.
PP5
MAY 2011
Updated Typical Electrical Performance section.
PP6
JUN 2011
Updated Characteristics and Specifications section.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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16
DS927PP6