ONSEMI NCP1215SNT1

NCP1215
Product Preview
Low Cost Variable OFF Time
Switched Mode Power
Supply Controller
The NCP1215 is a controller for low power off−line flyback
Switchemode Power Supplies (SMPS) featuring low size, weight and
cost constraints together with a good low standby power performance.
The operating principle uses switching frequency reduction at light
load by increasing the OFF Time. Also, when OFF Time expands, the
peak current is gradually reduced down to approximately 1/4 of the
maximum peak current to prevent from exciting the transformer
mechanical resonances. The risk of acoustic noise is thus greatly
diminished while keeping good standby power performance.
A low power internal supply block also ensures very low current
consumption at startup without hampering the standby power
performance.
A special primary current sensing technique minimizes the impact
of SMPS switching on control IC operation. The choice of peak
voltage across the current sense resistor allows dissipation to be
further reduced. The negative current sensing technique offers
advantages over a traditional approach by avoiding the voltage drop
incurred by traditional MOSFET source sensing. Thus, the IC drive
capability is greatly improved.
Finally, the bulk input ripple ensures a natural frequency dithering
which smooths the EMI signature.
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MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
6
TSOP−6
(SOT23−6, SC59−6)
SN SUFFIX
CASE 318G
1
6
1
FAA
A
L
Y
W
Pb−Free Package is Available
Variable OFF Time Control Method
Very Low Current Consumption at Startup
Natural Frequency Dithering for Improved EMI Signature
Current Mode Control Operation
Peak Current Compression Reduces Transformer Noise
Programmable Current Sense Resistor Peak Voltage
Undervoltage Lockout
FB 1
8
NC
CT 2
7
NC
CS 3
6
VCC
5
Gate
GND
TSOP−6
CS
1
6
Gate
GND
2
5
VCC
CT
3
4
FB
(Top View)
ORDERING INFORMATION
Device
NCP1215DR2
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
October, 2004 − Rev. 2
4
(Top View)
Auxiliary Power Supply
Standby Power Supply
AC−DC Adapter
Off−line Battery Charger
 Semiconductor Components Industries, LLC, 2004
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
SOIC−8
Typical Applications
•
•
•
•
FAAYW
PIN CONNECTIONS
Features
•
•
•
•
•
•
•
•
P1215
ALYW
1
Package
Shipping†
SOIC−8
2500 Tape & Reel
NCP1215DR2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
NCP1215SNT1
TSOP−6
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP1215/D
NCP1215
Line
+
+
+
−
+
FB
NC
CT
NC
CS
Vcc
GND Gate *
N
* If your application requires a gate−source resistor, please refer to design guidelines in this document.
Figure 1. Typical Application
FB
Feedback Loop
Control
VDD
Iref
−
Voffset
+
0−7 V
CT
−
+
Reference
Regulator
+
−
VCC
12/8.5 V
Undervoltage
Lockout
Off−Time
Comparator
10 A
Gate Driver
Set
CS
Q
12.5−50 A
Current Sense Comparator
GND
+
−
Reset
Q
Figure 2. Representative Block Diagram
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2
Gate
NCP1215
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PIN FUNCTION DESCRIPTION
TSOP−6
SOIC−8
Symbol
Description
4
1
FB
The FB pin provides voltage feedback loop. The current injected into the pin determines the
primary switch OFF time interval. It also influences the peak value of the primary current.
3
2
CT
Connection for an external timing programming capacitor.
1
3
CS
The CS pin senses the power switch current.
2
4
GND
Primary and internal ground.
6
5
Gate
Output drive for an external power MOSFET.
5
6
Vcc
Power supply voltage and Undervoltage Lockout.
7
7
NC
Unconnected pin.
8
8
NC
Unconnected pin.
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MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
Vcc
18
V
FB Pins Voltage Range
VFB
−0.3 to 18
V
CS and CT Pin Voltage Range
Vin
−0.3 to 10
V
RJA
178
°C/W
Junction Temperature
TJ
150
°C
Storage Temperature Range
Tstg
−60 to +150
°C
VESD−HBM
2.0
kV
Thermal Resistance, Junction−to−Air (SOIC−8 Version)
ESD Voltage Protection, Human Body Model (Except CT Pin)
ESD Voltage Protection, Human Body Model for CT Pin
VESD−HBM−CT
1.5
kV
ESD Voltage Protection, Machine Model (Except CT Pin)
VESD−MM
200
V
VESD−MM−CT
150
V
ESD Voltage Protection, Machine Model for CT Pin
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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3
NCP1215
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values Tj = 25°C, for min/max values Tj = 0°C to +105°C, unless
otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Voffset
1.05
1.19
1.34
V
Maximum CT Pin Voltage at FB Current = 25 A (Including Voffset)
VCT−25A
2.4
3.1
4.3
V
Maximum CT Pin Voltage at FB Current = 50 A (Including Voffset)
VCT−50A
3.6
4.6
6.2
V
ICT
8.0
9.8
11.5
A
Source Current Maximum Voltage Capability
VCT−max
−
6.5
−
V
Minimum CT Pin Voltage (Pin Unloaded, Discharge Switch Turned On)
VCT−min
−
−
20
mV
Minimum Source Current (IFB = 180 A, CT Pin Grounded)
ICS−min
8.0
12.5
16
A
Maximum Source Current (IFB = 0 A, CT Pin Grounded)
ICS−max
40
49
58
A
Vth
15
42
80
mV
tdelay
−
215
310
ns
Sink Resistance (Isink = 30 mA)
ROL
25
40
90
Source Resistance (Isource = 30 mA)
ROH
60
80
130
VOLTAGE FEEDBACK
Offset Voltage
CT PIN − OFF TIME CONTROL
Source Current (CT Pin Grounded)
CURRENT SENSE
Comparator Threshold Voltage
Propagation Delay (CS Falling Edge to Gate Output)
GATE DRIVE
POWER SUPPLY
VCC Startup Voltage
Vstartup
−
12.5
14.2
V
Undervoltage Lockout Threshold Voltage
VUVLO
7.2
9.0
−
V
Vhys
2.2
3.5
−
V
VCC Startup Current Consumption (VCC = 8.0 V)
ICC−start
−
2.8
6.5
A
VCC Steady State Current Consumption
(CGATE = 1.0 nF, fSW = 100 kHz, FB open)
ICC−SW
0.55
0.9
1.75
mA
Hysteresis (Vstartup − VUVLO)
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NCP1215
11.6
8.8
11.5
8.7
11.4
8.6
VUVLO, (V)
Vstartup, (V)
TYPICAL CHARACTERISTICS
11.3
8.5
11.2
8.4
11.1
8.3
11.0
−25
0
25
50
75
8.2
−25
125
100
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Vstartup Threshold vs. Junction
Temperature
Figure 4. VUVLO Threshold vs. Junction
Temperature
0.990
125
1.20
1.18
0.985
1.16
1.14
Voffset, (V)
ICC−SW, (mA)
0.980
0.975
0.970
1.12
1.10
1.08
1.06
1.04
0.965
1.02
0.960
−25
0
25
50
75
100
1.00
−25
125
0
TJ, JUNCTION TEMPERATURE (°C)
48.5
60
48.0
55
VCS−th, (mV)
ICS−max, (A)
65
47.5
47.0
46.0
35
75
125
45
40
50
100
50
46.5
25
75
Figure 6. Offset Voltage vs. Junction
Temperature
49.0
0
50
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Operating Current Consumption vs.
Junction Temperature
45.5
−25
25
100
30
−25
125
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Current Sense Source Current vs.
Junction Temperature
Figure 8. Current Sense Threshold vs.
Junction Temperature
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5
125
NCP1215
16
10.0
9.9
14
VCT−min, (mV)
ICT, (A)
9.8
9.7
9.6
12
10
8
9.5
9.4
−25
0
25
50
75
100
6
−25
125
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. CT pin Source Current vs. Junction
Temperature
Figure 10. CT pin Threshold vs. Junction
Temperature
120
60.0
100
50.0
125
Rsource
80
40.0
60
ICS, (A)
Rsource−Rsink, ()
TJ = 25°C
Rsink
30.0
40
20.0
20
10.0
0
−25
0
25
50
75
100
0.0
125
0
TJ, JUNCTION TEMPERATURE (°C)
25
50
75
100
Ifb, FEEDBACK CURRENT (A)
Figure 11. Drive Sink and Source Resistance
vs. Junction Temperature
Figure 12. Current Sense Source Current vs.
Feedback Current
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125
NCP1215
APPLICATION INFORMATION
Feedback Loop Control
The NCP1215 implements a current mode SMPS with a
variable OFF−time dependant upon output power demand.
It can be seen from the typical application that NCP1215 is
designed to operate with a minimum number of external
component. The NCP1215 incorporates the following
features:
• Frequency Foldback: Since the switch−off time
increases when power demand decreases, the switching
frequency naturally diminishes in light load conditions.
This helps to minimize switching losses and offers
excellent standby power performance.
• Very Low Startup Current: The patented internal
supply block is specially designed to offer a very low
current consumption during startup. It allows the use of
a very high value external startup resistor, greatly
reducing dissipation, improving efficiency and
minimizing standby power consumption.
• Natural Frequency Dithering: The quasi−fixed Ton
mode of operation improves the EMI signature since
the switching frequency varies with the natural bulk
ripple voltage.
• Peak Current Compression: As the load becomes
lighter, the frequency decreases and can enter the
audible range. To avoid exciting transformer
mechanical resonances, hence generating acoustic
noise, the NCP1215 includes a patented technique,
which reduces the peak current as power goes down.
As such, inexpensive transformer can be used without
having noise problems.
• Negative Primary Current Sensing: By sensing
the total current, this technique does not modify the
MOSFET driving voltage (Vgs) while switching.
Furthermore, the programming resistor together with the
pin capacitance, forms a residual noise filter which
blanks spurious spikes. Also fixing primary current level
to a maximum value sets the maximum power limit.
• Programmable Primary Current Sense: It offers a
second peak current adjustment variable which improves
the design flexibility.
• Secondary or Primary Regulation: The feedback
loop arrangement allows simple secondary or primary
side regulation without significant additional external
components.
A detailed description of each internal block within the IC
is given in the following.
The main task of the Feedback Loop Block is to control
the SMPS output voltage through the change of primary
switch OFF time interval. It sets the peak voltage of the
timing capacitor, which varies upon the output power
demand. Figure 13 shows the simplified internal schematic:
VCC
Current
Mirror
1:1
Voffset
+
−
17 k
FB
Current
Mirror
1:1
To OFF
Time
Comparator
45 k
Figure 13. Feedback Loop − OFF Time Control
OFF−Time Comparator Input Voltage
The voltage feedback signal is sensed as a current injected
through the FB pin.
VDD
Voffset
0 A
FB Pin Sink Current
Figure 14. FB Loop Transfer Characteristic
The transfer characteristic (output voltage to input
current) of the feedback loop control block can be seen in
Figure 14. VDD refers to the internal stabilized supply
whereas the offset value sets the maximum switching
frequency in lack of optocoupler current (e.g. an output
short−circuit).
To keep the switching frequency above the audio range in
light load condition the FB pin also regulates in certain range
the peak primary current. The corresponding block diagram
can be seen from Figure 15.
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NCP1215
To Current Sense Comparator
From Feedback Loop Block
17 k
FB
−
CS
Voffset
Current
Mirror
4:3
37.5 A
12.5 A
+
Voffset to VDD
−
+
CT
To Latch’s Set Input
Figure 15. Feedback Loop − Current Sense Control
10 A
The resulting current sense regulation characteristic can
be seen from Figure 16.
To Latch’s Output
CT
50 A
CS Pin Source Current
GND
Figure 17. OFF Time Control
During the switch−ON time, the CT capacitor is kept
discharged by a MOSFET switch. As soon as the latch
output changes to a low state, the voltage across CT created
by the internal current source, starts to ramp−up until its
value reaches the threshold given by the feedback loop
demand.
12.5 A
0 A
50 A
100 A
140 A
V
FB Pin Sink Current
Figure 16. Current Sense Regulation Characteristic
VDD
POUT Goes Down
When the load goes light, the compression circuitry
decreases the peak current. This has the effect of slightly
increasing the switching frequency but the compression
ratio is selected to not hamper the standby power.
CT Pin
Voltage
POUT Goes Up
P3
OFF Time Control
P2
Voffset
The loop signal together with the internal current source,
via an external capacitor, controls the switch−off time. This
is portrayed in Figure 17.
P1
toff−min
t
Figure 18. CT Pin Voltage (Pout1 Pout2 Pout3)
The voltage that can be observed on CT pin is shown in
Figure 18. The bold waveform shows the maximum output
power when the OFF time is at its minimum. The IC allows
an OFF time of several seconds.
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NCP1215
Primary Current Sensing
The primary current sensing method we described, brings
the following benefits compared to the traditional approach:
• Maximum peak voltage across the current sense resistor
is determined and can be optimized by the value of the
shift resistor.
• CS pin is not exposed to negative voltage, which could
induce a parasitic substrate current within the IC and
distort the surrounding internal circuitry.
• The gate drive capability is improved because the
current sense resistor is located out of the gate driver
loop and does not deteriorate the turn−on and also
turn−off gate drive amplitude.
The primary current sensing circuit is shown in Figure 19.
FB
Feedback Loop
Control
12.5 A
50 A
CS
+
−
Vshift
Rshift
To Latch
Gate Driver
GND
The Gate Driver consists of a CMOS buffer designed to
directly drive a power MOSFET.
It features an unbalanced source and sink capabilities to
optimize turn ON and OFF performance without additional
external components. Since the power MOSFET turns−off
at high drain current, to minimize its turn−off losses the sink
capability of the gate driver is increased for a faster turn−off.
To the opposite, the source capability is lower to slow−down
power MOSFET at turn−on in order to reduce the EMI noise.
Whenever the IC supply voltage is lower than the
undervoltage threshold, the Gate Driver is low, pulling down
the gate to ground. It eliminates the need for an external
resistor.
RCS
VCS
Iprimary
Figure 19. Primary Current Sensing
When the primary switch is ON, the transformer current
flows through the sense resistor Rcs. The current creates a
voltage, Vcs which is negative with respect to GND. Since
the comparator connected to CS pin requires a positive
voltage, the voltage Vshift is developed across the resistor
Rshift by a current source which level−shifts the negative
voltage Vcs. The level−shift current is in range from 12.5 to
50 A depending on the Feedback Loop Control block
signal (see more details in the Feedback Loop Control
section).
The peak primary current is thus equal to:
R
Ipk shift · ICS
RCS
Startup Circuit
An external startup resistor is connected between high
voltage potential of the input bulk capacitor and Vcc supply
capacitor. The value of the resistor can be calculated as
follows:
(eq. 1)
Rstartup A typical CS pin voltage waveform is shown in Figure 20.
Vbulk Vstartup
Istartup
(eq. 2)
Where:
Vstartup
Vcc voltage at which IC starts operation
(see spec.)
Istartup
Startup current
Vbulk
Input bulk capacitor’s voltage
Since the Vbulk voltage has obviously much higher value
than Vstartup the equation can be simplified in the following
way:
V
Ishift = 50 A
Rstartup Ishift = 12.5 A
Vbulk
Istartup
(eq. 3)
The startup current can be calculated as follows:
Vstartup
Istartup CVcc
ICC−start
tstartup
0
Switch
Turn−on
t
Where:
CVcc
tstartup
ICC−start
Figure 20. CS Pin Voltage
Figure 20 also shows the effect of the inductor current of
differing output power demand.
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Vcc capacitor value
Startup time
IC current consumption (see spec.)
(eq. 4)
NCP1215
Application Design Example
If the IC current consumption is assumed constant during
the startup phase, one can obtain resulting equation for
startup resistor calculation:
Rstartup Vbulk
CVcc
Vstartup
tstartup
An example of the typical wall adapter application is
described hereafter.
As a wall adapter it should be able to operate properly with
wide range of the input voltage from 90 VAC up to 265 VAC.
The bulk capacitor voltage then can be calculated:
(eq. 5)
ICC−start
Vbulk− min VAC− min 2 90 · 2 127 VDC
Switching Frequency
(eq. 11)
The switching frequency varies with the output load and
input voltage. The highest frequency appears at highest
input voltage and maximum output power.
Since the peak primary current is fixed, the on time
portion of the switching period can be calculated:
Ipk
ton Lp
Vbulk
Vbulk− max VAC− max 2 265 · 2 375 VDC
(eq. 12)
The requested output power is 5.2 Watts.
Assuming 80% efficiency the input power is equal to:
(eq. 6)
P
5.2
Pin out
0.8 6.5 W
Where:
Lp
Transformer primary inductance
Ipk
Peak primary current
Using equation for peak primary current estimation the
switch−on time is:
Rshift
ton Lp
50 · 10−6
Rcs · Vbulk
The average value of input current at minimum input
voltage is:
Iin−avg V
Pin
6.5 51.2 mA (eq. 14)
127
bulk− min
The suitable reflected primary winding voltage for 600 V
rated MOSFET switch is:
(eq. 7)
Vflbk 600 V Vbulk− max Vspike
Minimum switch−on time occurs at maximum input
voltage:
600 375 100 125 V
(eq. 15)
Using calculated flyback voltage the maximum duty cycle
can be calculated:
Rshift
ton− min Lp
50 · 10−6 (eq. 8)
Rcs · Vbulk− max
As it can be seen from the above equation, the switch−on
time linearly depends on the input bulk capacitor voltage.
Since this voltage has ripple due to AC input voltage and
input rectifier, it allows natural frequency dithering to
improve EMI signature of the SMPS.
The switch−off time is determined by the charge of an
external capacitor connected to the CT pin. The minimum
Toff value can be computed by:
V
toff− min CT offset CT 1.2
ICt
10−5
0.12 · 106 CT
(eq. 13)
max Vflbk
Vflbk Vbulk− min
(eq. 16)
125
0.496 0.5
125 127
Following equation determines peak primary current:
Ippk 2 · Iin−avg
max
−3
2 · 51.2 · 10
0.5
(eq. 17)
204.7 mA
The desired maximum switching frequency at minimum
input voltage is 75 kHz.
The highest switching frequency occurs at the highest
input voltage and its value can be estimated as follows:
(eq. 9)
Where:
Voffset Offset voltage (see spec.)
ICt
CT pin source current (see spec.)
The maximum switching frequency then can be evaluated
by:
f max −high f max −low
Vbulk− max
Vbulk− min max(eq. 18)
75 · 103 375 0.5 110.7 kHz
127
This frequency is much below 150 kHz, so that the desired
operating frequency can be exploited for further calculation
of the primary inductance:
1
fsw− max ton− min toff− min
(eq. 10)
1
Lp · Rshift
−6
6
· 50 · 10 0.12 · 10 · CT
V
· max
Lp bulk− min
Ippk · fsw− max
Vbulk · Rcs
As output power diminishes, the switching frequency
decreases because the switch−off time prolongs upon
feedback loop. The range of the frequency change is
sufficient to keep output voltage regulation in any light load
condition.
127 · 0.5
4.14 mH
0.2047 · 75 · 103
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10
(eq. 19)
NCP1215
The EF16 core for transformer was selected. It has
cross−section area Ae = 20.1 mm2. The N67 magnetic
allows to use maximum operating flux density
Bmax = 0.28 Tesla.
The number of turns of the primary winding is:
Lp · Ippk
np B max · Ae
V
RCS CS 0.5 2.442 2.7 0.2047
Ippk
The voltage drop across the sense resistor needs to be
recalculated:
VCS RCS · Ippk 2.7 · 0.2047 0.553 V (eq. 25)
Using the above results the value of the shift resistor is:
(eq. 20)
V
Rshift CS 0.553 11.06 k 11 k
ICS
50 · 10−6
(eq. 26)
−3
4.14 · 10 · 0.2047 150 turns
0.28 · 20.1 · 10−6
The value of timing capacitor for the off time control has
to be calculated for minimum bulk capacitor voltage since
at these conditions the converter should be able to deliver
specified maximum output power. The value of the timing
capacitor is then given by the following equation:
The AL factor of the transformer’s core can be calculated:
AL Lp
(np)2
−3
4.14 · 10 · 184 nH
2
(150)
(eq. 21)
For an adapter output voltage of 6.5 V, the number of turns
of the secondary winding can be calculated accounting
Schottky diode for output rectifier as follows:
ns CT (Vs Vfwd)(1 max)np
max · Vbulk− min
(eq. 22)
(6.5 0.7)(1 0.5)150
8.5 9 turns
0.5 · 127
Lp · Ippk
V
bulk− min
1.2 · 106
1
75 · 103
(eq. 27)
3
4.14 · 10127 · 0.2047
55.5 pF 56 pF
0.12 · 106
Rstartup (Vs Vfwd)(1 max)np
max · Vbulk− min
1
fsw
The value of the startup resistor for startup time of 200 ms
and Vcc capacitor of 200 nF is following:
The number of turns for auxiliary winding can be
calculated similarly:
ns (eq. 24)
(eq. 23)
Vbulk− min
CVcc
(12 1)(1 0.5)150
15.35 15 turns
0.5 · 127
Vstartup
tstartup
ICC−start MAX
200 · 10−9
127
12
10 · 10−6
0.2
5.77 M 5.6 M
The peak primary current is known from initial
calculations. The current sense method allows choosing the
voltage drop across the current sense resistor. Let’s use a
value of 0.5 V. The value of the current sense resistor can
then be evaluated as follows:
(eq. 28)
The result of all the calculations is the application
schematic depicted in Figure 21.
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11
NCP1215
3
J1
Line 1
J2
Neutral 1
L1
+ 1
S250
T1
2.2 mH
C1 +
C2
4
2 −
1 nF/Y
C8
D1
2.2 F/
400 V
2.2 F/
400 V
4
+
R3
2M7
100 nF
D5
3
R7
LL4448
C3
1
FB
2M7
NC1
8
R6
47 k
X
10 nF
C4
2 CT
56 pF
3
11 k R2
R1
2.7
4
CS
GND
NC2 7 X
VCC
Gate
R5
220
C6
100 nF
5
5
1
47 k
1 nF/
500 V
470 F/
16 V
+
L2
4.7 H
J3
+6.5 [email protected]
1
800 mA
R8
220
10 F/
16 V +
R9
1k
C7
D8
6
D9 MBRS360T3
C9
C5
R4
IC1
8
C10
2
MURA160T3
Q1
MTD1N60
BZX84C5V6
D7
NCP1215
J4
1 GND
ISO1
PC817
Figure 21. Adaptor Application Schematic
The following oscilloscope snapshots illustrate the
operation of the working adapter. The Channel 3 in
Figure 22 shows CT pin voltage at full output load. The
Channel 1 is a gate driver output.
The CT voltage at no load condition is depicted in
Figure 23.
Figure 22. CT Voltage at Full Load Condition
Figure 23. CT Voltage at No Load Condition
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12
NCP1215
Figure 24 shows CT voltage and also by Channel 2 the
switch’s drain voltage at light load conditions.
Figure 26 demonstrates the reduction of the peak primary
current at light load conditions.
Figure 24. CT and Drain at Light Load
Figure 26. CS Pin at Light Load Condition
The waveform on the current sense pin at full load
conditions can be observed from Channel 3 in Figure 25.
Gate−Source Resistor Design Guidelines
In some applications, there is a need to wire a resistor
between the MOSFET gate and source connections. This
can preclude an eventual MOSFET destruction if, in the
production stage, the converter is powered whilst the gate is
left unconnected. However, dealing with an extremely low
startup current implies a careful selection of the gate−source
resistance. With the NCP1215, the gate−source resistor must
be calculated to allow the growth of the VCC capacitor to
4.0 V in order to not interfere with the power−on sequence.
The following equation helps deriving Rgate−source,
accounting for the minimum rectified input voltage and the
startup resistor: Vinmin x Rgate−source/(Rgate−source +
Rstartup) 4.0 V. If we take a Vinmin of 100 VDC, a startup
resistor of 4.0 M, then Rgate−source equals 180 k as a
minimum normalized value.
Figure 25. CS Pin at Full Load Condition
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13
NCP1215
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
X 45 DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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14
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
NCP1215
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE M
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
L
6
S
1
5
4
2
3
B
D
MILLIMETERS
DIM MIN
MAX
A
2.90
3.10
B
1.30
1.70
C
0.90
1.10
D
0.25
0.50
G
0.85
1.05
H 0.013 0.100
J
0.10
0.26
K
0.20
0.60
L
1.25
1.55
M
0
10 S
2.50
3.00
G
M
J
C
0.05 (0.002)
K
H
SOLDERING FOOTPRINT*
2.4
0.094
1.9
0.075
0.95
0.037
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
INCHES
MIN
MAX
0.1142 0.1220
0.0512 0.0669
0.0354 0.0433
0.0098 0.0197
0.0335 0.0413
0.0005 0.0040
0.0040 0.0102
0.0079 0.0236
0.0493 0.0610
0
10 0.0985 0.1181
NCP1215
The product described herein (NCP1215), may be covered by the following U.S. patents: 6,385,060, 6,605,978. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your
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NCP1215/D