NTMFS5844NL, NVMFS5844NL Power MOSFET 60 V, 61 A, 12 mW, Single N−Channel Features • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These are Pb−Free Devices http://onsemi.com V(BR)DSS RDS(ON) MAX 12 mW @ 10 V 60 V Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RYJ−mb (Notes 1, 2, 3, 4) Power Dissipation RYJ−mb (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1, 3, 4) Power Dissipation RqJA (Notes 1 & 3) Pulsed Drain Current Tmb = 25°C Steady State Symbol Value Unit VDSS 60 V VGS "20 V ID 61 A Tmb = 100°C Tmb = 25°C Steady State PD 107 ID 11.2 Current Limited by Package (Note 4) TA = 25°C Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL(pk) = 31 A, L = 0.1 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) N−CHANNEL MOSFET A PD 3.7 Junction−to−Ambient − Steady State (Note 3) IDM 247 A IDmaxPkg 80 A TJ, Tstg −55 to 175 °C IS 60 A EAS 48 mJ TL 260 °C Symbol Value Unit RYJ−mb 1.4 °C/W RqJA 41 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2012 June, 2012 − Rev. 3 D 1.8 THERMAL RESISTANCE MAXIMUM RATINGS Junction−to−Mounting Board (top) − Steady State (Notes 2, 3) MARKING DIAGRAM W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Parameter S (1,2,3) W 8.0 TA = 100°C TA = 25°C, tp = 10 ms G (4) 54 TA = 100°C TA = 25°C D (5) 43 Tmb = 100°C TA = 25°C 61 A 16 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter ID MAX 1 1 DFN5 (SO−8FL) CASE 488AA STYLE 1 A Y W ZZ S S S G 5844NL AYWZZ D D D = Assembly Location = Year = Work Week = Lot Traceability ORDERING INFORMATION Device Package Shipping† NTMFS5844NLT1G DFN5 1500/Tape & Reel (Pb−Free) NVMFS5844NLT1G DFN5 1500/Tape & Reel (Pb−Free) NVMFS5844NLT3G DFN5 5000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTMFS5844NL/D NTMFS5844NL, NVMFS5844NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 57 VGS = 0 V, VDS = 60 V mV/°C TJ = 25 °C 1 TJ = 125°C 100 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.5 2.3 6.2 VGS = 10 V ID = 10 A 10.2 12 VGS = 4.5 V ID = 10 A 13 16 gFS VDS = 5 V, ID = 10 A V mV/°C 27 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 1460 VGS = 0 V, f = 1 MHz, VDS = 25 V 150 pF 96 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 48 V; ID = 10 A Total Gate Charge QG(TOT) 15 Threshold Gate Charge QG(TH) 1.0 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 8.0 Plateau Voltage VGP 3.0 V Gate Resistance RG 0.62 W td(ON) 12 VGS = 4.5 V, VDS = 48 V; ID = 10 A 30 nC 4.0 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDS = 48 V, ID = 10 A, RG = 2.5 W tf 25 ns 20 10 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 10 A TJ = 25°C 0.79 TJ = 125°C 0.65 tRR ta tb 1.2 V 19 VGS = 0 V, dIS/dt = 100 A/ms, IS = 10 A QRR 13 6.0 15 5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns nC NTMFS5844NL, NVMFS5844NL TYPICAL CHARACTERISTICS 50 3.6 V 40 3.4 V 30 60 50 40 30 20 3.2 V 10 3.0 V 10 0 2.8 V 0 1 2 3 4 5 TJ = 25°C 20 TJ = 125°C 1 TJ = −55°C 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.030 ID = 10 A TJ = 25°C 0.025 0.020 0.015 0.010 0.005 VDS ≥ 10 V 70 2 4 6 8 10 12 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.016 TJ = 25°C 0.014 VGS = 4.5 V 0.012 VGS = 10 V 0.010 0.008 5 10 15 20 25 30 35 40 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.5 100,000 VGS = 0 V VGS = 10 V ID = 10 A 2 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 25°C 3.8 V 60 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 4.0 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 70 80 VGS = 5 V 10 V ID, DRAIN CURRENT (A) 80 10,000 1.5 1 0.5 −50 −25 0 25 50 75 100 125 150 175 TJ = 150°C 1,000 100 TJ = 125°C 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 60 NTMFS5844NL, NVMFS5844NL TYPICAL CHARACTERISTICS 10 VGS = 0 V TJ = 25°C 1600 C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V) 1800 1400 Ciss 1200 1000 800 600 400 Coss 200 0 Crss 0 10 20 30 40 50 60 IS, SOURCE CURRENT (A) t, TIME (ns) 2 0 VDS = 48 V ID = 10 A TJ = 25°C 0 5 10 15 20 25 Qg, TOTAL GATE CHARGE (nC) td(off) tf td(on) 10 1 10 100 30 VGS = 0 V TJ = 25°C 30 20 10 0 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 50 VGS = 10 V Single Pulse TC = 25°C 100 ms EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (A) Qgd Qgs 40 tr 10 ms 1 ms 10 10 ms 0.1 4 Figure 8. Gate−to−Source Voltage vs. Total Charge 100 1 6 DRAIN−TO−SOURCE VOLTAGE (V) VDD = 48 V ID = 10 A VGS = 4.5 V 100 8 Figure 7. Capacitance Variation 1000 1 QT RDS(on) Limit Thermal Limit Package Limit 0.1 dc 1 10 VDS, DRAISN VOLTAGE (V) 100 40 30 20 10 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 175 NTMFS5844NL, NVMFS5844NL TYPICAL CHARACTERISTICS RqJA(t) (°C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE 100 Duty Cycle = 0.5 10 0.2 0.1 1 0.05 0.02 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) Figure 13. Thermal Response http://onsemi.com 5 1 10 100 1000 NTMFS5844NL, NVMFS5844NL PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE G 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D 2 A B D1 2X 0.20 C 4X E1 2 3 q E 2 1 DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q c A1 4 TOP VIEW C 3X e 0.10 C SEATING PLANE DETAIL A A STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 0.10 C SIDE VIEW SOLDERING FOOTPRINT* DETAIL A 3X 8X 0.10 C A B 0.05 c 4X e/2 1 4 0.965 K G 0.750 1.000 L PIN 5 (EXPOSED PAD) 4X 1.270 b MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.15 BSC 4.50 4.90 5.10 3.50 −−− 4.22 6.15 BSC 5.50 5.80 6.10 3.45 −−− 4.30 1.27 BSC 0.51 0.61 0.71 1.20 1.35 1.50 0.51 0.61 0.71 0.05 0.17 0.20 3.00 3.40 3.80 0_ −−− 12 _ 1.330 2X 0.905 2X E2 L1 M 0.495 4.530 3.200 0.475 D2 2X BOTTOM VIEW 1.530 4.560 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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